E702336_SH7043 Renesas - Sh7043 Series Fp-144 User System Interface Cable
E702360_SH7058 Неопределенные - Regarding The Change Of Names Mentioned In The Document, Such As Hitachi Electric and Hitachi Xx, To Renesas Technology Corp.
EB1112H Stanley - PKG Type = Thin(2012/0805) ; Emitted Color = Blue ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 430 ; Luminous Intensity iv (mcd) Min = 3.8 ; Luminous Intensity iv (mcd) TYP = 6.4 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 150
EB1112HA Stanley - PKG Type = Thin(2012/0805) ; Emitted Color = Blue ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 430 ; Luminous Intensity iv (mcd) Min = 3.8 ; Luminous Intensity iv (mcd) TYP = 6.4 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 150
EB1112HB Stanley - PKG Type = Thin(2012/0805) ; Emitted Color = Blue ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 430 ; Luminous Intensity iv (mcd) Min = 3.8 ; Luminous Intensity iv (mcd) TYP = 6.4 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 150
EB1112HC Stanley - PKG Type = Thin(2012/0805) ; Emitted Color = Blue ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 430 ; Luminous Intensity iv (mcd) Min = 3.8 ; Luminous Intensity iv (mcd) TYP = 6.4 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 150
EB1112HD Stanley - PKG Type = Thin(2012/0805) ; Emitted Color = Blue ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 430 ; Luminous Intensity iv (mcd) Min = 3.8 ; Luminous Intensity iv (mcd) TYP = 6.4 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 150
EB1112HE Stanley - PKG Type = Thin(2012/0805) ; Emitted Color = Blue ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 430 ; Luminous Intensity iv (mcd) Min = 3.8 ; Luminous Intensity iv (mcd) TYP = 6.4 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 150
EB1112HF Stanley - PKG Type = Thin(2012/0805) ; Emitted Color = Blue ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 430 ; Luminous Intensity iv (mcd) Min = 3.8 ; Luminous Intensity iv (mcd) TYP = 6.4 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 150
EB-120 Неопределенные - 20w Class D Single Channel Audio Amplifier
EB2 NEC - Compact and Light Weight Surface Mounting Type
EB-2100 Неопределенные - Ddx All-digital, High Efficiency Evaluation Amplifier
EB-2100M Неопределенные - DDX All-Digital, High Efficiency Evaluation Amplifier
EB-2100S Неопределенные - DDX All-Digital, High Efficiency Evaluation Amplifier
EB-2100x Неопределенные - DDX All-Digital, High Efficiency Evaluation Amplifier
EB2-12 NEC - COMPACT and LIGHT WEIGHT SURFACE MOUNTING TYPE
EBE10AD4AGFA Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE10AD4AGFA-4A-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE10AD4AGFA-5C-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE10AD4AGFA-6E-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE10RD4ABFA Elpida - 1gb Registered Ddr2 Sdram Dimm (128m Words X 72 Bits, 1 Rank)
EBE11UD8ABFA-5C-E Elpida - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AEFA Elpida - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 64 Bits, 2 Ranks)
EBE11UD8AEFA-4A-E Elpida - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AEFA-5C-E Elpida - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AEFA-6 Elpida - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 64 Bits, 2 Ranks)
EBE11UD8AEFA-6E-E Elpida - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AESA Elpida - 1gb Ddr2 Sdram So-dimm (128m Words X 64 Bits, 2 Ranks)
EBE11UD8AESA-4A-E Elpida - 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AESA-5C-E Elpida - 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AESA-6E-E Elpida - 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AGFA Elpida - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 64 Bits, 2 Ranks)
EBE11UD8AGFA-4A-E Elpida - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AGFA-5C-E Elpida - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AGFA-6E-E Elpida - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AGSA Elpida - 1gb Ddr2 Sdram So-dimm (128m Words X 64 Bits, 2 Ranks)
EBE11UD8AGSA-4A-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE11UD8AGSA-5C-E Elpida - 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)
EBE11UD8AGSA-6E-E Elpida - 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)
EBE20AE4ABFA Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE20AE4ABFA-6E-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE20RE4AAFA Elpida - 2gb Registered Ddr2 Sdram Dimm (256m Words X 72 Bits, 1 Rank)
EBE20RE4AAFA-4A-E Elpida - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)
EBE20RE4AAFA-5C-E Elpida - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)
EBE20RE4ABFA Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE20RE4ABFA-4A-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE20RE4ABFA-5C-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE20RE4ABFA-6E-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE21AD4AGFB Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE21AD4AGFB-4A-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE21AD4AGFB-5C-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE21AD4AGFB-6E-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE21RD4ABHA Elpida - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
EBE21RD4ABHA-4A-E Elpida - 2gb Registered Ddr2 Sdram Dimm (256m Words X 72 Bits, 2 Ranks)
EBE21RD4ABHA-5C-E Elpida - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
EBE21RD4AEFA Elpida - 2gb Registered Ddr2 Sdram Dimm (256m Words X 72 Bits, 2 Ranks)
EBE21RD4AEFA-4A-E Elpida - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
EBE21RD4AEFA-5C-E Elpida - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
EBE21RD4AGFA Elpida - 2gb Registered Ddr2 Sdram Dimm (256m Words X 72 Bits, 2 Ranks)
EBE21RD4AGFA-4A-E Elpida - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
EBE21RD4AGFA-5C-E Elpida - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
EBE21RD4AGFA-6E-E Elpida - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
EBE21RD4AGFB Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE21RD4AGFB-4A-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE21RD4AGFB-5C-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE21RD4AGFB-6E-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE41RE4AAHA Elpida - 4gb Registered Ddr2 Sdram Dimm (512m Words X 72 Bits, 2 Ranks)
EBE41RE4AAHA-4A-E Elpida - 4GB Registered DDR2 SDRAM DIMM (512M words x 72 bits, 2 Ranks)
EBE41RE4AAHA-5C-E Elpida - 4GB Registered DDR2 SDRAM DIMM (512M words x 72 bits, 2 Ranks)
EBE41RE4ABHA Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE41RE4ABHA-4A-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE41RE4ABHA-5C-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE41RE4ABHA-6E-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE51AD8AGFA Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE51AD8AGFA-4A-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE51AD8AGFA-5C-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE51AD8AGFA-6E-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
EBE51ED8ABFA Elpida - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
EBE51ED8ABFA-4A-E Elpida - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8ABFA-5C-E Elpida - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8AEFA Elpida - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
EBE51ED8AEFA-4A-E Elpida - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8AEFA-5C-E Elpida - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8AEFA-6 Elpida - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
EBE51ED8AEFA-6E-E Elpida - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8AGFA Elpida - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
EBE51ED8AGFA-4A-E Elpida - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8AGFA-5C-E Elpida - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51ED8AGFA-6E-E Elpida - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8ABFA Elpida - 512mb Registered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
EBE51RD8ABFA-4A-E Elpida - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8ABFA-5C-E Elpida - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AEFA Elpida - 512mb Registered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
EBE51RD8AEFA-4A-E Elpida - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AEFA-5C-E Elpida - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AGFA Elpida - 512mb Registered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
EBE51RD8AGFA-4A-E Elpida - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AGFA-5C-E Elpida - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AGFA-6E-E Elpida - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51UD8ABFA Elpida - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 64 Bits, 1 Rank)
EBG5304S Stanley - PKG Type = 5 ; Emitted Color = Pure Green ; Lens Type = Clear ; Peak Wavelength λ P (nm) = 555 ; Luminous Intensity iv (mcd) Min = 50.0 ; Luminous Intensity iv (mcd) TYP = 80.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 20
EBG5305S Stanley - PKG Type = 5 ; Emitted Color = Pure Green ; Lens Type = Clear ; Peak Wavelength λ P (nm) = 555 ; Luminous Intensity iv (mcd) Min = 12.0 ; Luminous Intensity iv (mcd) TYP = 18.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 35
EBG5334S Stanley - PKG Type = 5 ; Emitted Color = Pure Green ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 555 ; Luminous Intensity iv (mcd) Min = 10.0 ; Luminous Intensity iv (mcd) TYP = 15.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 30
EBG5335S Stanley - PKG Type = 5 ; Emitted Color = Pure Green ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 555 ; Luminous Intensity iv (mcd) Min = 8.0 ; Luminous Intensity iv (mcd) TYP = 12.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 45
EBR3338S Stanley - PKG Type = 3 ; Emitted Color = Red ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 660 ; Luminous Intensity iv (mcd) Min = 30.0 ; Luminous Intensity iv (mcd) TYP = 45.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 25
EBR3361X Stanley - PKG Type = 3 ; Emitted Color = Red ; Lens Type = Clear ; Peak Wavelength λ P (nm) = 660 ; Luminous Intensity iv (mcd) Min = 12.0 ; Luminous Intensity iv (mcd) TYP = 18.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 100
EBR3368S Stanley - PKG Type = 3 ; Emitted Color = Red ; Lens Type = Clear ; Peak Wavelength λ P (nm) = 660 ; Luminous Intensity iv (mcd) Min = 80.0 ; Luminous Intensity iv (mcd) TYP = 120.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 15
EBR3371X Stanley - PKG Type = 3 ; Emitted Color = Red ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 660 ; Luminous Intensity iv (mcd) Min = 10.0 ; Luminous Intensity iv (mcd) TYP = 15.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 110
EBR3378S Stanley - PKG Type = 3 ; Emitted Color = Red ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 660 ; Luminous Intensity iv (mcd) Min = 30.0 ; Luminous Intensity iv (mcd) TYP = 45.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 20
EBR5304S Stanley - PKG Type = 5 ; Emitted Color = Red ; Lens Type = Clear ; Peak Wavelength λ P (nm) = 660 ; Luminous Intensity iv (mcd) Min = 80.0 ; Luminous Intensity iv (mcd) TYP = 160.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 15
EBR5305S Stanley - PKG Type = 5 ; Emitted Color = Red ; Lens Type = Clear ; Peak Wavelength λ P (nm) = 660 ; Luminous Intensity iv (mcd) Min = 20.0 ; Luminous Intensity iv (mcd) TYP = 30.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 50
EBR5334S Stanley - PKG Type = 5 ; Emitted Color = Red ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 660 ; Luminous Intensity iv (mcd) Min = 20.0 ; Luminous Intensity iv (mcd) TYP = 30.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 30
EBR5335S Stanley - PKG Type = 5 ; Emitted Color = Red ; Lens Type = Diffused ; Peak Wavelength λ P (nm) = 660 ; Luminous Intensity iv (mcd) Min = 12.0 ; Luminous Intensity iv (mcd) TYP = 18.0 ; Luminous Intensity iv (mcd) Max = 20 ; Viewing Angle (2 θ 1/2) = 45
EB-RD35 Gennum - Genlinx-tm Ii Eb-rd35 Evaluation Board
EClamp1002A Semtech - ESD/EMI Protection for Speaker Ports The EClamp1002A isA low pass filter array with integrated TVS diodes for ESD protection. It is designed to provide bidirectional filtering of EMI/RFI signals and electrostatic discharge (ESD) protection in portable electronic equipment.
EClamp1002A.TCT Semtech - ESD/EMI Protection for Speaker Ports The EClamp1002A isA low pass filter array with integrated TVS diodes for ESD protection. It is designed to provide bidirectional filtering of EMI/RFI signals and electrostatic discharge (ESD) protection in portable electronic equipment.
EClamp3202A Semtech - ESD/EMI Protection for Microphone Ports The EClamp™3202A isA low pass filter array with integrated TVS diodes for ESD protection. It is designed to provide bidirectional filtering of EMI/RFI signals and electrostatic discharge (ESD) protection in portable electronic equipment.
EClamp3202A.TCT Semtech - ESD/EMI Protection for Microphone Ports The EClamp™3202A isA low pass filter array with integrated TVS diodes for ESD protection. It is designed to provide bidirectional filtering of EMI/RFI signals and electrostatic discharge (ESD) protection in portable electronic equipment.