REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Serial-Port 16-Bit
SoundPort Stereo Codec
AD1847
Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Single-Chip Integrated
Digital Audio Stereo Codec
Supports the Microsoft Windows Sound System*
Multiple Channels of Stereo Input
Analog and Digital Signal Mixing
Programmable Gain and Attenuation
On-Chip Signal Filters
Digital Interpolation and Decimation
Analog Output Low-Pass
Sample Rates from 5.5 kHz to 48 kHz
44-Lead PLCC and TQFP Packages
Operation from +5 V Supplies
Serial Digital Interface Compatible with ADSP-21xx
Fixed-Point DSP
I
S
A
B
U
S
ASIC
AD1847
DSP
Figure 1. Example System Diagram
External circuit requirements are limited to a minimal number
of low cost support components. Anti-imaging DAC output
filters are incorporated on-chip. Dynamic range exceeds 70 dB
over the 20 kHz audio band. Sample rates from 5.5 kHz to
48 kHz are supported from external crystals.
The Codec includes a stereo pair of
analog-to-digital con-
verters (ADCs) and a stereo pair of
digital-to-analog con-
verters (DACs). Inputs to the ADC can be selected from four
stereo pairs of analog signals: line 1, line 2, auxiliary ("aux")
line #1, and post-mixed DAC output. A software-controlled
programmable gain stage allows independent gain for each
channel going into the ADC. The ADCs' output can be digitally
mixed with the DACs' input.
The pair of 16-bit outputs from the ADCs is available over a se-
rial interface that also supports 16-bit digital input to the DACs
and control/status information. The AD1847 can accept and
generate 16-bit twos-complement PCM linear digital data, 8-bit
unsigned magnitude PCM linear data, and 8-bit
-law or A-law
companded digital data.
(Continued on page 7)
FUNCTIONAL BLOCK DIAGRAM
ANALOG
I/O
L
R
DIGITAL
I/O
CRYSTALS
2
2
2
S
E
R
I
A
L
P
O
R
T
OSCILLATORS
2.25V
REFERENCE
L
R
L
R
CLOCK
OUT
ATTEN
DIGITAL
SUPPLY
ANALOG
SUPPLY
M
U
X
L
R
L
R
L
R
L
R
BUS
MASTER
TIME SLOT
INPUT
TIME SLOT
OUTPUT
SERIAL DATA
OUTPUT
SERIAL DATA
INPUT
EXTERNAL
CONTROL
SERIAL BIT
CLOCK
FRAME
SYNC
RESET
LINE 1
INPUT
LINE 2
INPUT
AUX 1
INPUT
LINE
OUTPUT
AUX 2
INPUT
AD1847
ATTEN/
MUTE
ATTEN
POWER
DOWN
/A
LAW
/A
LAW
ATTEN
D/A
CONVERTER
D/A
CONVERTER
/A
LAW
/A
LAW
GAIN
GAIN
A/D
CONVERTER
A/D
CONVERTER
GAIN/ATTEN/MUTE
GAIN/ATTEN
/MUTE
GAIN/ATTEN
/MUTE
ATTEN/
MUTE
PRODUCT OVERVIEW
The AD1847 SoundPort
Stereo Codec integrates key audio
data conversion and control functions into a single integrated
circuit. The AD1847 is intended to provide a complete, low
cost, single-chip solution for business, game audio and multi-
media applications requiring operation from a single +5 V sup-
ply. It provides a serial interface for implementation on a
computer motherboard, add-in or PCMCIA card. See Figure 1
for an example system diagram.
*Windows Sound System is a registered trademark of Microsoft Corp.
SoundPort is a registered trademark of Analog Devices, Inc.
STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED
Temperature
25
C
DAC Output Conditions
Digital Supply (V
DD
)
5.0
V
0 dB Attenuation
Analog Supply (V
CC
)
5.0
V
Full-Scale Digital Inputs
Word Rate (F
S
)
48
kHz
16-Bit Linear Mode
Input Signal
1007
Hz
No Output Load
Analog Output Passband
20
Hz to 20 kHz
Mute Off
FFT Size
4096
ADC Input Conditions
V
IH
2.4
V
0 dB Gain
V
IL
0.8
V
3.0 dB Relative to Full Scale
V
OH
2.4
V
Line Input
V
OL
0.4
V
16-Bit Linear Mode
ANALOG INPUT
Min
Typ
Max
Units
Full-Scale Input Voltage (RMS Values Assume Sine Wave Input)
Line1, Line2, AUX1, AUX2
1
V rms
2.54
2.8
3.10
V p-p
Input Impedance
Line1, Line2, AUX1, AUX2
10
k
Input Capacitance
15
pF
PROGRAMMABLE GAIN AMPLIFIER--ADC
Min
Typ
Max
Units
Step Size (All Steps Tested, 30 dB Input)
1.10
1.5
1.90
dB
PGA Gain Range Span
21.0
24.0
dB
AUXILIARY INPUT ANALOG AMPLIFIERS/ATTENUATORS
Min
Typ
Max
Units
Step Size (+12 dB to 28.5 dB, Referenced to DAC Full Scale)
1.3
1.5
1.7
dB
(30 dB to 34.5 dB, Referenced to DAC Full Scale)
1.1
1.5
1.9
dB
Input Gain/Attenuation Range Span
45.5
47.5
dB
AUX Input Impedance
10
k
DIGITAL DECIMATION AND INTERPOLATION FILTERS
Min
Max
Units
Passband
0
0.4 F
S
Hz
Passband Ripple
0.1
+0.1
dB
Transition Band
0.4 F
S
0.6 F
S
Hz
Stopband
0.6 F
S
Hz
Stopband Rejection
74
dB
Group Delay
30/F
S
Group Delay Variation Over Passband
0
s
REV. B
AD1847SPECIFICATIONS
2
ANALOG-TO-DIGITAL CONVERTERS
Min
Typ
Max
Units
Resolution
16
Bits
Dynamic Range (60 dB Input, THD+N Referenced to Full Scale, A-Weighted)
70
dB
THD+N (Referenced to Full Scale)
0.040
%
68
dB
Signal-to-Intermodulation Distortion
83
dB
ADC Crosstalk
Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)
80
dB
Line1 to Line2 (Input Line1, Ground and Select Line2, Read Both Channels)
80
dB
Line to AUX1
80
dB
Line to AUX2
80
dB
Line to DAC
80
dB
Gain Error (Full-Scale Span Relative to V
REFI
)
10
%
Interchannel Gain Mismatch (Difference of Gain Errors)
0.2
dB
DC Offset
55
LSB
DIGITAL-TO-ANALOG CONVERTERS
Min
Typ
Max
Units
Resolution
16
Bits
Dynamic Range (60 dB Input, THD+N Referenced to Full Scale, A-Weighted)
76
dB
THD+N (Referenced to Full Scale)
0.025
%
72
dB
Signal-to-Intermodulation Distortion
86
dB
Gain Error (Full-Scale Span Relative to V
REFI
)
10
%
Interchannel Gain Mismatch (Difference of Gain Errors)
0.2
dB
DAC Crosstalk (Input L, Zero R, Measure R_OUT; Input R, Zero L, Measure L_OUT)
80
dB
Total Out-of-Band Energy (Measured from 0.6 F
S
to 100 kHz)
50
dB
Audible Out-of-Band Energy (Measured from 0.6 F
S
to 22 kHz, Tested at F
S
= 5.5 kHz)
55
dB
DAC ATTENUATOR
Min
Typ
Max
Units
Step Size (0 dB to 22.5 dB) (Tested at Steps 0 dB, 19.5)
1.3
1.5
1.7
dB
Step Size (24 dB to 94 dB)
1.0
1.5
2.0
dB
Output Attenuation Range Span
93
95
dB
DIGITAL MIX ATTENUATOR
Min
Typ
Max
Units
Step Size (0 dB to 22.5 dB) (Tested at Steps 0 dB, 19.5)
1.3
1.5
1.7
dB
Step Size (24 dB to 94 dB)
1.0
1.5
2.0
dB
Output Attenuation Range Span
93.5
95.5
dB
ANALOG OUTPUT
Min
Typ
Max
Units
Full-Scale Line Output Voltage
0.707
V rms
V
REFI
= 2.35*
1.80
2
2.20
V p-p
Line Output Impedance
600
External Load Impedance
10
k
Output Capacitance
15
pF
External Load Capacitance
100
pF
V
REF
(Clock Running)
2.00
2.50
V
V
REF
Current Drive
100
A
V
REFI
2.35
V
Mute Attenuation of 0 dB
80
dB
Fundamental (LOUT)
Mute Click
8
mV
(|Muted Output Minus Unmuted
Midscale DAC Output|)
*Full-scale line output voltage scales with V
REF
(e.g., V
OUT
(typ) 2.0 V (V
REF
/2.35)).
Guaranteed, Not Tested.
REV. B
3
AD1847
AD1847
REV. B
4
SYSTEM SPECIFICATIONS
Min
Typ
Max
Units
System Frequency Response
0.3
dB
(Line In to Line Out, 20 Hz to 20 kHz)
Differential Nonlinearity
1/2
Bit
Phase Linearity Deviation
1
Degrees
STATIC DIGITAL SPECIFICATIONS
Min
Max
Units
High Level Input Voltage (V
IH
)
Digital Inputs
2.0
V
XTAL1/2I
2.4
V
Low Level Input Voltage (V
IL
)
0.8
V
High Level Output Voltage (V
OH
) I
OH
= 1 mA
2.4
V
DD
V
Low Level Output Voltage (V
OL
) I
OL
= 4 mA
0.4
V
Input Leakage Current (GO/NOGO Tested)
10
+10
A
Output Leakage Current (GO/NOGO Tested)
10
+10
A
TIMING PARAMETERS (Guaranteed Over Operating Temperature Range)
Min
Typ
Max
Units
Serial Frame Sync Period (t
1
)
1/0.5 F
S
s
Clock to Frame Sync [SDFS] Propagation Delay (t
PD1
)
20
ns
Data Input Setup Time (t
S
)
15
ns
Data Input Hold Time (t
H
)
15
ns
Clock to Output Data Valid (t
DV
)
25
ns
Clock to Output Three-State [High-Z] (t
HZ
)
20
ns
Clock to Time Slot Output [TSO] Propagation Delay (t
PD2
)
20
ns
RESET
and PWRDOWN Lo Pulse Width (t
RPWL
)
100
ns
POWER SUPPLY
Min
Max
Units
Power Supply Range Digital & Analog
4.75
5.25
V
Power Supply Current Operating (10 k
Line Out Load)
140
mA
Analog Supply Current Operating (10 k
Line Out Load)
70
mA
Digital Supply Current Operating (10 k
Line Out Load)
70
mA
Analog Power Supply Current Power Down
400
A
Digital Power Supply Current Power Down
400
A
Power Dissipation Operating (Current Nominal Supply)
750
mW
Power Dissipation Power Down (Current Nominal Supply)
4
mW
Power Supply Rejection (@ 1 kHz)
(At Both Analog and Digital Supply Pins, ADCs)
45
dB
(At Both Analog and Digital Supply Pins, DACs)
55
dB
CLOCK SPECIFICATIONS
Min
Max
Units
Input Clock Frequency
27
MHz
Recommended Clock Duty Cycle
10
%
Initialization/Sample Rate Change Time
16.9344 MHz Crystal Selected at Power-Up
171
ms
24.576 MHz Crystal Selected at Power-Up
171
ms
16.9344 MHz Crystal Selected Subsequently
6
ms
24.576 MHz Crystal Selected Subsequently
6
ms
Guaranteed, not tested.
Specifications subject to change without notice.
AD1847
REV. B
5
ABSOLUTE MAXIMUM RATINGS*
Min Max
Units
Power Supplies
Digital (V
DD
)
0.3 6.0
V
Analog (V
CC
)
0.3 6.0
V
Input Current
(Except Supply Pins)
10.0
mA
Analog Input Voltage (Signal Pins) 0.3 (VA+) + 0.3
V
Digital Input Voltage (Signal Pins) 0.3 (VD+) + 0.3
V
Ambient Temperature (Operating) 0
+70
C
Storage Temperature
65
+150
C
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option*
AD1847JP
0
C to +70
C
44-Lead PLCC
P-44A
AD1847JST
0
C to +70
C
44-Lead TQFP
ST-44
*P = PLCC; ST = TQFP.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1847 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
44-Lead PLCC
44-Lead TQFP
R_LINE2
RFILT
L_LINE2
L_LINE1
GNDA
GNDA
LFILT
L_AUX1
R_AUX1
R_OUT
V
CC
SDFS
SDO
V
DD
SCLK
CLKOUT
SDI
GNDD
XTAL2I
XTAL1O
XTAL1I
XTAL2O
V
DD
GNDD
GNDD
V
DD
BM
XCTL1
XCTL0
R_AUX2
L_OUT
N/C
L_AUX2
44
1
2
6
4
5
21
24
23
22
18
20
19
39
38
35
34
33
37
36
3
7
8
11
12
13
9
10
40
41
42
25
28
27
26
43
31
30
29
32
15
16
17
14
Top View
(Not to Scale)
AD1847JP
TSO
TSI
RESET
PWRDOWN
V
CC
V
DD
GNDD
V
REFI
V
REF
R_LINE1
GNDA
N/C = NO CONNECT
44 SDFS
43 SDO
42 SDI
41 GNDD
40 V
DD
39 SCLK
38 CLKOUT
37 XTAL2O
36 XTAL2I
35 XTAL1O
34 XTAL1I
33
32
31
30
29
28
27
26
25
24
23
PIN 1 IDENTIFIER
R_LINE1
V
REF
V
REFI
GNDA
V
CC
PWRDOWN
RESET
GNDD
V
DD
TSI
TSO
1
2
3
4
5
6
7
8
9
11
10
V
DD
GNDD
XCTL1
XCTL0
GNDD
V
DD
BM
L_AUX2
R_AUX2
L_OUT
N/C
R_LINE2 12
RFILT 13
GNDA 14
LFILT 15
L_LINE2 16
L_LINE1 17
GNDA 18
L_AUX1 20
R_AUX1 21
R_OUT 22
V
CC
19
Top View
(Not to Scale)
AD1847JST
N/C = NO CONNECT
PINOUTS
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