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Электронный компонент: AD5203AN100

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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD5203
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
4-Channel, 64-Position
Digital Potentiometer
FUNCTIONAL BLOCK DIAGRAM
SHDN
DAC 1
A1
W1
B1
AGND1
6
V
DD
DGND
SDI
CLK
CS
AD5203
SDO
SHDN
A2
W2
B2
AGND2
A3
W3
B3
AGND3
A4
W4
B4
AGND4
6
2
RS
6-BIT
LATCH
CK
RS
6
6-BIT
LATCH
CK
RS
SHDN
DAC 2
SHDN
DAC 3
6
6
SHDN
DAC 4
6-BIT
LATCH
CK
RS
6-BIT
LATCH
CK
RS
DAC
SELECT
A1, A0
1
2
3
4
8-BIT
SERIAL
LATCH
D
CK Q
RS
FEATURES
64 Position
Replaces Four Potentiometers
10 k , 100 k
Power Shutdown--Less than 5 A
3-Wire SPI-Compatible Serial Data Input
10 MHz Update Data Loading Rate
+2.7 V to +5.5 V Single Supply Operation
Midscale Preset
APPLICATIONS
Mechanical Potentiometer Replacement
Programmable Filters, Delays, Time Constants
Volume Control, Panning
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD5203 provides a quad channel, 64-position digitally-
controlled variable resistor (VR) device. These parts perform the
same electronic adjustment function as a potentiometer or vari-
able resistor. The AD5203 contains four independent variable
resistors in a 24-lead SOIC and the compact TSSOP-24 pack-
ages. Each part contains a fixed resistor with a wiper contact
that taps the fixed resistor value at a point determined by a digi-
tal code loaded into the controlling serial input register. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code transferred
into the VR latch. Each variable resistor offers a completely
programmable value of resistance, between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 10 k
, or 100 k
has a
1% channel-to-
channel matching tolerance with a nominal temperature coeffi-
cient of 700 ppm/
C.
Each VR has its own VR latch which holds its programmed
resistance value. These VR latches are updated from an internal
serial-to-parallel shift register that is loaded from a standard
3-wire serial-input digital interface. Eight data bits make up the
data word clocked into the serial input register. The data word is
decoded where the first two bits determine the address of the VR
latch to be loaded, the last 6-bits are data. A serial data output
pin at the opposite end of the serial register allows simple daisy-
chaining in multiple VR applications without additional external
decoding logic.
The reset
RS pin forces the wiper to the midscale position by
loading 20
H
into the VR latch. The
SHDN pin forces the resis-
tor to an end-to-end open circuit condition on terminal A and
shorts the wiper to terminal B, achieving a microwatt power
shutdown state. When shutdown is returned to logic-high the
previous latch settings put the wiper in the same resistance set-
ting prior to shutdown.
The AD5203 is available in a narrow body P-DIP-24, the
24-lead surface mount package, and the compact 1.1 mm thin
TSSOP-24 package. All parts are guaranteed to operate over the
extended industrial temperature range of 40
C to +85
C.
For pin compatible higher resolution applications, see the 256-
position AD8403 product.
2
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AD5203SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
2
R-DNL
R
WB
, V
A
= No Connect
0.25
0.1
+0.25
LSB
Resistor Nonlinearity Error
2
R-INL
R
WB
, V
A
= No Connect
0.5
0.1
+0.5
LSB
Nominal Resistor Tolerance
3
R
AB
30
+30
%
Resistance Temperature Coefficient
R
AB
/
T
V
AB
= V
DD
, Wiper = No Connect
700
ppm/
C
Wiper Resistance
R
W
I
W
= 1 V/R
AB
45
100
Nominal Resistance Match
R/R
O
CH 1 to CH 2,
V
AB
= V
DD
, T
A
= +25
C
0.2
1
%
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution
N
6
Bits
Differential Nonlinearity Error
4
DNL
0.25
0.1
+0.25
LSB
Integral Nonlinearity Error
4
INL
0.75
0.1
+0.75
LSB
Voltage Divider Temperature Coefficient
V
W
/
T
Code = 20
H
20
ppm/
C
Full-Scale Error
V
WFSE
Code = 3F
H
0.75
0.2
0
LSB
Zero-Scale Error
V
WZSE
Code = 00
H
0
+0.1
+0.75
LSB
RESISTOR TERMINALS
Voltage Range
5
V
A,
V
B,
V
W
0
V
DD
V
Capacitance
6
Ax, Bx
C
A,
C
B
f = 1 MHz, Measured to GND, Code = 20
H
75
pF
Capacitance
6
Wx
C
W
f = 1 MHz, Measured to GND, Code = 20
H
120
pF
Shutdown Supply Current
7
I
A_SD
V
A
= V
DD
, V
B
= 0 V,
SHDN = 0
0.01
5
A
Shutdown Wiper Resistance
R
W_SD
V
A
= V
DD
, V
B
= 0 V,
SHDN = 0, V
DD
= +5 V
45
100
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD
= +5 V
2.4
V
Input Logic Low
V
IL
V
DD
= +5 V
0.8
V
Input Logic High
V
IH
V
DD
= +3 V
2.1
V
Input Logic Low
V
IL
V
DD
= +3 V
0.6
V
Output Logic High
V
OH
R
L
= 2.2 k
to V
DD
V
DD
0.1
V
Output Logic Low
V
OL
I
OL
= 1.6 mA, V
DD
= +5 V
0.4
V
Input Current
I
IL
V
IN
= 0 V or +5 V, V
DD
= +5 V
1
A
Input Capacitance
6
C
IL
5
pF
POWER SUPPLIES
Power Supply Range
V
DD
Range
2.7
5.5
V
Supply Current (CMOS)
I
DD
V
IH
= V
DD
or V
IL
= 0 V
0.01
5
A
Supply Current (TTL)
8
I
DD
V
IH
= 2.4 V or V
IL
= 0.8 V, V
DD
= +5.5 V
0.9
4
mA
Power Dissipation (CMOS)
9
P
DISS
V
IH
= V
DD
or V
IL
= 0 V, V
DD
= +5.5 V
27.5
W
Power Supply Sensitivity
PSS
V
DD
= +5 V
10%
0.0002
0.001
%/%
PSS
V
DD
= +3 V
10%
0.006
0.03
%/%
DYNAMIC CHARACTERISTICS
6, 10
Bandwidth 3 dB
BW_10K
R
AB
= 10 k
600
kHz
BW_100K
R
AB
= 100 k
71
kHz
Total Harmonic Distortion
THD
W
V
A
=1 V rms + 2 V dc, V
B
= 2 V dc, f = 1 kHz
0.003
%
V
W
Settling Time
t
S
_10K
V
A
= V
DD
, V
B
= 0 V,
1 LSB Error Band
2
s
t
S
_100K
V
A
= V
DD
, V
B
= 0 V,
1 LSB Error Band
18
s
Resistor Noise Voltage
e
NWB
R
WB
= 5 k
, f = 1 kHz,
RS = 0
9
nV/
Hz
R
WB
= 50 k
, f = 1 kHz,
RS = 0
29
nV/
Hz
Crosstalk
11
C
T
V
A
= V
DD
, V
B
= 0 V
65
dB
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
6, 12
Input Clock Pulsewidth
t
CH
, t
CL
Clock Level High or Low
10
ns
Data Setup Time
t
DS
5
ns
Data Hold Time
t
DH
5
ns
CLK to SDO Propagation Delay
13
t
PD
R
L
= 2.2 k
, C
L
< 20 pF
1
25
ns
CS Setup Time
t
CSS
10
ns
CS High Pulsewidth
t
CSW
10
ns
Reset Pulsewidth
t
RS
50
ns
CLK Fall to
CS Rise Hold Time
t
CSH
0
ns
CS Rise to Clock Rise Setup
t
CS1
10
ns
(V
DD
= +3 V 10% or +5 V 10%, V
A
= +V
DD
, V
B
= 0 V, 40 C < T
A
< +85 C unless
otherwise noted)
3
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AD5203
NOTES
1
Typicals represent average readings at +25
C and V
DD
= +5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27 test circuit. I
W
= V
DD
/R
for both V
DD
= +3 V or V
DD
= +5 V.
3
V
AB
= V
DD
, Wiper (V
W
) = No connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of
1 LSB maximum are guaranteed monotonic operating conditions. See Figure 26 test circuit.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the AX terminals. All AX terminals are open-circuited in shutdown mode.
8
Worst case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. See Figure 19 for a plot of I
DD
vs. logic voltage
inputs result in minimum power dissipation.
9
P
DISS
is calculated from (I
DD
V
DD
). CMOS logic level inputs result in minimum power dissipation.
10
All dynamic characteristics use V
DD
= +5 V.
11
Measured at a V
W
pin where an adjacent V
W
pin is making a full-scale voltage change.
12
See timing diagrams for location of measured values. All input control voltages are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V
DD
= +3 V or +5 V. Input logic should have a 1 V/
s minimum slew rate.
13
Propagation delay depends on value of V
DD
, R
L
and C
L
. See Operation section.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25
C, unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +8 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
DD
I
AB
, I
AW
, I
BW
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 mA
Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V
Operating Temperature Range . . . . . . . . . . . 40
C to +85
C
Maximum Junction Temperature (T
J
MAX) . . . . . . . . +150
C
Storage Temperature . . . . . . . . . . . . . . . . . . 65
C to +150
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300
C
Package Power Dissipation . . . . . . . . . . . . . . (T
J
maxT
A
)/
JA
Thermal Resistance
JA
P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
C/W
SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
C/W
TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
C/W
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Table I. Serial-Data Word Format
ADDR
DATA
B7
B6
B5
B4
B3
B2
B1
B0
A1
A0
D5
D4
D3
D2
D1
D0
MSB
LSB
MSB
LSB
2
7
2
6
2
5
2
0
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5203 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
SDI
CLK
CS
V
OUT
1
0
1
0
1
0
V
DD
0V
D0
D1
D2
D3
D4
D5
A0
A1
DAC REGISTER LOAD
Figure 1a. Timing Diagram
CLK
V
OUT
1
0
1
0
1
0
V
DD
0V
SDI
(DATA IN)
SDO
(DATA OUT)
CS
1
0
Ax OR Dx
Ax OR Dx
A'x OR D'x
t
DS
t
DH
t
PD MAX
t
PD MIN
t
CH
t
CS1
t
CL
t
CSS
t
CSH
1 LSB
1 LSB ERROR BAND
t
CSW
t
S
A'x OR D'x
Figure 1b. Detail Timing Diagram
V
OUT
V
DD
0V
RS
1
0
1 LSB
1 LSB ERROR BAND
t
S
t
RS
Figure 1c. Reset Timing Diagram
AD5203
4
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PIN FUNCTION DESCRIPTIONS
Pin
No.
Name
Description
1
AGND2
Analog Ground #2*
2
B2
B Terminal RDAC #2
3
A2
A Terminal RDAC #2
4
W2
Wiper RDAC #2, addr = 01
2
5
AGND4
Analog Ground #4*
6
B4
B Terminal RDAC #4
7
A4
A Terminal RDAC #4
8
W4
Wiper RDAC #4, addr = 11
2
9
DGND
Digital Ground*
10
SHDN
Active Low Input. Terminal A open circuit.
Shutdown controls Variable Resistors #1
through #4.
11
CS
Chip Select Input, Active Low. When
CS
returns high data in the serial input register
is decoded based on the address bits and
loaded into the target DAC register.
12
SDI
Serial Data Input
13
SDO
Serial Data Output. Open drain transistor
requires pull-up resistor.
14
CLK
Serial Clock Input, positive edge triggered.
15
RS
Active low reset to midscale; sets RDAC
registers to 20
H
.
16
V
DD
Positive power supply, specified for opera-
tion at both +3 V and +5 V.
17
AGND3
Analog Ground #3*
18
W3
Wiper RDAC #3, addr =10
2
19
A3
A Terminal RDAC #3
20
B3
B Terminal RDAC #3
21
AGND1
Analog Ground #1*
22
W1
Wiper RDAC #1, addr = 00
2
23
A1
A Terminal RDAC #1
24
B1
B Terminal RDAC #1
*All AGNDs must be connected to DGND voltage potential.
ORDERING GUIDE
Model
k
Temperature Range
Package Descriptions
Package Options
AD5203AN10
10
40
C to +85
C
24-Lead Narrow Body Plastic DIP
N-24
AD5203AR10
10
40
C to +85
C
24-Lead Wide Body (SOIC)
SOL-24
AD5203ARU10
10
40
C to +85
C
24-Lead Thin Surface Mount Package (TSSOP)
RU-24
AD5203AN100
100
40
C to +85
C
24-Lead Narrow Body Plastic DIP
N-24
AD5203AR100
100
40
C to +85
C
24-Lead Wide Body (SOIC)
SOL-24
AD5203ARU100
100
40
C to +85
C
24-Lead Thin Surface Mount Package (TSSOP)
RU-24
PIN CONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5203
SDI
CS
SHDN
DGND
W4
AGND2
B2
A2
W2
A4
B4
AGND4
SDO
CLK
RS
V
DD
AGND3
B1
A1
W1
AGND1
W3
A3
B3
(Not to Scale)
AD5203
5
REV. 0
Typical Performance Characteristics
CODE Decimal
RESISTANCE k
10
0
0
8
64
16
24
32
40
48
56
9
6
5
3
1
8
7
4
2
V
DD
= +3V, OR +5V
R
AB
= 10k
R
WB
R
WA
Figure 2. Wiper to End Terminal
Resistance vs. Code
WIPER RESISTANCE
FREQUENCY
80
60
0
30
31 32
33
34
35
36
37 38
39
40
20
SS = 544 UNITS
V
DD
= +4.5V
T
A
= +25 C
Figure 5. Wiper-Contact-Resistance
Histogram
DIGITAL INPUT CODE Decimal
DNL ERROR LSB
0.25
0.25
0
8
64
16
24
32
40
48
56
0.2
0.05
0
0.1
0.2
0.15
0.1
0.05
0.15
V
DD
= +3.0V
T
A
= +25 C, +85 C, 40 C
Figure 8. Potentiometer Divider
Differential Nonlinearity Error vs.
Code
05
H
I
WA
CURRENT mA
V
WB
VOLTAGE V
5
0
0
1
7
2
3
4
5
6
4.5
2
1.5
1
0.5
3.5
2.5
4
3
R
AB
= 10k
V
DD
= +5V
T
A
= +25 C
3F
H
20
H
10
H
08
H
02
H
Figure 3. Resistance Linearity vs.
Conduction Current
TEMPERATURE C
NOMINAL RESISTANCE k
12
0
75 50
125
25
0
25
50
75
100
10
8
6
4
2
AD5203-10K VERSION
R
AB
(END-TO-END)
R
WB
(WIPER-TO-END)
CODE = 20
H
Figure 6. Nominal Resistance vs.
Temperature
CODE Decimal
POTENTIOMETER MODE TEMPCO ppm/
C 50
0
0
8
64
16
24
32
40
48
56
30
40
20
10
V
DD
= +3.0V
T
A
= 40 C/+85 C
V
A
= +2.0V
V
B
= 0V
Figure 9.
V
WB
/
T Potentiometer
Mode Tempco
DIGITAL INPUT CODE Decimal
R
INL
ERROR LSB
0.25
0.25
0
8
64
16
24
32
40
48
56
0.2
0.05
0
0.1
0.2
0.15
0.1
0.05
0.15
V
DD
= +3.0V
T
A
= 55 C
T
A
= +85 C
T
A
= +25 C
Figure 4. Resistance Step Position
Nonlinearity Error vs. Code
DIGITAL INPUT CODE Decimal
INL NONLINEARITY ERROR LSB
0.25
0.25
0
8
64
16
24
32
40
48
56
0.2
0.05
0
0.1
0.2
0.15
0.1
0.05
0.15
55 C
+85 C
+25 C
V
DD
= +3.0V
Figure 7. Potentiometer Divider
Nonlinearity Error vs. Code
CODE Decimal
RHEOSTAT MODE TEMPCO ppm
/
C
120
0
0
8
64
16
24
32
40
48
56
80
100
60
40
20
V
DD
= +3.0V
T
A
= 40 C/+85 C
V
A
= NO CONNECT
R
WB
MEASURED
Figure 10.
R
WB
/
T Rheostat Mode
Tempco