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Электронный компонент: AD5232BRU50

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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD5232
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
*
8-Bit Dual Nonvolatile Memory
Digital Potentiometer
FEATURES
Nonvolatile Memory Preset Maintains Wiper Settings
Dual Channel, 256-Position Resolution
Full Monotonic Operation DNL < 1 LSB
10 k , 50 k , 100 k Terminal Resistance
Linear or Log Taper Settings
Push-Button Increment/Decrement Compatible
SPI-Compatible Serial Data Input with Readback
Function
3 V to 5 V Single Supply or 2.5 V Dual Supply
Operation
14 Bytes of User EEMEM Nonvolatile Memory for
Constant Storage
Permanent Memory Write Protection
100-Year Typical Data Retention T
A
= 55 C
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
DIP Switch Setting
GENERAL DESCRIPTION
The AD5232 device provides a nonvolatile, dual-channel,
digitally controlled variable resistor (VR) with 256-position
resolution. These devices perform the same electronic adjust-
ment function as a potentiometer or variable resistor. The
AD5232's versatile programming via a microcontroller allows
multiple modes of operation and adjustment.
In the direct program mode a predetermined setting of the RDAC
register can be loaded directly from the microcontroller.
Another key mode of operation allows the RDAC register to be
refreshed with the setting previously stored in the EEMEM
register. When changes are made to the RDAC register to estab-
lish a new wiper position, the value of the setting can be saved
into the EEMEM by executing an EEMEM save operation.
Once the settings are saved in the EEMEM register these values
will be automatically transferred to the RDAC register to set the
wiper position at system power ON. Such operation is enabled
by the internal preset strobe and the preset can also be accessed
externally.
All internal register contents can be read out of the serial data
output (SDO). This includes the RDAC1 and RDAC2 registers,
the corresponding nonvolatile EEMEM1 and EEMEM2 regis-
ters, and the 14 spare USER EEMEM registers available for
constant storage.
*Patent pending.
FUNCTIONAL BLOCK DIAGRAM
RDAC1
REGISTER
EEMEM1
RDAC2
REGISTER
EEMEM
CONTROL
14 BYTES
USER EEMEM
EEMEM2
AD5232
RDAC1
RDAC2
CS
CLK
WP
PR
SDI
GND
SDO
RDY
SDO
SERIAL
INTERFACE
ADDR
DECODE
V
DD
V
SS
A1
W1
B1
A2
W2
B2
SDI
The basic mode of adjustment is the increment and decrement
command controlling the present setting of the Wiper position
setting (RDAC) register. An internal scratch pad RDAC register
can be moved UP or DOWN one step of the nominal terminal
resistance between terminals A and B. This linearly changes the
wiper to B terminal resistance (R
WB
) by one position segment of
the devices' end-to-end resistance (R
AB
). For exponential/loga-
rithmic changes in wiper setting, a left/right shift command
adjusts levels in
6 dB steps, which can be useful for audio and
light alarm applications.
The AD5232 is available in a thin TSSOP-16 package. All parts
are guaranteed to operate over the extended industrial tempera-
ture range of 40
C to +85
C. An evaluation board is available,
Part Number: AD5232EVAL.
CODE Decimal
100
75
0
0
256
64
PERCENT OF NOMINAL
END-T
O
-END RESIST
ANCE % R
AB
128
192
50
25
R
WB
R
WA
Figure 1. Symmetrical RDAC Operation
REV. 0
2
AD5232SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, 10 k , 50 k , 100 k VERSIONS
( V
DD
= 3 V 10% or 5 V 10% and V
SS
= 0 V, V
A
= +V
DD
, V
B
= 0 V, 40 C < T
A
< +85 C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Unit
DC CHARACTERISTICS
RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
= NC
1
1/2
+1
LSB
Resistor Nonlinearity
2
R-INL
R
WB
, V
A
= NC
0.4
+0.4
% FS
Nominal Resistor Tolerance
R
AB
40
+20
%
Resistance Temperature Coefficient
R
AB
/ T
600
ppm/
C
Wiper Resistance
R
W
I
W
= 100
A, V
DD
= 5.5 V, Code = 1E
H
5
100
R
W
I
W
= 100
A, V
DD
= 3 V, Code = 1E
H
200
POTENTIOMETER DIVIDER MODE -- Specifications Apply to All VRs
Resolution
N
8
Bits
Differential Nonlinearity
3
DNL
1
1/2
+1
LSB
Integral Nonlinearity
3
INL
0.4
+0.4
% FS
Voltage Divider Temperature Coefficient
V
W
/ T
Code = Half-Scale
15
ppm/
C
Full-Scale Error
V
WFSE
Code = Full-Scale
3
0
% FS
Zero-Scale Error
V
WZSE
Code = Zero-Scale
0
+3
% FS
RESISTOR TERMINALS
Terminal Voltage Range
4
V
A,B,W
V
SS
V
DD
V
Capacitance
5
Ax, Bx
C
A,B
f = 1 MHz, Measured to GND,
Code = Half-Scale
45
pF
Capacitance
5
Wx
C
W
f = 1 MHz, Measured to GND,
Code = Half-Scale
60
pF
Common-Mode Leakage Current
5, 6
I
CM
V
W
= V
DD
/2
0.01
1
A
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
With Respect to GND, V
DD
= 5 V
2.4
V
Input Logic Low
V
IL
With Respect to GND, V
DD
= 5 V
0.8
V
Input Logic High
V
IH
With Respect to GND, V
DD
= 3 V
2.1
V
Input Logic Low
V
IL
With Respect to GND, V
DD
= 3 V
0.6
V
Input Logic High
V
IH
With Respect to GND, V
DD
= +2.5 V, 2.0
V
V
SS
= 2.5 V
Input Logic Low
V
IL
With Respect to GND, V
DD
= +2.5 V,
0.5
V
V
SS
= 2.5 V
Output Logic High (SDO and RDY)
V
OH
R
PULL-UP
= 2.2 k
to 5 V
4.9
V
Output Logic Low
V
OL
I
OL
= 1.6 mA, V
LOGIC
= 5 V
0.4
V
Input Current
I
IL
V
IN
= 0 V or V
DD
2.5
A
Input Capacitance
5
C
IL
4
pF
POWER SUPPLIES
Single-Supply Power Range
V
DD
V
SS
= 0 V
2.7
5.5
V
Dual-Supply Power Range
V
DD
/V
SS
2.25
2.75 V
Positive Supply Current
I
DD
V
IH
= V
DD
or V
IL
= GND
3.5
10
A
Programming Mode Current
I
DD(PG)
V
IH
= V
DD
or V
IL
= GND
35
mA
Read Mode Current
7
I
DD(XFR)
V
IH
= V
DD
or V
IL
= GND
0.9
3
9
mA
Negative Supply Current
I
SS
V
IH
= V
DD
or V
IL
= GND,
V
DD
= +2.5 V, V
SS
= 2.5 V
3.5
10
A
Power Dissipation
8
P
DISS
V
IH
= V
DD
or V
IL
= GND
0.018
0.05
mW
Power Supply Sensitivity
5
PSS
V
DD
= 5 V
10%
0.002
0.01
%/%
3
REV. 0
nV/
Hz
Parameter
Symbol
Conditions
Min
Typ
1
Max Unit
DYNAMIC CHARACTERISTICS
5, 9
Bandwidth
3 dB, BW_10 k
, R = 10 k
500
kHz
Total Harmonic Distortion
THD
W
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz,
R
AB
= 10 k
0.022
%
THD
W
V
A
=1 V rms, V
B
= 0 V, f = 1 kHz,
R
AB
= 50 k
, 100 k
0.045
%
V
W
Settling Time
t
S
V
DD
= 5 V, V
SS
= 0 V, V
A
= V
DD
, V
B
= 0 V,
V
W
= 0.50% Error Band, Code 00
H
to
80
H
For R
AB
= 10 k
/50 k
/100 k
0.65/3/6
s
Resistor Noise Voltage
e
N_WB
R
WB
= 5 k
, f = 1 kHz
9
Crosstalk (C
W1
/C
W2
)
C
T
V
A
= V
DD
, V
B
= 0 V, Measure V
W
with
Adjacent VR Making Full-Scale Code Change
5
nV-s
Analog Crosstalk (C
W1
/C
W2
)
C
TA
V
A1
= V
DD
, V
B1
= 0 V, Measure V
W1
with V
W2
= 5 V p-p @ f = 10 kHz,
Code
1
= 80
H
;
Code
2
= FF
H
70
dB
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
5, 10
Clock Cycle Time (t
CYC
)
t
1
20
ns
CS Setup Time
t
2
10
ns
CLK Shutdown Time to
CS Rise
t
3
1
t
CYC
Input Clock Pulsewidth
t
4
, t
5
Clock Level High or Low
10
ns
Data Setup Time
t
6
From Positive CLK Transition
5
ns
Data Hold Time
t
7
From Positive CLK Transition
5
ns
CS to SDO-SPI Line Acquire
t
8
40
ns
CS to SDO-SPI Line Release
t
9
50
ns
CLK to SDO Propagation Delay
11
t
10
R
P
= 2.2 k
, C
L
< 20 pF
50
ns
CLK to SDO Data Hold Time
t
11
R
P
= 2.2 k
, C
L
< 20 pF
0
ns
CS High Pulsewidth
12
t
12
10
ns
CS High to CS High
12
t
13
4
t
CYC
RDY Rise to
CS Fall
t
14
0
ns
CS Rise to RDY Fall Time
t
15
0.1
0.15
ms
Read/Store to Nonvolatile EEMEM
13
t
16
Applies to Command 2
H
, 3
H
, 9
H
25
ms
CS Rise to Clock Rise/Fall Setup
t
17
10
ns
Preset Pulsewidth (Asynchronous)
t
PRW
Not Shown in Timing Diagram
50
ns
Preset Response Time to RDY High t
PRESP
PR Pulsed Low to Refreshed
Wiper Positions
70
s
FLASH/EE MEMORY RELIABILITY CHARACTERISTICS
Endurance
14
100
K Cycles
Data Retention
15
100
Years
NOTES
1
Typical parameters represent average readings at 25
C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
postions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
~ 50
A @ V
DD
= 2.7 V and
I
W
~ 400
A @ V
DD
= 5 V for the R
AB
= 10 k
version, I
W
~ 50
A for the R
AB
= 50 k
and I
W
~
25
A for the R
AB
= 100 k
version. See Figure 13.
3
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= V
SS
. DNL
specification limits of
1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 14.
4
Resistor terminals A, B, W have no limitations on polarity with respect to each other. Dual Supply Operation enables ground-referenced bipolar signal adjustment.
5
Guaranteed by design and not subject to production test.
6
Common-mode leakage current is a measure of the dc leakage from any terminal A, B, W to a common-mode bias level of V
DD
/2.
7
Transfer (XFR) Mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register. See TPC 9.
8
P
DISS
is calculated from (I
DD
V
DD
) + (I
SS
V
SS
).
9
All dynamic characteristics use V
DD
= +2.5 V and V
SS
= 2.5 V unless otherwise noted.
10
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using both V
DD
= 3 V or 5 V.
11
Propagation delay depends on value of V
DD
, R
PULL_UP
, and C
L
. See applications text.
12
Valid for commands that do not activate the RDY pin.
13
RDY pin low only for instruction commands 8, 9, 10, 2, 3, and the
PR hardware pulse: CMD_8 ~ 1 ms; CMD_9,10 ~ 0.12 ms; CMD_2,3 ~ 20 ms. Device operation
at T
A
= 40
C and V
DD
< 3 V extends the save time to 35 ms.
14
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at V
DD
= 2.7 V, T
A
= 40
C to +85
C, typical endurance at 25
C is
700,000 cycles.
15
Retention lifetime equivalent at junction temperature (T
J
) = 55
C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV
will derate with junction temperature as shown in Figure 23 in the Flash/EE Memory description section of this data sheet. The AD5232 contains 9,646
transistors. Die size: 69 mil 115 mil, 7,993 sq. mil.
Specifications subject to change without notice
AD5232
REV. 0
4
AD5232
CPOL = 1
t
12
t
13
t
3
t
17
t
9
t
11
t
5
t
4
t
2
t
1
CLK
t
8
*
MSB
LSB OUT
MSB
LSB
RDY
CPHA = 1
t
10
t
7
t
6
t
14
t
15
t
16
*
NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.
THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
CS
SDO
SDI
Figure 2a. CPHA = 1 Timing Diagram
t
12
t
13
t
3
t
17
t
9
t
11
t
5
t
4
t
2
t
1
CLK
CPOL = 0
t
8
MSB OUT
LSB
SDO
MSB IN
LSB
SDI
RDY
CPHA = 0
t
10
t
7
t
6
t
14
t
15
t
16
*
NOT DEFINED, BUT NORMALLY MSB OF CHARACTER JUST RECEIVED.
THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.
*
CS
Figure 2b. CPHA = 0 Timing Diagram
REV. 0
AD5232
5
ORDERING GUIDE
Number of
Number of
End-to-End
Temperature Package
Package
Devices per
Branding
*
Model
Channels
R
AB
(k )
Range (
C)
Description
Option
Container
Information
AD5232BRU10
2
10
40 to +85
TSSOP-16
RU-16
96
5232B10
AD5232BRU10-REEL7
2
10
40 to +85
TSSOP-16
RU-16
1,000
5232B10
AD5232BRU50
2
50
40 to +85
TSSOP-16
RU-16
96
5232B50
AD5232BRU50-REEL7
2
50
40 to +85
TSSOP-16
RU-16
1,000
5232B50
AD5232BRU100
2
100
40 to +85
TSSOP-16
RU-16
96
5232BC
AD5232BRU100-REEL7
2
100
40 to +85
TSSOP-16
RU-16
1,000
5232BC
*Line 1 contains ADI logo symbol and the data code YYWW, line 2 contains detail model number listed in this column.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5232 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25
C, unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +7 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, 7 V
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
V
A
, V
B
, V
W
to GND . . . . . . . . . . . . . V
SS
0.3 V, V
DD
+ 0.3 V
A
X
B
X
, A
X
W
X
, B
X
W
X
Intermittent
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 mA
Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 mA
Digital Inputs and Output Voltage to
GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, V
DD
+0.3 V
Operating Temperature Range
3
. . . . . . . . . . . 40
C to +85
C
Maximum Junction Temperature (T
J
Max) . . . . . . . . 150
C
Storage Temperature . . . . . . . . . . . . . . . . . . 65
C to +150
C
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
C
Package Power Dissipation . . . . . . . . . . . . . (T
J
Max T
A
)/
JA
Thermal Resistance Junction-to-Ambient
JA
,
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
C/W
Thermal Resistance Junction-to-Case
JC
,
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Maximum terminal current is bounded by the maximum current handling of the
switches, maximum power dissipation of the package, and maximum applied
voltage across any two of the A, B, and W terminals at a given resistance.
3
Includes programming of nonvolatile memory.