PRELIMINARY TECHNICAL DATA
a
Nonvolatile Memory
Digital Potentiometers
AD5231/AD5232/AD5233
REV PrF, 22 MAR '01
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use; nor for any infringements of patents
or other rights of third parties, which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106,
Norwood, MA 02062-9106 U
.
S
.
A
.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax:617/326-8703
Analog Devices, Inc., 1999
FEATURES
Nonvolatile Memory Preset Maintains Wiper Settings
AD5231 Single, 1024 Position Resolution
AD5232 Dual, 256 Position Resolution
AD5233 Quad, 64 Position Resolution
10K, 50K, 100K Ohm Terminal Resistance
Linear or Log taper Settings
Increment/Decrement Commands, Push Button Command
SPI Compatible Serial Data Input with Readback Function
+3 to +5V Single Supply or 2.5V Dual Supply Operation
User EEMEM nonvolatile memory for constant storage
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage to Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
DIP Switch Setting
GENERAL DESCRIPTION
The AD5231/AD5232/AD5233 family provides a single-
/dual-/quad-channel, digitally controlled variable resistor (VR)
with resolutions of 1024/256/64 positions respectively. These
devices perform the same electronic adjustment function as a
potentiometer or variable resistor. The AD523X's versatile
programming via a Micro Controller allows multiple modes of
operation and adjustment.
In the direct program mode a predetermined setting of the
RDAC register can be loaded directly from the micro controller.
Another key mode of operation allows the RDAC register to be
refreshed with the setting previously stored in the EEMEM
register. When changes are made to the RDAC register to
establish a new wiper position, the value of the setting can be
saved into the EEMEM by executing an EEMEM save
operation. Once the settings are saved in the EEMEM register
these values will be transferred automatically to the RDAC
register to set the wiper position at system power ON. Such
operation is enabled by the internal preset strobe and the preset
can also be accessed externally.
The basic mode of adjustment is the increment and decrement
command controlling the present setting of the Wiper position
setting (RDAC) register. An internal scratch pad RDAC register
can be moved UP or DOWN, one step of the nominal terminal
resistance between terminals A-and-B. This linearly changes the
wiper to B terminal resistance (R
WB
) by one position segment of
the device's end-to-end resistance (R
AB
). For
exponential/logarithmic changes in wiper setting, a left/right
shift command adjusts levels in +/-6dB steps, which can be
useful for sound and light alarm applications.
The AD523X are available in the thin TSSOP package. All
parts are guaranteed to operate over the extended industrial
temperature range of -40C to +85C.
FUNCTIONAL BLOCK DIAGRAMS
R D A C 1
R D A C 1
R E G IS T E R
S E R IA L
IN T E R F A C E
S D I
S D O
E E M E M 1
C S
C L K
S D I
S D O
V
D D
A
1
W
1
V
S S
W P
AD 5 2 3 1
A D D R
D E C O D E
B
1
D IG IT A L
O U T P U T
B U F F E R
D IG IT A L 2
R E G IS T E R
E E M E M 2
O
1
O
2
2
R D Y
G N D
E E M E M
C O N T R O L
P R
2 8 B Y T E S
U S E R E E M E M
R D A C 1
R D A C 1
R E G IS T E R
S E R IA L
IN T E R F A C E
S D I
S D O
E E M E M 1
C S
C L K
S D I
S D O
V
D D
A
1
W
1
V
S S
W P
A D 5232
A D D R
D E C O D E
B
1
R D A C 2
R D A C 2
R E G IS T E R
E E M E M 2
R D Y
G N D
E E M E M
C O N T R O L
A
2
W
2
B
2
P R
1 4 B Y T E S
U S E R E E M E M
R D A C 1
R D A C 1
R E G IS T E R
S E R IA L
IN T E R F A C E
S D I
S D O
E E M E M 1
C S
C L K
S D I
S D O
V
D D
A
1
W
1
W P
A D 5233
A D D R
D E C O D E
B
1
R D A C 2
R D A C 2
R E G IS T E R
E E M E M 2
R D Y
G N D
E E M E M
C O N T R O L
A
2
W
2
B
2
R D A C 3
R D A C 3
R E G IS T E R
E E M E M 3
A
3
W
3
V
S S
B
3
R D A C 4
R D A C 4
R E G IS T E R
E E M E M 4
A
4
W
4
B
4
D IG IT A L
O U T P U T
B U F F E R
D IG IT A L 5
R E G IS T E R
E E M E M 5
2
O
1
O
2
P R
1 1 B Y T E S
U S E R E E M E M
PRELIMINARY TECHNICAL DATA
AD5231/AD5232/AD5233 -
SPECIFICATIONS
REV PrF
2
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS
(V
DD
= +3V10% or +5V10% and V
SS
=0V,
V
A
= +V
DD
, V
B
= 0V, -40C < T
A
< +85C unless otherwise noted.)
Parameter Symbol
Conditions
Min
Typ
1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
=NC -1
1/4
+1
LSB
Resistor Nonlinearity
2
R-INL
R
WB
, V
A
=NC -1
1/2
+1
%FS
Nominal resistor tolerance
R T
A
= 25C, V
AB
= V
DD
,Wiper (V
W
) = No connect
-30
30
%
Resistance Temperature Coefficent
R
AB
/
T VAB = VDD, Wiper (V
W
) = No Connect
500
ppm/C
Wiper Resistance
R
W
I
W
= 1 V/R, V
DD
= +5V
50
100
Wiper Resistance
R
W
I
W
= 1 V/R, V
DD
= +3V
200
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs
Resolution
N
AD5231/AD5232/AD5233
10 / 8 / 6
Bits
Integral Nonlinearity
3
INL
1
1/2
+1
%FS
Differential Nonlinearity
3
DNL
1
1/4
+1
LSB
Voltage Divider Temperature Coefficent
V
W
/
T Code
=
Half-scale
15
ppm/C
Full-Scale Error
V
WFSE
Code
=
Full-scale
3 +0
%FS
Zero-Scale Error
V
WZSE
Code
=
Zero-scale
0 +3
%FS
RESISTOR TERMINALS
Voltage Range
4
V
A,B,W
V
SS
V
DD
V
Capacitance
5
Ax, Bx
C
A,B
f = 1 MHz, measured to GND, Code = Half-scale
45
pF
Capacitance
5
Wx
C
W
f = 1 MHz, measured to GND, Code = Half-scale
60
pF
Common-mode Leakage Current
6
I
CM
V
A
= V
B
= V
DD
/2
0.01
1
A
DIGITAL INPUTS & OUTPUTS
Input Logic High
V
IH
with respect to GND, VDD = 5V
2.4
V
Input Logic Low
V
IL
with respect to GND, VDD = 5V
0.8
V
Input Logic High
V
IH
with respect to GND, VDD = 3V
2.1
V
Input Logic Low
V
IL
with respect to GND, VDD = 3V
0.6
V
Output Logic High
V
OH
R
PULL-UP
= 2.2K
to +5V
4.9
V
Output Logic High
V
OH
I
OH
= 40
A, V
LOGIC
= +5V
4
V
Output Logic Low
V
OL
I
OL
= 1.6mA, V
LOGIC
= +5V
0.4
V
Input Current
I
IL
V
IN
= 0V or V
DD
1
A
Input Capacitance
5
C
IL
5
pF
POWER SUPPLIES
Single-Supply Power Range
V
DD
V
SS
= 0V
2.7
5.5
V
Dual-Supply Power Range
V
DD
/V
SS
2.25 2.75
V
Positive Supply Current
I
DD
V
IH
= V
DD
or V
IL
= GND
2
20
A
Programming Mode Current
I
DD(PG)
V
IH
= V
DD
or V
IL
= GND
35
mA
Read Mode Current
13
I
DD(READ)
V
IH
= V
DD
or V
IL
= GND
0.9
9
mA
Negative Supply Current
I
SS
V
IH
= V
DD
or V
IL
= GND, V
DD
= 2.5V, V
SS
= -2.5V
10
A
Power Dissipation
7
P
DISS
V
IH
= V
DD
or V
IL
= GND
0.1
mW
Power Supply Sensitivity
PSS
V
DD
= +5V 10%
0.002
0.01
%/%
DYNAMIC CHARACTERISTICS
5, 8
Bandwidth 3dB
BW_10K
R = 10K
600
KHz
Total Harmonic Distortion
THD
W
V
A
=1Vrms, V
B
= 0V, f=1KHz
0.003
%
V
W
Settling Time
t
S
V
A
= V
DD
, V
B
=0V, 50% of final value
For
R
AB
= 10K/50K/100K
1 / 3 / 6
s
Resistor Noise Voltage
e
N_WB
R
WB
= 5K
, f = 1KHz
9
nV
Hz
Crosstalk (C
W1
/C
W2
) C
T
V
A
= V
DD
, V
B
= 0V, Measure V
W
with
adjacent
VR making full scale change
-65
dB
NOTES: See bottom of table next page.
PRELIMINARY TECHNICAL DATA
AD5231/AD5232/AD5233 -
SPECIFICATIONS
REV PrF
3
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
ELECTRICAL CHARACTERISTICS 10K, 50K, 100K OHM VERSIONS
(V
DD
= +3V10% to +5V10% and V
SS
=0V,
V
A
= +V
DD
, V
B
= 0V, -40C < T
A
< +85C unless otherwise noted.)
Parameter Symbol
Conditions
Min
Typ
1
Max
Units
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 5, 9)
Clock Cycle Time
t
1
20
ns
Input Clock Pulse Width
t
2
, t
3
Clock level high or low
10
ns
CS Setup Time
t
4
10
ns
Data Setup Time
t
5
From Positive CLK transition
5
ns
Data Hold Time
t
6
From Positive CLK transition
5
ns
CLK Shutdown Time
t
7
0
ns
CS Rise to Clock Rise Setup
t
8
10
ns
CS High Pulse Width
t
9
10
ns
CLK to SDO Propagation Delay
10
t
10
R
P
= 1K
, C
L
< 20pF
1
25
ns
Store to Nonvolatile EEMEM Save Time
11
t
12
Applies to Command 2
H
, 3
H
, 9
H
25
ms
CS to SDO - SPI line acquire
t
13
ns
CS to SDO - SPI line release
t
14
ns
RDY Rise to
CS Fall
t
15
ns
Startup Time
t
16
ms
CLK Setup Time
t
17
For 1 CLK period (t
4
- t
3
= 1 CLK period)
ns
Preset Pulse Width (Asynchronous)
t
PR
50
ns
Preset Response Time
t
PRESP
PR pulsed low then high
70
us
NOTES:
1.
Typicals represent average readings at +25C and V
DD
= +5V.
2.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
W
= V
DD
/R for both V
DD
=+3V or V
DD
=+5V.
3.
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= V
SS
.
DNL specification limits of 1LSB maximum are Guaranteed Monotonic operating conditions.
4.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5.
Guaranteed by design and not subject to production test.
6.
Common mode leakage current is a measure of the DC leakage from any terminal A, B, W to a common mode bias level of V
DD
/ 2.
7. P
DISS
is calculated from (I
DD
x V
DD
) + (I
SS
X V
SS
).
8.
All dynamic characteristics use V
DD
= +5V.
9.
See timing diagram for location of measured values. All input control voltages are specified with t
R
=t
F
=2.5ns(10% to 90% of 3V) and timed from a voltage level of 1.5V. Switching
characteristics are measured using both V
DD
= +3V or +5V.
10.
Propagation delay depends on value of V
DD
, R
PULL_UP
, and C
L
see applications text.
11.
Low only for instruction commands 8, 9,10, 2, 3: CMD_8 ~ 1ms; CMD_9,10 ~0.12ms; CMD_2,3 ~20ms
12.
Dual Supply Operation primarily affects the POT terminals.
13.
Read Mode current is not continuous.
Timing Diagram
t
2
t
3
M S B
L S B
M S B
L S B
C L K
C S
S D I
S D O
1
t
1
t
4
t
5
t
6
t
7
t
9
t
1 4
t
1 0
R D Y
t
1 2
t
1 7
M S B
L S B
S D O
2
t
1 3
t
1 5
t
1 6
SD O
1
C LK ID LES L O W
SD O
2
C LK ID LES H IG H
t
8
Figure 1. Timing Diagram
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers
AD5231/AD5232/AD5233
REV PrF
4
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
Absolute Maximum Rating (
T
A
= +25C, unless
otherwise noted)
V
DD
to GND ..............................................................-0.3, +7V
V
SS
to GND ................................................................. 0V, -7V
V
DD
to V
SS
.........................................................................+7V
V
A
, V
B
, V
W
to GND..................................................V
SS
, V
DD
A
X
B
X
, A
X
W
X
, B
X
W
X
Intermittent ................................................... 20mA
Continuous................................................... 1.3mA
O
x
to GND .................................................................. 0V, V
DD
Digital Inputs & Output Voltage to GND .................. 0V, +7V
Operating Temperature Range ........................ -40C to +85C
Maximum Junction Temperature (T
J MAX
) .................. +150C
Storage Temperature ..................................... -65C to +150C
Lead Temperature (Soldering, 10 sec) ......................... +300C
Package Power Dissipation ........................ (T
JMAX
- T
A
) /
JA
Thermal Resistance
JA,
TSSOP-16 ..................................................... 150C/W
TSSOP-24 ..................................................... 128C/W
Ordering Guide
Number of
End to End
Temp
Package
Package #Devices
Top Mark
Model
Channels
R (k Ohm)
Range
Description
Option
per Container
AD5231BRU10 X1 10 -40/+85C
TSSOP-16
RU-16
AD5231BRU10-REEL7 X1
10
-40/+85C
TSSOP-16
RU-16
1,000
AD5231BRU50 X1 50 -40/+85C
TSSOP-16
RU-16
AD5231BRU50-REEL7 X1
50
-40/+85C
TSSOP-16
RU-16
1,000
AD5231BRU100 X1
100 -40/+85C
TSSOP-16
RU-16
AD5231BRU100-REEL7 X1
100
-40/+85C
TSSOP-16 RU-16
1,000
AD5232BRU10 X2 10 -40/+85C
TSSOP-16
RU-16
AD5232BRU10-REEL7 X2
10
-40/+85C
TSSOP-16
RU-16
1,000
AD5232BRU50 X2 50 -40/+85C
TSSOP-16
RU-16
AD5232BRU50-REEL7 X2
50
-40/+85C
TSSOP-16
RU-16
1,000
AD5232BRU100 X2
100 -40/+85C
TSSOP-16
RU-16
AD5232BRU100-REEL7 X2
100
-40/+85C
TSSOP-16 RU-16
1,000
AD5233BRU10 X4 10 -40/+85C
TSSOP-24
RU-24
AD5233BRU10-REEL7 X4
10
-40/+85C
TSSOP-24
RU-24
AD5233BRU50 X4 50 -40/+85C
TSSOP-24
RU-24
AD5233BRU50-REEL7 X4
50
-40/+85C
TSSOP-24
RU-24
AD5233BRU100 X4
100 -40/+85C
TSSOP-24
RU-24
AD5233BRU100-REEL7 X4
100
-40/+85C
TSSOP-24 RU-24
The AD5231/AD5232/AD5233 contains 9,646 transistors.
Die size: 69 mil x 115 mil, 7,993 sq. mil
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Digital Potentiometers
AD5231/AD5232/AD5233
REV PrF
5
22 MAR '01
Information contained in this Preliminary data sheet describes a product in the early definition stage. There is no guarantee that the
information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa
Clara, CA. TEL(408)382-3107; FAX (408)382-2708; walt.heinzer@analog.com
AD5231
PIN CONFIGURATION
O1
CLK
SDI
SDO
GND
V
SS
T1
B1
O2
RDY
CS
CS
CS
CS
PR
PR
PR
PR
WP
WP
WP
WP
V
DD
A1
W1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
AD5231 PIN FUNCTION DESCRIPTION
# Name Description
1
O1
Non-Volatile Digital Output #1, ADDR(O1) =
1H, data bit position D0
2
CLK
Serial Input Register clock pin. Shifts in one
bit at a time on positive clock CLK edges.
3
SDI
Serial Data Input Pin.
4
SDO
Serial Data Output Pin. Open Drain Output
requires external pull-up resistor. Commands 9
& 10 activate the SDO output. See Instruction
operation Truth Table. Other commands shift
out the previously loaded bit pattern delayed
by 24 clock pulses. This allows daisy-chain
operation of multiple packages.
5
GND
Ground pin, logic ground reference.
6 V
SS
Negative Supply. Connect to zero volts for
single supply applications.
7
T1
Used as digital input during factory test mode.
Leave pin floating or connect to V
DD
or V
SS
.
8
B1
B terminal of RDAC1.
9
W1
Wiper terminal of RDAC1,
ADDR(RDAC1) = 0
H
10
A1
A terminal of RDAC1.
11 V
DD
Positive Power Supply Pin. Should be
the
input-logic HIGH voltage.
12
WP
Write Protect Pin. When active low
WP
prevents any changes to the present contents
except retrieving EEMEM contents and
RESET.
13
PR
Hardware over ride preset pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 200
H
until EEMEM loaded with a
new value by the user (
PR is activated at the
rising logic high transition)
14
CS
Serial Register chip select active low. Serial
register operation takes place when
CS returns
to logic high.
15
RDY
Ready. Active-high open drain output.
Identifies completion of commands 2, 3, 8, 9,
10.
16
O2
Non-Volatile Digital Output #2, ADDR(O2) =
1H, data bit position D1.
AD5232
PIN CONFIGURATION
CLK
SDI
SDO
GND
V
SS
A1
W1
B1
RDY
CS
CS
CS
CS
PR
PR
PR
PR
WP
WP
WP
WP
V
DD
A2
W2
B2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
AD5232 PIN FUNCTION DESCRIPTION
# Name Description
1
CLK
Serial Input Register clock pin. Shifts in one
bit at a time on positive clock edges.
2
SDI
Serial Data Input Pin. Shifts in one bit at a
time on positive clock CLK edges.
3
SDO
Serial Data Output Pin. Open Drain Output
requires external pull-up resistor. Commands 9
& 10 activate the SDO output. See Instruction
operation Truth Table. Other commands shift
out the previously loaded bit pattern delayed
by 16 clock pulses. This allows daisy-chain
operation of multiple packages.
4
GND
Ground pin, logic ground reference
5 V
SS
Negative Supply. Connect to zero volts for
single supply applications.
6
A1
A terminal of RDAC1.
7
W1
Wiper terminal of RDAC1,
ADDR(RDAC1) = 0
H
.
8
B1
B terminal of RDAC1.
9
B2
B terminal of RDAC2.
10
W2
Wiper terminal of RDAC2,
ADDR(RDAC2) = 1
H
.
11
A2
A terminal of RDAC2.
12 V
DD
Positive Power Supply Pin. Should be
the
input-logic HIGH voltage.
13
WP
Write Protect Pin. When active low,
WP
prevents any changes to the present contents,
except retrieving EEMEM content and
RESET.
14
PR
Hardware over ride preset pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 80
H
until EEMEM loaded with a new
value by the user (
PR is activated at the logic
high transition).
15
CS
Serial Register chip select active low. Serial
register operation takes place when
CS returns
to logic high.
16
RDY
Ready. Active-high open drain output.
Identifies completion of commands 2, 3, 8, 9,
10.
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