REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD654
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
Low Cost Monolithic
Voltage-to-Frequency Converter
FEATURES
Low Cost
Single or Dual Supply, 5 V to 36 V, 5 V to 18 V
Full-Scale Frequency Up to 500 kHz
Minimum Number of External Components Needed
Versatile Input Amplifier
Positive or Negative Voltage Modes
Negative Current Mode
High Input Impedance, Low Drift
Low Power: 2.0 mA Quiescent Current
Low Offset: 1 mV
PRODUCT DESCRIPTION
The AD654 is a monolithic V/F converter consisting of an input
amplifier, a precision oscillator system, and a high current output
stage. A single RC network is all that is required to set up any
full scale (FS) frequency up to 500 kHz and any FS input voltage
up to
30 V. Linearity error is only 0.03% for a 250 kHz FS,
and operation is guaranteed over an 80 dB dynamic range. The
overall temperature coefficient (excluding the effects of external
components) is typically
50 ppm/
C. The AD654 operates from
a single supply of 5 V to 36 V and consumes only 2.0 mA quies-
cent current.
The low drift (4
V/
C typ) input amplifier allows operation
directly from small signals such as thermocouples or strain gauges
while offering a high (250 M
) input resistance. Unlike most
V/F converters, the AD654 provides a square-wave output, and
can drive up to 12 TTL loads, optocouplers, long cables, or
similar loads.
PRODUCT HIGHLIGHTS
1. Packaged in both an 8-lead mini-DIP and an 8-lead SOIC
package, the AD654 is a complete V/F converter requiring
only an RC timing network to set the desired full-scale fre-
quency and a selectable pull-up resistor for the open-collector
output stage. Any full scale input voltage range from 100 mV
to 10 volts (or greater, depending on +V
S
) can be accommo-
dated by proper selection of the timing resistor. The full-
scale frequency is then set by the timing capacitor from the
simple relationship, f = V/10 RC.
2. A minimum number of low cost external components are
necessary. A single RC network is all that is required to set
up any full scale frequency up to 500 kHz and any full-scale
input voltage up to
30 V.
3. Plastic packaging allows low cost implementation of the
standard VFC applications: A/D conversion, isolated signal
transmission, F/V conversion, phase-locked loops, and tuning
switched-capacitor filters.
4. Power supply requirements are minimal; only 2.0 mA of
quiescent current is drawn from the single positive supply
from 4.5 volts to 36 volts. In this mode, positive inputs can
vary from 0 volts (ground) to (+V
S
4) volts. Negative inputs
can easily be connected for below ground operation.
5. The versatile open-collector output stage can sink more than
10 mA with a saturation voltage less than 0.4 volts. The Logic
Common terminal can be connected to any level between
ground (or V
S
) and 4 volts below +V
S
. This allows easy
direct interface to any logic family with either positive or
negative logic levels.
FUNCTIONAL BLOCK DIAGRAM
3
2
1
5
8
7
6
AD654
4
DRIVER
OSC
F
OUT
LOGIC
COMMON
R
T
+V
IN
+V
S
C
T
C
T
V
S
2
REV. B
AD654SPECIFICATIONS
(T
A
= +25 C and V
S
(total) = 5 V to 16.5 V, unless otherwise noted. All testing done
@ V
S
= +5 V.)
AD654JN/JR
Model
Min
Typ
Max
Units
CURRENT-TO-FREQUENCY CONVERTER
Frequency Range
0
500
kHz
Nonlinearity
1
f
MAX
= 250 kHz
0.06
0.1
%
f
MAX
= 500 kHz
0.20
0.4
%
Full-Scale Calibration Error
C = 390 pF, I
IN
= 1.000 mA
10
+10
%
vs. Supply (f
MAX
250 kHz)
V
S
= +4.75 V to +5.25 V
0.20
0.40
%/V
V
S
= +5.25 V to +16.5 V
0.05
0.10
%/V
vs. Temp (0
C to +70
C)
50
ppm/
C
ANALOG INPUT AMPLIFIER
(Voltage-to-Current Converter)
Voltage Input Range
Single Supply
0
(+V
S
4)
V
Dual Supply
V
S
(+V
S
4)
V
Input Bias Current
(Either Input)
30
50
nA
Input Offset Current
5
nA
Input Resistance (Noninverting)
250
M
Input Offset Voltage
0.5
1.0
mV
vs. Supply
V
S
= +4.75 V to +5.25 V
0.1
0.25
mV/V
V
S
= +5.25 V to +16.5 V
0.03
0.1
mV/V
vs. Temp (0
C to +70
C)
4
V/
C
OUTPUT INTERFACE (Open Collector Output)
(Symmetrical Square Wave)
Output Sink Current in Logic "0"
2
V
OUT
= 0.4 V max, +25
C
10
20
mA
V
OUT
= 0.4 V max, 0
C to +70
C
5
10
mA
Output Leakage Current in Logic "1"
10
100
nA
0
C to +70
C
50
500
nA
Logic Common Level Range
V
S
(+V
S
4)
V
Rise/Fall Times (C
T
= 0.01
F)
I
IN
= 1 mA
0.2
s
I
IN
= 1
A
1
s
POWER SUPPLY
Voltage, Rated Performance
4.5
16.5
V
Voltage, Operating Range
Single Supply
4.5
36
V
Dual Supply
5
18
V
Quiescent Current
V
S
(Total) = 5 V
1.5
2.5
mA
V
S
(Total) = 30 V
2.0
3.0
mA
TEMPERATURE RANGE
Operating Range
40
+85
C
NOTES
1
At f
MAX
= 250 kHz; R
T
= 1 k
, C
T
= 390 pF, I
IN
= 0 mA1 mA.
1
At
f
MAX
= 500 kHz; R
T
= 1 k
, C
T
= 200 pF, I
IN
= 0 mA1 mA.
2
The sink current is the amount of current that can flow into Pin 1 of the AD654 while maintaining a maximum voltage of 0.4 V between Pin 1 and Logic Common.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
AD654
REV. B
3
ABSOLUTE MAXIMUM RATING
Total Supply Voltage +V
S
to V
S
. . . . . . . . . . . . . . . . . . . 36 V
Maximum Input Voltage
(Pins 3, 4) to V
S
. . . . . . . . . . . . . . . . . . . . 300 mV to +V
S
Maximum Output Current
Instantaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Sustained . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Logic Common to V
S
. . . . . . . . . . . . . . . 500 mV to (+V
S
4)
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150
C
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD654JN
40
C to +85
C
8-Lead Plastic DIP
N-8
AD654JR
40
C to +85
C
8-Lead SOIC
SO-8
AD654
4
REV. B
CIRCUIT OPERATION
The AD654's block diagram appears in Figure 1. A versatile
operational amplifier serves as the input stage; its purpose is to
convert and scale the input voltage signal to a drive current in the
NPN follower. Optimum performance is achieved when, at the
full-scale input voltage, a 1 mA drive current is delivered to the
current-to-frequency converter (an astable multivibrator). The
drive current provides both the bias levels and the charging current
to the externally connected timing capacitor. This "adaptive" bias
scheme allows the oscillator to provide low nonlinearity over
the entire current input range of 100 nA to 2 mA. The square
wave oscillator output goes to the output driver which provides
a floating base drive to the NPN power transistor. This floating
drive allows the logic interface to be referenced to a level other
than V
S
.
OSC/
DRIVER
AD654
OPTIONAL
R
COMP
CR1
V
S
(0V TO 15V)
R1
R2
V
IN
+V
S
(+5V TO V
S
+30)
C
T
+V
LOGIC
R
PU
F
OUT
F
OUT
=
V
IN
(10V) (R1 + R2) C
T
Figure 1. Standard V-F Connection for Positive Input
Voltages
V/F CONNECTION FOR POSITIVE INPUT VOLTAGES
In the connection scheme of Figure 1, the input amplifier presents
a very high (250 M
) impedance to the input voltage, which
is converted into the proper drive current by the scaling resistors
at Pin 3. Resistors R1 and R2 are selected to provide a 1 mA
full-scale current with enough trim range to accommodate the
AD654's 10% FS error and the components' tolerances. Full-
scale currents other than 1 mA can be chosen, but linearity will
be reduced; 2 mA is the maximum allowable drive. The AD654's
positive input voltage range spans from V
S
(ground in sink supply
operation) to four volts below the positive supply. Power sup-
ply rejection degrades as the input exceeds (+V
S
3.75 V) and at
(+V
S
3.5 V) the output frequency goes to zero.
As indicated by the scaling relationship in Figure 1, a 0.01
F
timing capacitor will give a 10 kHz full-scale frequency, and
0.001
F will give 100 kHz with a 1 mA drive current. Good V/F
linearity requires the use of a capacitor with low dielectric
absorption (DA), while the most stable operation over tempera-
ture calls for a component having a small tempco. Polystyrene,
polypropylene, or Teflon* capacitors are preferred for tempco and
dielectric absorption; other types will degrade linearity. The
capacitor should be wired very close to the AD654. In Figure 1,
Schottky diode CR1 (MBD101) prevents logic common from
dropping more than 500 mV below V
S
. This diode is not
required if V
S
is equal to logic common.
V/F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
OR CURRENT
The AD654 can accommodate a wide range of negative input
voltages with proper selection of the scaling resistor, as indicated
in Figure 2. This connection, unlike the buffered positive con-
nection, is not high impedance because the signal source must
supply the 1 mA FS drive current. However, large negative volt-
ages beyond the supply can be handled easily by modifying the
scaling resistors appropriately. If the input is a true current source,
R1 and R2 are not used. Again, diode CR1 prevents latch-up by
insuring Logic Common does not drop more than 500 mV below
V
S
. The clamp diode (MBD101) protects the AD654 input
from "below V
S
" inputs.
OSC/
DRIVER
AD654
OPTIONAL
R
COMP
CR1
V
S
(0V TO 15V)
R1
R2
+V
S
(+5V TO V
S
+30)
C
T
+V
LOGIC
R
PU
F
OUT
F
OUT
=
V
IN
(10V) (R1 + R2) C
T
V
IN
CLAMP
DIODE
Figure 2. V-F Connections for Negative Input Voltages or
Current
OFFSET CALIBRATION
In theory, two adjustments calibrate a V/F: scale and offset. In
practice, most applications find the AD654's 1 mV max voltage
offset sufficiently low to forgo offset calibration. However, the
input amplifier's 30 nA (typ) bias currents will generate an offset
due to the difference in dc sound resistance between the input
terminals. This offset can be substantial for large values of R
T
=
R1 + R2 and will vary as the bias currents drift over temperature.
Therefore, to maintain the AD654's low offset, the application may
require balancing the dc source resistances at the inputs (Pins
3 and 4).
For positive inputs, this is accomplished by adding a compensation
resistor nominally equal to R
T
in series with the input as shown
in Figure 3a. This limits the offset to the product of the 30 nA
bias current and the mismatch between the source resistance R
T
and R
COMP
. A second, smaller offset arises from the inputs' 5 nA
offset current flowing through the source resistance R
T
or R
COMP
.
For negative input voltage and current connections, the compensa-
tion resistor is added at Pin 4 as shown in Figure 3b in lieu of
grounding the pin directly. For both positive and negative inputs,
the use of R
COMP
may lead to noise coupling at Pin 4 and should
therefore be bypassed for lowest noise operation.
R1
R2
V
IN
R
COMP
AD654
(OPTIONAL)
C
Figure 3a. Bias Current Compensation--Positive Inputs
*Teflon is a trademark of E.I. Du Pont de Nemours & Co.
AD654
REV. B
5
(OPTIONAL)
C
R1
R2
V
IN
R
COMP
AD654
Figure 3b. Bias Current Compensation--Negative Inputs
If the AD654's 1 mV offset voltage must be trimmed, the trim
must be performed external to the device. Figure 3c shows an
optional connection for positive inputs in which R
OFF1
and
R
OFF2
add a variable resistance in series with R
T
. A variable
source of
0.6 V applied to R
OFF1
then adjusts the offset
1 mV.
Similarly, a
0.6 V variable source is applied to R
OFF
in Fig-
ure 3d to trim offset for negative inputs. The
0.6 V bipolar
source could simply be an AD589 reference connected as shown
in Figure 3e.
V
IN
10k
AD654
5k
8.25k
R
OFF2
20
R
OFF1
10k
0.6V
Figure 3c. Offset Trim Positive Input (10 V FS)
V
IN
10k
AD654
5k
8.25k
R
OFF
5.6M
0.6V
Figure 3d. Offset Trim Negative Input (10 V FS)
+5V
R3
10k
0.6V
R4
10k
R5
100k
+
AD589
R1
10k
R1
10k
R2
10k
5V
Figure 3e. Offset Trim Bias Network
FULL-SCALE CALIBRATION
Full-scale trim is the calibration of the circuit to produce the
desired output frequency with a full-scale input applied. In most
cases this is accomplished by adjusting the scaling resistor R
T
.
Precise calibration of the AD654 requires the use of an accurate
voltage standard set to the desired FS value and an accurate
frequency meter. A scope is handy for monitoring output wave-
shape. Verification of converter linearity requires the use of a
switchable voltage source or DAC having a linearity error below
0.005%, and the use of long measurement intervals to mini-
mize count uncertainties. Since each AD654 is factory tested for
linearity, it is unnecessary for the end-user to perform this tedious
and time consuming test on a routine basis.
Sufficient FS calibration trim range must be provided to accom-
modate the worst-case sum of all major scaling errors. This
includes the AD654's 10% full-scale error, the tolerance of the
fixed scaling resistor, and the tolerance of the timing capacitor.
Therefore, with a resistor tolerance of 1% and a capacitor tolerance
of 5%, the fixed part of the scaling resistor should be a maximum
of 84% of nominal, with the variable portion selected to allow
116% of the nominal.
If the input is in the form of a negative current source, the scaling
resistor is no longer required, eliminating the capability of trim-
ming FS frequency in this fashion. Since it is usually not practical
to smoothly vary the capacitance for trimming purposes, an
alternative scheme such as the one shown in Figure 4 is needed.
Designed for a FS of 1 mA, this circuit divides the input into two
AD654
R
OFF
100k
R4
392
R3
1k
0.6V
*
*OPTIONAL
OFFSET TRIM
f =
I
S
(20V) C
T
I
R
V
1mA
FS
I
S
R2
100
R1
100
Figure 4. Current Source FS Trim
and flowing into Pin 3; it constitutes the signal current I
T
to be
converted. The second path, through another 100
resistor R2,
carries the same nominal current. Two equal valued resistors
offer the best overall stability, and should be either 1% discrete
film units, or a pair from a common array.
Since the 1 mA FS input current is divided into two 500
A legs
(one to ground and one to Pin 3), the total input signal current
(I
S
) is divided by a factor of two in this network. To achieve the
same conversion scale factor, C
T
must be reduced by a factor of
two. This results in a transfer unique to this hookup:
f
=
I
S
(20 V ) C
T
For calibration purposes, resistors R3 and R4 are added to the
network, allowing a
15% trim of scale factor with the values
shown. By varying R4's value the trim range can be modified to
accommodate wider tolerance components or perhaps the cali-
bration tolerance on a current output transducer such as the
AD592 temperature sensor. Although the values of R1R4 shown
are valid for 1 mA FS signals only, they can be scaled upward
proportionately for lower FS currents. For instance, they should
be increased by a factor of ten for a FS current of 100
A.
In addition to the offsets generated by the input amplifier's bias
and offset currents, an offset voltage induced parasitic current
arises from the current fork input network. These effects are
minimized by using the bias current compensation resistor R
OFF
and offset trim scheme shown in Figure 3e.
Although device warm-up drifts are small, it is good practice to
allow the devices operating environment to stabilize before trim,
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