FUNCTIONAL BLOCK DIAGRAM
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD674B/AD774B
5V SUPPLY
V
LOGIC
DATA MODE SELECT
12/
8
CHIP SELECT
CS
BYTE ADDRESS/
SHORT CYCLE A
0
READ/CONVERT R/
C
CHIP ENABLE
CE
12V/15V SUPPLY
V
CC
10V REFERENCE
REF OUT
ANALOG COMMON
AC
REFERENCE INPUT
REF IN
12V/ 15V SUPPLY
V
EE
BIPOLAR OFFSET
BIPOFF
10V SPAN INPUT
10V
IN
20V SPAN INPUT
20V
IN
STATUS
STS
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
DIGITAL
COMMON DC
CONTROL
VOLTAGE
DIVIDER
N
Y
B
B
L
E
A
MSB
3
S
T
A
T
E
O
U
T
P
U
T
B
U
F
F
E
R
S
LSB
N
Y
B
B
L
E
B
N
Y
B
B
L
E
C
CLOCK
SAR
12
10V
REF
+
COMP
I DAC
+
199.95
k
DAC
N
V
EE
I REF
DIGITAL
DATA
OUTPUTS
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
Complete 12-Bit
A/D Converters
AD674B
*
/AD774B
*
FEATURES
Complete Monolithic 12-Bit A/D Converters with
Reference, Clock, and Three-State Output Buffers
Industry Standard Pinout
High Speed Upgrades for AD574A
8- and 16-Bit Microprocessor Interface
8 s (Max) Conversion Time (AD774B)
15 s (Max) Conversion Time (AD674B)
5 V, 10 V, 0 V10 V, 0 V20 V Input Ranges
Commercial, Industrial, and Military Temperature
Range Grades
MIL-STD-883-Compliant Versions Available
PRODUCT DESCRIPTION
The AD674B and AD774B are complete 12-bit successive-
approximation analog-to-digital converters with three-state
output buffer circuitry for direct interface to 8- and 16-bit
microprocessor busses. A high-precision voltage reference and
clock are included on chip, and the circuit requires only power
supplies and control signals for operation.
The AD674B and AD774B are pin-compatible with the indus-
try standard AD574A, but offer faster conversion time and bus-
access speed than the AD574A and lower power consumption.
The AD674B converts in 15
s (maximum) and the AD774B
converts in 8
s (maximum).
The monolithic design is implemented using Analog Devices'
BiMOS II process allowing high-performance bipolar analog
circuitry to be combined on the same die with digital CMOS logic.
Offset, linearity, and scaling errors are minimized by active
laser trimming of thin-film resistors.
Five different grades are available. The J and K grades are
specified for operation over the 0
C to 70C temperature range.
The A and B grades are specified from 40
C to +85C, the T grade
is specified from 55
C to +125C. The J and K grades are
available in a 28-lead plastic DIP or 28-lead SOIC. All other grades
are available in a 28-lead hermetically sealed ceramic DIP.
PRODUCT HIGHLIGHTS
1. Industry Standard Pinout: The AD674B and AD774B use
the pinout established by the industry standard AD574A.
2. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges: 0 V to
10 V and 0 V to 20 V unipolar; 5 V to +5 V and 10 V to
+10 V bipolar. The AD674B and AD774B operate on +5 V
and
12 V or 15 V power supplies.
3. Flexible Digital Interface: On-chip multiple-mode three-state
output buffers and interface logic allow direct connection to
most microprocessors. The 12 bits of output data can be
read either as one 12-bit word or as two 8-bit bytes (one with
8 data bits, the other with 4 data bits and 4 trailing zeros).
4. The internal reference is trimmed to 10.00 V with 1% maxi-
mum error and 10 ppm/
C typical temperature coefficient.
The reference is available externally and can drive up to
2.0 mA beyond the requirements of the converter and bipo-
lar offset resistors.
5. The AD674B and AD774B are available in versions compli-
ant with MIL-STD-883. Refer to the Analog Devices Mili-
tary Products Databook or current AD674B/AD774B/883B
data sheet for detailed specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
*Protected by U.S. Patent Nos. 4,250,445; 4,808,908; RE30586.
J Grade
K Grade
A Grade
B Grade
T Grade
Model (AD674B or AD774B)
Min Typ
Max Min Typ Max
Min Typ Max
Min Typ Max
Min
Typ Max
Unit
RESOLUTION
12
12
12
12
12
Bits
LINEARITY ERROR @ 25
C
1
1/2
1
1/2
1/2
LSB
T
MIN
to T
MAX
1
1/2
1
1/2
1
LSB
DIFFERENTIAL LINEARITY ERROR
(Minimum Resolution for Which No
Missing Codes are Guaranteed)
12
12
12
12
12
Bits
UNIPOLAR OFFSET
1
@ 25
C
2
2
2
2
2
LSB
BIPOLAR OFFSET
1
@ 25
C
6
3
6
3
3
LSB
FULL-SCALE CALIBRATION ERROR
1, 2
@ 25
C (with Fixed 50 Resistor
from REF OUT to REF IN)
0.1
0.25
0.1
0.125
0.1 0.25
0.1
0.125
0.1 0.125
% of FS
TEMPERATURE RANGE
0
70
0
70
40
+85
40
+85
55
+125
C
TEMPERATURE DRIFT
3
(Using Internal Reference)
Unipolar
2
1
2
1
1
LSB
Bipolar Offset
2
1
2
1
2
LSB
Full-Scale Calibration
6
2
8
5
7
LSB
POWER SUPPLY REJECTION
Max Change in Full-Scale Calibration
V
CC
= +15 V
1.5 V or +12 V 0.6 V
2
1
2
1
1
LSB
V
LOGIC
= +5 V
0.5 V
1/2
1/2
1/2
1/2
1/2
LSB
V
EE
= 15 V
1.5 V or 12 V 0.6 V
2
1
2
1
1
LSB
ANALOG INPUT
Input Ranges
Bipolar
5
+5
5
+5
5
+5
5
+5
5
+5
V
10
+10
10
+10
10
+10
10
+10
10
+10
V
Unipolar
0
10
0
10
0
10
0
10
0
10
V
0
20
0
20
0
20
0
20
0
20
V
Input Impedance
10 V Span
3
5
7
3
5
7
3
5
7
3
5
7
3
5
7
k
20 V Span
6
10
14
6
10
14
6
10
14
6
10
14
6
10
14
k
POWER SUPPLIES
Operating Range
V
LOGIC
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
V
CC
11.4
16.5
11.4
16.5
11.4
16.5
11.4
16.5
11.4
16.5
V
V
EE
16.5
11.4 16.5
11.4 16.5
11.4
16.5
11.4 16.5
11.4
V
Operating Current
I
LOGIC
3.5
7
3.5
7
3.5 7
3.5
7
3.5 7
mA
I
CC
3.5
7
3.5
7
3.5 7
3.5
7
3.5 7
mA
I
EE
10
14
10
14
10
14
10
14
10
14
mA
POWER CONSUMPTION
220
375
220 375
220 375
220 375
220 375
mW
4
175
175
175
175
175
mW
5
INTERNAL REFERENCE VOLTAGE
9.9
10.0 10.1
9.9
10.0 10.1
9.9
10.0 10.1
9.9
10.0 10.1
9.9
10.0 10.1
V
Output Current
(Available for External Loads)
2.0
2.0
2.0
2.0
2.0
mA
(External Load Should Not
Change During the Conversion)
NOTES
1
Adjustable to zero.
2
Includes internal voltage reference error.
3
Maximum change from 25
C value to the value at T
MIN
or T
MAX
.
4
Tested with REF OUT tied to REF IN through 50
resistor, V
CC
= +16.5 V, V
EE
= 16.5 V, V
LOGIC
= +5.5 V, and outputs in high-Z mode.
5
Tested with REF OUT tied to REF IN through 50
resistor, V
CC
= +12 V, V
EE
= 12 V, V
LOGIC
= +5 V, and outputs in high-Z mode.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at T
MIN
, 25
C, and T
MAX
. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed, although only those shown in boldface are tested.
AD674B/AD774BSPECIFICATIONS
(T
MIN
to T
MAX
with V
CC
= +15 V 10% or +12 V 5%,
V
LOGIC
= +5 V 10%, V
EE
= 15 V
10% or 12 V 5%, unless otherwise noted.)
REV. C
2
REV. C
3
CONVERTER START TIMING (Figure 1)
J, K, A, B Grades T Grade
Parameter
Symbol
Min Typ Max
Min Typ Max Unit
Conversion Time
8-Bit Cycle (AD674B)
t
C
6
8
10
6
8
10
s
12-Bit Cycle (AD674B) t
C
9
12
15
9
12
15
s
8-Bit Cycle (AD774B)
t
C
4
5
6
4
5
6
s
12-Bit Cycle (AD774B) t
C
6
7.3
8
6
7.3
8
s
STS Delay from CE
t
DSC
200
225
ns
CE Pulsewidth
t
HEC
50
50
ns
CS to CE Setup
t
SSC
50
50
ns
CS Low During CE High
t
HSC
50
50
ns
R/
C to CE Setup
t
SRC
50
50
ns
R/
C LOW During CE High t
HRC
50
50
ns
A
0
to CE Setup
t
SAC
0
0
ns
A
0
Valid During CE High
t
HAC
50
50
ns
READ TIMING--FULL CONTROL MODE (Figure 2)
J, K, A, B Grades T Grade
Parameter
Symbol
Min Typ Max Min Typ Max Unit
Access Time
C
L
= 100 pF
t
DD
1
75
150
75
150
ns
Data Valid After CE Low
t
HD
25
2
25
2
ns
20
3
15
4
ns
Output Float Delay
t
HL
5
150
150
ns
CS to CE Setup
t
SSR
50
50
ns
R/
C to CE Setup
t
SRR
0
0
ns
A
0
to CE Setup
t
SAR
50
50
ns
CS Valid After CE Low
t
HSR
0
0
ns
R/
C High After CE Low
t
HRR
0
0
ns
A
0
Valid After CE Low
t
HAR
50
50
ns
NOTES
1
t
DD
is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.
2
0
C to T
MAX
.
3
At 40
C.
4
At 55
C.
5
t
HL
is defined as the time required for the data lines to change 0.5 V when loaded with
the circuit of Figure 3b.
Specifications shown in boldface are tested on all devices at final electrical test with
worst case supply voltages at T
MIN
, 25
C, and T
MAX
. Results from those tests are used
to calculate outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested.
Specifications subject to change without notice.
Parameter
Test Conditions
Min
Max
Unit
LOGIC INPUTS
V
IH
High Level Input Voltage
2.0
V
LOGIC
+ 0.5
V
V
IL
Low Level Input Voltage
0.5
+0.8
V
I
IH
High Level Input Current
V
IN
= V
LOGIC
10
+10
A
I
IL
Low Level Input Current
V
IN
= 0 V
10
+10
A
C
IN
Input Capacitance
10
pF
LOGIC OUTPUTS
V
OH
High Level Output Voltage
I
OH
= 0.5 mA
2.4
V
V
OL
Low Level Output Voltage
I
OL
= 1.6 mA
0.4
V
I
OZ
High-Z Leakage Current
V
IN
= 0 to V
LOGIC
10
+10
A
C
OZ
High-Z Output Capacitance
10
pF
DIGITAL SPECIFICATIONS
(For all grades T
MIN
to T
MAX
with V
CC
= +15 V
10% or +12 V 5%, V
LOGIC
= +5 V 10%,
V
EE
= 15 V 10% or 12 V 5%, unless otherwise noted.)
SWITCHING SPECIFICATIONS
(For all grades T
MIN
to T
MAX
with V
CC
= +15 V 10% or +12 V 5%,
V
LOGIC
= +5 V 10%, V
EE
= 15 V 10% or 12 V 5%, unless otherwise noted.)
t
HEC
t
HSC
t
SSC
t
HRC
t
SRC
t
SAC
t
HAC
t
C
t
DSC
CE
CS
R/
C
A
0
STS
DB11 DB0
HIGH
IMPEDANCE
Figure 1. Convert Start Timing
t
SSR
CE
CS
R/
C
A
0
STS
DB11 DB0
t
HSR
t
HRR
t
HAR
t
HD
t
SAR
t
SRR
HIGH
IMPEDANCE
DATA
VALID
HIGH
IMPEDANCE
t
HL
t
DD
Figure 2. Read Cycle Timing
DB
N
3k
100pF
DB
N
3k
100pF
5V
HIGH-Z TO LOGIC 0
HIGH-Z TO LOGIC 1
High-Z to Logic 1 High-Z to Logic 0
Figure 3a. Load Circuit for Access Time Test
DB
N
3k
100pF
LOGIC 1 TO HIGH-Z
DB
N
3k
100pF
5V
LOGIC 0 TO HIGH-Z
Logic 1 to High-Z Logic 0 to High-Z
Figure 3b. Load Circuit for Output Float Delay Test
AD674B/AD774B
REV. C
4
AD674B/AD774B
TIMING--STAND ALONE MODE (Figures 4a and 4b)
J, K, A, B Grades T Grade
Parameter
Symbol
Min Typ Max
Min Typ Max Unit
Data Access Time
t
DDR
150
150
ns
Low R/
C Pulsewidth
t
HRL
50
50
ns
STS Delay from R/
C
t
DS
200
225
ns
Data Valid After R/
C Low
t
HDR
25
25
ns
STS Delay After Data Valid t
HS
30
200
600
30
200 600
ns
High R/
C Pulsewidth
t
HRH
150
150
ns
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
*
V
CC
to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +16.5 V
V
EE
to Digital Common . . . . . . . . . . . . . . . . . . . . 0 to 16.5 V
V
LOGIC
to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +7 V
Analog Common to Digital Common . . . . . . . . . . . . . . .
1 V
Digital Inputs to Digital Common . . . 0.5 V to V
LOGIC
+0.5 V
Analog Inputs to Analog Common . . . . . . . . . . . . V
EE
to V
CC
20 V
IN
to Analog Common . . . . . . . . . . . . . . . . . . . . . .
24 V
REF OUT . . . . . . . . . . . . . . . . . . Indefinite Short to Common
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to V
CC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175
C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300
C
Storage Temperature . . . . . . . . . . . . . . . . . . 65
C to +150C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
R/
C
STS
DB11DB0
DATA
VALID
DATA VALID
t
HRL
t
DS
HIGHZ
t
HS
t
HDR
t
C
Flgure 4a. Standalone Mode Timing Low Pulse R/
C
R/
C
STS
DB11DB0
HIGHZ
HIGHZ
DATA
VALID
t
HRH
t
DS
t
DDR
t
HDR
t
C
t
HL
Figure 4b. Standalone Mode Timing High Pulse for R/
C
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD674B/AD774B features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Conversion
INL
Package
Package
Model
l
Temperature
Time (max)
(T
MIN
to T
MAX
)
Description
Option
2
AD674BJN
0
C to 70C
15
s
1 LSB
Plastic DIP
N-28
AD674BKN
0
C to 70C
15
s
1/2 LSB
Plastic DIP
N-28
AD674BAR
40
C to +85C
15
s
1 LSB
Plastic SOIC
R-28
AD674BBR
40
C to +85C
15
s
1/2 LSB
Plastic SOIC
R-28
AD674BAD
40
C to +85C
15
s
1 LSB
Ceramic DIP
D-28
AD674BBD
40
C to +85C
15
s
1/2 LSB
Ceramic DIP
D-28
AD674BTD
55
C to +125C
15
s
1 LSB
Ceramic DIP
D-28
AD774BJN
0
C to 70C
8
s
1 LSB
Plastic DIP
N-28
AD774BKN
0
C to 70C
8
s
1/2 LSB
Plastic DIP
N-28
AD774BAR
40
C to +85C
8
s
1 LSB
Plastic SOIC
R-28
AD774BBR
40
C to +85C
8
s
1/2 LSB
Plastic SOIC
R-28
AD774BAD
40
C to +85C
8
s
1 LSB
Ceramic DIP
D-28
AD774BBD
40
C to +85C
8
s
1/2 LSB
Ceramic DIP
D-28
AD774BTD
55
C to +125C
8
s
1 LSB
Ceramic DIP
D-28
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military
Products Databook or the current AD674B/ AD774B/883B data sheet.
2
N = Plastic DIP; D = Hermetic DIP; R = Plastic SOIC.
REV. C
5
DEFINITION OF SPECIFICATIONS
Linearity Error
Linearity error refers to the deviation of each individual code
from a line drawn from "zero" through "full scale." The point
used as "zero" occurs 1/2 LSB (1.22 mV for 10 V span) before
the first code transition (all zeroes to only the LSB "on"). "Full
scale" is defined as a level 1 1/2 LSB beyond the last code tran-
sition (to all ones). The deviation of a code from the true straight
line is measured from the middle of each particular code.
The K, B, and T grades are guaranteed for maximum nonlinear-
ity of
1/2 LSB. For these grades, this means that an analog
value that falls exactly in the center of a given code width will
result in the correct digital output code. Values nearer the upper
or lower transition of the code width may produce the next upper
or lower digital output code. The J and A grades are guaranteed
to
1 LSB max error. For these grades, an analog value that
falls within a given code width will result in either the correct
code for that region or either adjacent one.
Note that the linearity error is not user adjustable.
Differential Linearity Error (No Missing Codes)
A specification that guarantees no missing codes requires that
every code combination appear in a monotonic increasing sequence
as the analog input level is increased. Thus every code must have a
finite width. The AD674B and AD774B guarantee no missing codes
to 12-bit resolution, requiring that all 4096 codes must be present
over the entire operating temperature ranges.
Unipolar Offset
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the actual
transition from that point. This offset can be adjusted as discussed
later. The unipolar offset temperature coefficient specifies the
maximum change of the transition point over temperature,
with or without external adjustment.
Bipolar Offset
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
Quantization Uncertainty
Analog-to-digital converters exhibit an inherent quantization
uncertainty of
1/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be reduced
for a converter of given resolution.
Left-Justified Data
The output data format is left-justified. This means that the
data represents the analog input as a fraction of full scale, rang-
ing from 0 to 4095/4096. This implies a binary point 4095 to
the left of the MSB.
Full-Scale Calibration Error
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 V for 10.000 V full scale). The full-scale cali-
bration error is the deviation of the actual level at the last transi-
tion from the ideal level. This error, which is typically 0.05% to
0.1% of full scale, can be trimmed out as shown in Figures 7
and 8. The full-scale calibration error over temperature is given
with and without the initial error trimmed out. The temperature
coefficients for each grade indicate the maximum change in the
full-scale gain from the initial value using the internal 10 V
reference.
Temperature Drift
The temperature drift for full-scale calibration, unipolar offset,
and bipolar offset specifies the maximum change from the initial
(25
C) value to the value at T
MIN
or T
MAX
.
Power Supply Rejection
The standard specifications assume use of +5.00 V and
15.00 V
or
12.00 V supplies. The only effect of power supply error on
the performance of the device will be a small change in the
full-scale calibration. This will result in a linear change in all
low-order codes. The specifications show the maximum full-
scale change from the initial value with the supplies at the
various limits.
Code Width
A fundamental quantity for A/D converter specifications is the
code width. This is defined as the range of analog input values for
which a given digital output code will occur. The nominal value
of a code width is equivalent to 1 least significant bit (LSB) of the
full-scale range or 2.44 mV out of 10 V for a 12-bit ADC.
AD674B/AD774B
REV. C
6
AD674B/AD774B
PIN FUNCTION DESCRIPTIONS
Symbol
Pin No. Type
* Name and Function
AGND
9 P
Analog Ground (Common)
A
0
4 DI
Byte Address/Short Cycle. If a conversion is started with A
0
Active LOW, a full 12-bit conversion
cycle is initiated. If A
0
is Active HIGH during a convert start, a shorter 8-bit conversion cycle
results. During Read (R/
C = 1) with 12/8 LOW, A
0
= LOW enables the 8 most significant bits,
and A
0
= HIGH enables DB3DB0 and sets DB7DB4 = 0.
BIP OFF
12 AI
Bipolar Offset. Connect through a 50
resistor to REF OUT for bipolar operation or to Analog
Common for unipolar operation.
CE
6 DI
Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation.
CS
3 DI
Chip Select. Chip Select is Active LOW.
DB11DB8 2724 DO
Data Bits 11 through 8. In the 12-bit format (see 12/
8 and A
0
pins) these pins provide the upper
4 bits of data. In the 8-bit format, they provide the upper 4 bits when A
0
is LOW and are
disabled when A
0
is HIGH.
DB7DB4
2320 DO
Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the
8-bit format they provide the middle 4 bits when A
0
is LOW and all zeroes when A
0
is HIGH.
DB3DB0
1916 DO
Data Bits 3 through 0. In both the 12-bit and 8-bit format these pins provide the lower 4 bits of
data when A
0
is HIGH; they are disabled when A
0
is LOW.
DGND
15 P
Digital Ground (Common)
REF OUT
8 AO
10 V Reference Output
R/
C
5 DI
Read/Convert. In the full control mode R/
C is Active HIGH for a read operation and Active LOW
for a convert operation. In the standalone mode, the falling edge of R/
C initiates a conversion.
REF IN
10 AI
Reference Input is connected through a 50
resistor to +10 V Reference for normal operation.
STS
28 DO
Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is
completed.
V
CC
7 P
+12 V/+15 V Analog Supply
V
EE
11 P
12 V/15 V Analog Supply
V
LOGIC
1 P
5 V Logic Supply
10 V
IN
13 AI
10 V Span Input, 0 V to +10 V unipolar mode or 5 V to +5 V bipolar mode. When using the
20 V Span, 10 V
IN
should not be connected.
20 V
IN
14 AI
20 V Span Input, 0 V to +20 V unipolar mode or 10 V to +10 V bipolar mode. When using the
10 V Span, 20 V
IN
should not be connected.
12/
8
2 DI
The 12/
8 pin determines whether the digital output data is to be organized as two 8-bit words
(12/
8 LOW) or a single 12-bit word (12/8 HIGH).
*Types: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD674B
OR
AD774B
V
LOGIC
12/
8
CS
A
0
R/
C
CE
V
CC
REF OUT
AGND
REF IN
V
EE
BIP OFF
10 V
IN
20 V
IN
STS
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
DGND
REV. C
7
CIRCUIT OPERATION
The AD674B and AD774B are complete 12-bit monolithic A/D
converters that require no external components to provide the
complete successive-approximation analog-to-digital conversion
function. A block diagram is shown in Figure 5.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD674B/AD774B
5V SUPPLY
V
LOGIC
DATA MODE SELECT
12/
8
CHIP SELECT
CS
BYTE ADDRESS/
SHORT CYCLE A
0
READ/CONVERT R/
C
CHIP ENABLE
CE
12V/15V SUPPLY
V
CC
10V REFERENCE
REF OUT
ANALOG COMMON
AC
REFERENCE INPUT
REF IN
12V/ 15V SUPPLY
V
EE
BIPOLAR OFFSET
BIPOFF
10V SPAN INPUT
10V
IN
20V SPAN INPUT
20V
IN
STATUS
STS
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
DIGITAL
COMMON DC
CONTROL
VOLTAGE
DIVIDER
N
Y
B
B
L
E
A
MSB
3
S
T
A
T
E
O
U
T
P
U
T
B
U
F
F
E
R
S
LSB
N
Y
B
B
L
E
B
N
Y
B
B
L
E
C
CLOCK
SAR
12
10V
REF
+
COMP
I DAC
+
199.95
k
DAC
N
V
EE
I REF
DIGITAL
DATA
OUTPUTS
Figure 5. Block Diagram of AD674B and AD774B
When the control section is commanded to initiate a conversion
(as described later) it enables the clock and resets the
successive-approximation register (SAR) to all zeroes. Once a
conversion cycle has begun, it cannot be stopped or restarted
and data is not available from the output buffers. The SAR,
timed by the clock, will sequence through the conversion cycle
and return an end-of-convert flag to the control section. The
control section will then disable the clock, bring the output
status flag low, and enable control functions to allow data read
by external command.
During the conversion cycle, the internal 12-bit current output
DAC is sequenced by the SAR from the most significant bit
(MSB) to least significant bit (LSB) to provide an output cur-
rent that accurately balances the input signal current through
the divider network. The comparator determines whether the
addition of each successively weighted bit current causes the
DAC current sum to be greater or less than the input current; if
the sum is less, the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12-bit binary code
that accurately represents the input signal to within
1/2 LSB.
The temperature-compensated reference provides the primary
voltage reference to the DAC and guarantees excellent stability
with both time and temperature. The reference is trimmed to
10.00 V
1%; it can supply up to 2.0 mA to an external load in
addition to the requirements of the reference input resistor
(0.5 mA) and bipolar offset resistor (0.5 mA). Any external load
on the reference must remain constant during conversion. The
thin-film application resistors are trimmed to match the full-
scale output current of the DAC. The input divider network
provides a 10 V or 20 V input range. The bipolar offset resistor
is grounded for unipolar operation and connected to the 10 V
reference for bipolar operation.
DRIVING THE ANALOG INPUT
The AD674B and AD774B are successive-approximation analog-
to-digital converters. During the conversion cycle, the ADC input
current is modulated by the DAC test current at approximately
a 1 MHz rate. Thus it is important to recognize that the signal
source driving the ADC must be capable of holding a constant
output voltage under dynamically changing load conditions.
CURRENT
OUTPUT
DAC
ANALOG COMMON
CURRENT
LIMITING
RESISTORS
FEEDBACK TO AMPLIFIER
ADC
COMPARATOR
I
IN
I
TEST
R
IN
I
DIFF
I
IN
IS MODULATED BY
CHANGES IN TEST CURRENT.
AMPLIFIER PULSE LOAD
RESPONSE LIMITED BY
OPEN-LOOP OUTPUT IMPEDANCE.
V
V+
SAR
Figure 6. Op Amp--ADC Interface
The closed-loop output impedance of an op amp is equal to the
open-loop output impedance (usually a few hundred ohms)
divided by the loop gain at the frequency of interest. It is often
assumed that the loop gain of a follower-connected op amp is
sufficiently high to reduce the closed-loop output impedance to
a negligibly small value, particularly if the signal is low fre-
quency. However, the amplifier driving the ADC must either
have sufficient loop gain at 1 MHz to reduce the closed-loop
output impedance to a low value or have low open-loop output
impedance. This can be accomplished by using a wideband op
amp, such as the AD711.
If a sample-hold amplifier is required, the monolithic AD585 or
AD781 is recommended, with the output buffer driving the
AD674B or AD774B input directly. A better alternative is the
AD1674, which is a 10
s sampling ADC in the same pinout as the
AD574A, AD674A, or AD774B and is functionally equivalent.
SUPPLY DECOUPLING AND LAYOUT
CONSIDERATION
It is critical that the power supplies be filtered, well regulated,
and free from high-frequency noise. Use of noisy supplies will
cause unstable output codes. Switching power supplies is not
recommended for circuits attempting to achieve 12-bit accuracy
unless great care is used in filtering any switching spikes present
in the output. Few millivolts of noise represent several counts of
error in a 12-bit ADC.
Decoupling capacitors should be used on all power supply pins;
the 5 V supply decoupling capacitor should be connected directly
from Pin 1 to Pin 15 (digital common) and the +V
CC
and V
EE
pins should be decoupled directly to analog common (Pin 9). A
suitable decoupling capacitor is a 4.7
F tantalum type in paral-
lel with a 0.1
F ceramic disc type.
AD674B/AD774B
REV. C
8
AD674B/AD774B
Circuit layout should attempt to locate the ADC, associated
analog input circuitry, and interconnections as far as possible
from logic circuitry. For this reason, the use of wire-wrap circuit
construction is not recommended. Careful printed-circuit layout
and manufacturing is preferred.
UNIPOLAR RANGE CONNECTIONS FOR THE AD674B
AND AD774B
The AD674B and AD774B contain all the active components
required to perform a complete 12-bit A/D conversion. Thus,
for most situations, all that is necessary is connection of the
power supplies (+5 V, +12/+15 V, and 12/15 V), the analog
input, and the conversion initiation command, as discussed on
the next page.
2
3
4
5
6
8
12
13
10
14
9
AD674B/AD774B
STS 28
HIGH BITS
2427
MIDDLE BITS
2023
LOW BITS
1619
+15V 7
15V 11
DIG COM 15
+5V 1
100
R2
GAIN
R1
100k
OFFSET
+12V/
+15V
12V/
15V
100k
100
0 TO 10V
ANALOG
INPUTS
0 TO 20V
12/
8
CS
A
0
R/
C
CE
REF OUT
BIP OFF
10V
IN
REF IN
20V
IN
ANA COM
Figure 7. Unipolar Input Connections
All of the thin-film application resistors of the AD674B and
AD774B are factory trimmed for absolute calibration. Therefore,
in many applications, no calibration trimming will be required.
The absolute accuracy for each grade is given in the specification
tables. For example, if no trims are used,
2 LSB max zero offset
error and
0.25% (10 LSB) max full-scale error are guaranteed.
If the offset trim is not required, Pin 12 can be connected directly
to Pin 9; the two resistors and trimmer for Pin 12 are then not
needed. If the full-scale trim is not required, a 50
1% metal
film resistor should be connected between Pin 8 and Pin 10.
The analog input is connected between Pins 13 and 9 for a 0 V
to 10 V input range, between Pins 14 and 9 for a 0 V to 20 V
input range. Input signals beyond the supplies are easily accommo-
dated. For the 10 V span input, the LSB has a nominal value of
2.44 mV; for the 20 V span, 4.88 mV. If a 10.24 V range is
desired (nominal 2.5 mV/bit), the gain trimmer (R2) should be
replaced by a 50
resistor and a 200 trimmer inserted in
series with the analog input to Pin 13 (for a full-scale range of
20.48 V [5 mV/bit] use a 500
trimmer into Pin 14). The
gain trim described below is now done with these trimmers.
The nominal input impedance into Pin 13 is 5 k
, and into Pin
14 is 10 k
.
UNIPOLAR CALIBRATION
The connections for unipolar ranges are shown in Figure 7. The
AD674B or AD774B is trimmed to a nominal 1/2 LSB offset so
that the exact analog input for a given code will be in the middle
of that code (halfway between the transitions to the codes above
and below it). Thus, when properly calibrated, the first transition
(from 0000 0000 0000 to 0000 0000 0001) will occur for an input
level of +1/2 LSB (1.22 mV for 10 V range).
If Pin 12 is connected to Pin 9, the unit will behave in this manner,
within specifications. If the offset trim (R1) is used, it should be
trimmed as above, although a different offset can be set for a
particular system requirement. This circuit will give approximately
15 mV of offset trim range.
The full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 for a 10 V range). Trim R2 to
give the last transition (1111 1111 1110 to 1111 1111 1111).
BIPOLAR OPERATION
The connections for bipolar ranges are shown in Figure 8.
Again, as for the unipolar ranges, if the offset and gain specifica-
tions are sufficient, one or both of the trimmers shown can be
replaced by a 50
1% fixed resistor. The analog input is
applied as for the unipolar ranges. Bipolar calibration is similar
to unipolar calibration. First, a signal 1/2 LSB above negative
full scale (4.9988 V for the
5 V range) is applied and R1 is
trimmed to give the first transition (0000 0000 0000 to 0000
0000 0001). Then a signal 1 1/2 LSB below positive full scale
(+4.9963 V for the
5 V range) is applied and R2 trimmed to
give the last transition (1111 1111 1110 to 1111 1111 1111).
AD674B/AD774B
HIGH BITS
2427
MIDDLE BITS
2023
LOW BITS
1619
100
R2
GAIN
ANALOG
INPUTS
10V
R1
100
OFFSET
5V
2
3
4
5
6
8
12
13
10
14
9
STS 28
+15V 7
15V 11
DIG COM 15
+5V 1
12/
8
CS
A
0
R/
C
CE
REF OUT
BIP OFF
10V
IN
REF IN
20V
IN
ANA COM
Figure 8. Bipolar Input Connections
GROUNDING CONSIDERATIONS
The analog common at Pin 9 is the ground reference point for
the internal reference and is thus the "high quality" ground for
the ADC; it should be connected directly to the analog reference
point of the system. To achieve the high-accuracy performance
available from the ADC in an environment of high digital noise
content, the analog and digital commons must be connected
together at the package. In some situations, the digital common
at Pin 15 can be connected to the most convenient ground ref-
erence point; digital power return is preferred.
REV. C
9
TO
OUTPUT
BUFFERS
CE
CS
R/
C
A
0
12/
8
NYBBLE A
ENABLE
NYBBLE B
ENABLE
NYBBLE C
ENABLE
NYBBLE = 0
ENABLE
STATUS
CLK EN
HIGH IF CONVERSION
IN PROGRESS
SAR
RESET
EOC 12
EOC 8
START CONVERT
S
R
Q
QB
READ
VALUE OF A
0
AT LAST CONVERT COMMAND
D
EN
D
EN
Q
R
S
Q
Figure 9. Equivalent Internal Logic Circuitry
CONTROL LOGIC
The AD674B and AD774B contain on-chip logic to provide
conversion initiation and data read operations from signals
commonly available in microprocessor systems; this internal
logic circuitry is shown in Figure 9.
The control signals CE,
CS, and R/C control the operation of
the converter. The state of R/
C when CE and CS are both
asserted determines whether a data read (R/
C = 1) or a convert
(R/
C = 0) is in progress. The register control inputs, A
0
and
12/
8, control conversion length and data format. If a conversion
is started with A
0
low, a full 12-bit conversion cycle is initiated.
If A
0
is high during a convert start, a shorter 8-bit conversion
cycle results. During data read operations, A
0
determines
whether the three-state buffers containing the 8 MSBs of the
conversion result (A
0
= 0) or the 4 LSBs (A
0
= 1) are enabled.
The 12/
8 pin determines whether the output data is to be orga-
nized as two 8-bit words (12/
8 tied to DIGITAL COMMON)
or a single 12-bit word (12/
8 tied to V
LOGIC
). In the 8-bit mode,
the byte addressed when A
0
is high contains the 4 LSBs from
the conversion followed by four trailing zeroes. This organiza-
tion allows the data lines to be overlapped for direct interface to
8-bit buses without the need for external three-state buffers.
An output signal, STS, indicates the status of the converter.
STS goes high at the beginning of a conversion and returns low
when the conversion cycle is complete.
Table I. Truth Table
CE
CS R/C 12/8 A
0
Operation
0
X
X
X
X
None
X
1
X
X
X
None
1
0
0
X
0
Initiate 12-Bit Conversion
1
0
0
X
1
Initiate 8-Bit Conversion
1
0
1
1
X
Enable 12-Bit Parallel Output
1
0
1
0
0
Enable 8 Most Significant Bits
1
0
1
0
1
Enable 4 LSBs + 4 Trailing Zeroes
The ADC may be operated in one of two modes, the full-control
mode and the standalone mode. The full-control mode uses all
the control signals and is useful in systems that address decode
multiple devices on a single data bus. The standalone mode is
useful in systems with dedicated input ports available. In gen-
eral, the standalone mode is capable of issuing start-convert
commands on a more precise basis and therefore produces
higher accuracy results. The following sections describe these
two modes in more detail.
FULL-CONTROL MODE
Chip Enable (CE), Chip Select (
CS), and Read/Convert (R/C)
are used to control Convert or Read modes of operation. Either
CE or
CS may be used to initiate a conversion. The state of R/C
when CE and
CS are both asserted determines whether a data
Read (R/
C = 1) or a Convert (R/C = 0) is in progress. R/C
should be LOW before both CE and
CS are asserted; if R/C is
HIGH, a Read operation will momentarily occur, possibly
resulting in system bus contention.
AD674B/AD774B
REV. C
10
AD674B/AD774B
STANDALONE MODE
"Standalone" mode is useful in systems with dedicated input
ports available and thus not requiring full bus interface capabil-
ity. Standalone mode applications are generally able to issue
conversion start commands more precisely than full-control
mode, resulting in improved accuracy.
CE and 12/
8 are wired HIGH, CS and A
0
are wired LOW, and
conversion is controlled by R/
C. The three-state buffers are
enabled when R/
C is HIGH and a conversion starts when R/C
goes LOW. This gives rise to two possible control signals--a
high pulse or a low pulse. Operation with a low pulse is shown
in Figure 4a. In this case, the outputs are forced into the high
impedance state in response to the falling edge of R/
C and
return to valid logic levels after the conversion cycle is completed.
The STS line goes HIGH 200 ns after R/C goes LOW and
returns low 600 ns after data is valid.
If conversion is initiated by a high pulse as shown in Figure 4b,
the data lines are enabled during the time when R/
C is HIGH.
The falling edge of R/
C starts the next conversion, and the data
lines return to three-state (and remain three-state) until the next
high pulse of R/
C.
CONVERSION TIMING
Once a conversion is started, the STS line goes HIGH. Convert
start commands will be ignored until the conversion cycle is
complete. The output data buffers can be enabled up to 1.2
s
prior to STS going LOW. The STS line will return LOW at the
end of the conversion cycle.
The register control inputs, A
0
and 12/
8, control conversion
length and data format. If a conversion is started with A
0
LOW,
a full 12-bit conversion cycle is initiated. If A
0
is HIGH during a
convert start, a shorter 8-bit conversion cycle results.
During data read operations, A
0
determines whether the three-
state buffers containing the 8 MSBs of the conversion result
(A
0
= 0) or the 4 LSBs (A
0
= 1) are enabled. The 12/
8 pin
determines whether the output data is to be organized as two
8-bit words (12/
8 tied LOW) or a single 12-bit word (12/8 tied
HIGH). In the 8-bit mode, the byte addressed when A
0
is high
contains the 4 LSBs from the conversion followed by four trail-
ing zeroes. This organization allows the data lines to be over-
lapped for direct interface to 8-bit buses without the need for
external three-state buffers.
GENERAL A/D CONVERTER INTERFACE
CONSIDERATIONS
A typical A/D converter interface routine involves several opera-
tions. First, a write to the ADC address initiates a conversion.
The processor must then wait for the conversion cycle to com-
plete, since most integrated circuit ADCs take longer than one
instruction cycle to complete a conversion. Valid data can, of
course, only be read after the conversion is complete. The
AD674B and AD774B provide an output signal (STS) which
indicates when a conversion is in progress. This signal can be
polled by the processor by reading it through an external three-
state buffer (or other input port). The STS signal can also
generate an interrupt upon completion of conversion if the sys-
tem timing requirements are critical and the processor has other
tasks to perform during the ADC conversion cycle. Another
possible time-out method is to assume that the ADC will take its
maximum conversion time to convert, and insert a sufficient
number of "no-op" instructions to ensure that this amount of
processor time is consumed.
Once conversion is complete, the data can be read. For convert-
ers with more data bits than are available on the bus, a choice of
data formats is required, and multiple read operations are
needed. The AD674B and AD774B include internal logic to
permit direct interface to 8-bit and 16-bit data buses, selected
by the 12/
8 input. In 16-bit bus applications (12/8 high) the
data lines (DB11 through DB0) may be connected to either the
12 most significant or 12 least significant bits of the data bus.
The remaining 4 bits should be masked in software. The inter-
face to an 8-bit data bus (12/
8 low) is done in a left-justified for-
mat. The even address (A
0
low) contains the 8 MSBs (DB11
through DB4). The odd address (A
0
high) contains the 4 LSBs
(DB3 through DB0) in the upper half of the byte, followed by
four trailing zeroes, thus eliminating bit masking instructions.
It is not possible to rearrange the output data lines for right-jus-
tified 8-bit bus interface.
DB11
(MSB)
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
(LSB)
0
0
0
0
D7
D0
XXX0
(EVEN ADDR)
XXX1
(ODD ADDR)
Figure 10. Data Format for 8-Bit Bus
REV. C
11
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Ceramic DIP Package
(D-28)
1.42 (36.07)
1.40 (35.56)
28
1
15
14
0.59
0.01
(14.98)
+
0.050 (12.83)
0.085
(2.16)
0.017 0.003
(0.43)
+
0.1 (2.54)
0.047 0.007
(1.19)
+
0.095 (2.41)
0.050
0.010
(1.27)
+
0.6 (15.24)
0.010 0.002
(0.254 0.05)
+
+
0.145 0.02
(3.68)
+
0.08 (2.0)
0.125 MIN (3.17)
SEATING
PLANE
30
o
0.05 (1.27)
0.045 (1.14)
28-Lead Plastic DIP Package
(N-28)
0.195 (4.95)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.625 (15.87)
0.600 (15.24)
28
1
14
15
PIN 1
0.580 (14.73)
0.485 (12.32)
1.565 (39.70)
1.380 (35.10)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.250
(6.35)
MAX
0.022 (0.558)
0.014 (0.356)
0.200 (5.05)
0.125 (3.18)
0.150
(3.81)
MIN
0.100
(2.54)
BSC
0.070
(1.77)
MAX
28-Lead Wide Body SOIC Package
(R-28)
0.0125 (0.32)
0.0091 (0.23)
8
0
0.0291 (0.74)
0.0098 (0.25)
45
0.0500 (1.27)
0.0157 (0.40)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
28
15
14
1
0.7125 (18.10)
0.6969 (17.70)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
AD674B/AD774B
REV. C
12
AD674B/AD774B
C00808-0-4/02(C)
PRINTED IN U.S.A.
Revision History
Location
Page
Data Sheet changed from REV. B to REV. C.
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Add 28-Lead Wide Body SOIC Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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