REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

MOS

12-Bit DACPORTs

AD7245A/AD7248A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

FEATURES
12-Bit CMOS DAC with Output Amplifier and

Reference

Improved AD7245/AD7248:

12 V to 15 V Operation

1/2 LSB Linearity Grade

Faster Interface30 ns typ Data Setup Time

Extended Plastic Temperature Range (40 C to +85 C)
Single or Dual Supply Operation
Low Power65 mW typ in Single Supply
Parallel Loading Structure: AD7245A
(8+4) Loading Structure: AD7248A

GENERAL DESCRIPTION

The AD7245A/AD7248A is an enhanced version of the industry
standard AD7245/AD7248. Improvements include operation
from 12 V to 15 V supplies, a

1/2 LSB linearity grade, faster

interface times and better full scale and reference variations with
V

. Additional features include extended temperature range

operation for commercial and industrial grades.

The AD7245A/AD7248A is a complete, 12-bit, voltage output,
digital-to-analog converter with output amplifier and Zener volt-
age reference on a monolithic CMOS chip. No external user
trims are required to achieve full specified performance.

Both parts are microprocessor compatible, with high speed data
latches and double-buffered interface logic. The AD7245A ac-
cepts 12-bit parallel data which is loaded into the input latch on
the rising edge of CS or WR. The AD7248A has an 8-bit wide
data bus with data loaded to the input latch in two write opera-
tions. For both parts, an asynchronous LDAC signal transfers
data from the input latch to the DAC latch and updates the ana-
log output. The AD7245A also has a CLR signal on the DAC latch
which allows features such as power-on reset to be implemented.

The on-chip 5 V buried Zener diode provides a low noise, tem-
perature compensated reference for the DAC. For single supply
operation, two output ranges of 0 V to +5 V and 0 V to +10 V
are available, while these two ranges plus an additional

5 V

range are available with dual supplies. The output amplifiers are
capable of developing +10 V across a 2 k

load to GND.

The AD7245A/AD7248A is fabricated in linear compatible
CMOS (LC

MOS), an advanced, mixed technology process that

combines precision bipolar circuits with low power CMOS logic.
The AD7245A is available in a small, 0.3" wide, 24-pin DIP and

DACPORT is a registered trademark of Analog Devices, Inc.

AD7245A FUNCTIONAL BLOCK DIAGRAM

AD7248A FUNCTIONAL BLOCK DIAGRAM

SOIC and in 28-terminal surface mount packages. The
AD7248A is packaged in a small, 0.3" wide, 20-pin DIP and
SOIC and in 20-terminal surface mount packages.

PRODUCT HIGHLIGHTS

1. The AD7245A/AD7248A is a 12-bit DACPORT

on a single

chip. This single chip design and small package size offer
considerable space saving and increased reliability over
multichip designs.

2. The improved interface times on the part allows easy, direct

interfacing to most modern microprocessors.

3. The AD7245A/AD7248A features a wide power supply range

allowing operation from 12 V supplies.

Parameter

Version

Units

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

Bits

Relative Accuracy @ +25

3/4

1/2

LSB max

MIN

to T

MAX

3/4

LSB max

MIN

to T

MAX

1/2

LSB max

= 15 V

Differential Nonlinearity

LSB max

Guaranteed Monotonic

Unipolar Offset Error @ +25

LSB max

= 0 V or 12 V to 15 V

MIN

to T

MAX

LSB max

Typical Tempco is

3 ppm of FSR

Bipolar Zero Error @ +25

LSB max

OFS

connected to REF OUT; V

= 12 V to 15 V

MIN

to T

MAX

LSB max

Typical Tempco is

3 ppm of FSR

DAC Gain Error

3, 6

LSB max

Full-Scale Output Voltage Error

@ +25

0.2

% of FSR max

= +15 V

Full Scale/

0.06

% of FSR/V max

= +12 V to +15 V

Full Scale/

0.01

% of FSR/V max

= 12 V to 15 V

Full-Scale Temperature Coefficient

ppm of FSR/

C max

= +15 V

REFERENCE OUTPUT

REF OUT @ +25

4.99/5.01 4.99/5.01

4.99/5.01 V min/V max

= +15 V

REF OUT/

mV/V max

= +12 V to +15 V

Reference Temperature Coefficient

ppm/

C typ

Reference Load Change

(

REF OUT vs.

mV max

Referenee Load Current Change (0100

DIGITAL INPUTS

Input High Voltage, V

INH

2.4

V min

Input Low Voltage, V

INL

0.8

V max

Input Current, I

A max

= 0 V to V

Input Capacitance

pF max

ANALOG OUTPUTS

Output Range Resistors

15/30

min/k

max

Output Voltage Ranges

+5, +10

= 0 V; Pin Strappable

Output Voltage Ranges

+5, +10, +5, +10,

+5, +10,

= 12 V to 15 V;

Pin Strappable

DC Output Impedance

0.5

typ

AC CHARACTERISTICS

Voltage Output Settling Time

Settling Time to Within

1/2 LSB of Final Value

Positive Full-Scale Change

s max

DAC Latch All 0s to All 1s

Negative Full-Scale Change

s max

DAC Latch All 1s to All 0s; V

= 12 V to 15 V

Output Voltage Slew Rate

1.5

s min

Digital Feedthrough

nV-s typ

Digital-to-Analog Glitch Impulse

nV-s typ

POWER REQUIREMENTS

+10.8/

+11.4/

V min/

For Specified Performance Unless Otherwise Stated

+16.5

+15.75

V max

10.8/

11.4/

V min/

For Specified Performance Unless Otherwise Stated

16.5

15.75

V max

@ +25

mA max

Output Unloaded; Typically 5 mA

MlN

to T

MAX

mA max

Output Unloaded

(Dual Supplies)

mA max

Output Unloaded; Typically 2 mA

NOTES

Power supply tolerance is

10% for A Version and

5% for B and T Versions.

Temperature ranges are as follows: A/B Versions; 40

C to +85

C; T Version; 55

C to +125

See Terminology.

With appropriate power supply tolerances.

FSR means Full-Scale Range and is 5 V for the 0 V to +5 V output range and 10 V for both the 0 V to +10 V and

5 V output ranges.

This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.

This error is calculated with respect to an ideal 4.9988 V on rhe 0 V to +5 V and

5 V ranges; it is calculated with respect to an ideal 9.9976 V on the

0 V to +10 V range. It includes the effects of internal voltage reference, gain and offset errors.

Full-Scale TC =

FS/

T, where

FS is the full-scale change from T

= +25

C to T

MIN

or T

MAX

Sample tested at +25

C to ensure compliance.

0 V to +10 V output range is available only when V

+14.25 V.

Specifications subject to change without notice.

AD7245A/AD7248ASPECIFICATIONS

REV. A

= +12 V to +15 V,

= O V or 12 V to 15 V,

AGND = DGND = O V, R

= 2 k

, C

= 1OO pF. All specifications T

MIN

to T

MAX

unless otherwise noted.)

AD7245A/AD7248A

REV. A

SWITCHING CHARACTERISTICS

= +12 V to +15 V;

= O V or 12 V to 15 V;

See Figures 5 and 7.)

Parameter

A, B Versions

T Version

Units

Conditions

@ +25

ns typ

Chip Select Pulse Width

MIN

to T

MAX

100

ns min

@ +25

ns typ

Write Pulse Width

MIN

to T

MAX

100

ns min

@ +25

ns min

Chip Select to Write Setup Time

MIN

to T

MAX

ns min

@ +25

ns min

Chip Select to Write Hold Time

MIN

to T

MAX

ns min

@ +25

ns typ

Data Valid to Write Setup Time

MIN

to T

MAX

ns min

@ +25

ns min

Data Valid to Write Hold Time

MIN

to T

MAX

ns min

@ +25

ns typ

Load DAC Pulse Width

MIN

to T

MAX

100

ns min

(AD7245A only)

@ +25

ns typ

Clear Pulse Width

MIN

to T

MAX

100

ns min

NOTES

Sample tested at +25

C to ensure compliance.

Power supply tolerance is

10% for A Version and

5% for B and T Versions.

ABSOLUTE MAXIMUM RATINGS

to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +17 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +17 V

to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to +34 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, V

Digital Input Voltage to DGND . . . . . . . . 0.3 V, V

+0.3 V

OUT

to AGND

. . . . . . . . . . . . . . . . . . . . . . . . . . . . V

, V

OUT

to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +24 V

OUT

to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 V, 0 V

REF OUT

to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

Power Dissipation (Any Package) to +75

C . . . . . . . . 450 mW

Derates above +75

C by . . . . . . . . . . . . . . . . . . . . 6 mW/

Operating Temperature

Commercial (A, B Versions) . . . . . . . . . . . 40

C to +85

Extended (S Version) . . . . . . . . . . . . . . . 55

C to +125

Storage Temperature . . . . . . . . . . . . . . . . . . 65

C to +150

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300

NOTES

Stresses above those listed under "Absolute Maximum Ratings" may cause per-

manent damage to the device. This is a stress rating only and functional opera-
tion of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

The output may be shorted to voltages in this range provided the power dissipa-

tion of the package is not exceeded. V

OUT

short circuit current is typically

80 mA.

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7245A/AD7248A features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of function-
ality.

AD7245A/AD7248A

REV. A

DAC GAIN ERROR

DAC Gain Error is a measure of the output error between an
ideal DAC and the actual device output with all 1s loaded after
offset error has been allowed for. It is, therefore defined as:

Measured Value--Offset--Ideal Value

where the ideal value is calculated relative to the actual refer-
ence value.

UNIPOLAR OFFSET ERROR

Unipolar Offset Error is a combination of the offset errors of the
voltage mode DAC and the output amplifier and is measured
when the part is configured for unipolar outputs. It is present
for all codes and is measured with all 0s in the DAC register.

BIPOLAR ZERO OFFSET ERROR

Bipolar Zero Offset Error is measured when the part is config-
ured for bipolar output and is a combination of errors from the
DAC and output amplifier. It is present for all codes and is
measured with a code of 2048 (decimal) in the DAC register.

SINGLE SUPPLY LINEARITY AND GAIN ERROR

The output amplifier of the AD7245A/AD7248A can have a
true negative offset even when the part is operated from a single
positive power supply. However, because the lower supply rail
to the part is 0 V, the output voltage cannot actually go nega-
tive. Instead the output voltage sits on the lower rail and this re-
sults in the transfer function shown. This is an offset effect and
the transfer function would have followed the dotted line if the
output voltage could have gone negative. Normally, linearity is
measured after offset and full scale have been adjusted or al-
lowed for. On the AD7245A/AD7248A the negative offset is al-
lowed for by calculating the linearity from the code which the
amplifier comes off the lower rail. This code is given by the
negative offset specification. For example, the single supply lin-
earity specification applies between Code 3 and Code 4095 for
the 25

C specification and between Code 5 and Code 4095 over

the T

MIN

to T

MAX

temperature range. Since gain error is also

measured after offset has been allowed for, it is calculated between
the same codes as the linearity error. Bipolar linearity and gain er-
ror are measured between Code 0 and Code 4095.

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

DAC CODE

{

TERMINOLOGY

RELATIVE ACCURACY

Relative Accuracy, or end-point nonlinearity, is a measure of the
actual deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after allow-
ing for zero and full scale and is normally expressed in LSBs or
as a percentage of full-scale reading.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of

1 LSB max over

the operating temperature range ensures monotonicity.

DIGITAL FEEDTHROUGH

Digital Feedthrough is the glitch impulse injected from the digi-
tal inputs to the analog output when the inputs change state. It
is measured with LDAC high and is specified in nV-s.

AD7245A ORDERING GUIDE

Temperature

Relative

Package

Model

Range

Accuracy

Option

AD7245AAN

C to +85

3/4 LSB

N-24

AD7245ABN

C to +85

1/2 LSB

N-24

AD7245AAQ

C to +85

3/4 LSB

Q-24

AD7245ATQ

C to +125

3/4 LSB

Q-24

AD7245AAP

C to +85

3/4 LSB

P-28A

AD7245AAR

C to +85

3/4 LSB

R-24

AD7245ABR

C to +85

1/2 LSB

R-24

AD7245ATE

C to +125

3/4 LSB

E-28A

NOTES

To order MIL-STD-883, Class B. processed parts, add /883B to part number.

Contact our local sales office for military data sheet and availability.

E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip

Carrier; Q = Cerdip; R = SOIC.

This grade will be available to /883B processing only.

AD7248A ORDERING GUIDE

Temperature

Relative

Package

Model

Range

Accuracy

Option

AD7248AAN

C to +85

3/4 LSB

N-20

AD7248ABN

C to +85

1/2 LSB

N-20

AD7248AAQ

C to +85

3/4 LSB

Q-20

AD7248ATQ

C to +125

3/4 LSB

Q-20

AD7248AAP

C to +85

3/4 LSB

P-20A

AD7248AAR

C to +85

3/4 LSB

R-20

AD7248ABR

C to +85

1/2 LSB

R-20

NOTES

To order MIL-STD-883, Class B, processed parts, add /883B to part number.

Contact our local sales office for military data sheet and availability.

N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.

This grade will be available to /883B processing only.

AD7245A/AD7248A

REV. A

AD7248A PIN FUNCTION DESCRIPTION

(DIP PIN NUMBERS)

Pin

Mnemonic

Description

Negative Supply Voltage (0 V for single

supply operation).

OFS

Bipolar Offset Resistor. This provides

access to the on-chip application resistors
and allows different output voltage ranges.

REF OUT

Reference Output. The on-chip reference

is provided at this pin and is used when
configuring the part for bipolar outputs.

AGND

Analog Ground.

DB11

Data Bit 11. Most Significant Bit (MSB).

6-11

DB10-DB5

Data Bit 10 to Data Bit 5.

DGND

Digital Ground.

13-16 DB4-DB1

Data Bit 4 to Data Bit 1.

DB0

Data Bit 0. Least Significant Bit (LSB).

Chip Select Input (Active LOW). The de-

vice is selected when this input is active.

Pin

Mnemonic

Description

Write Input (Active LOW). This is used in
conjunction with CS to write data into the
input latch of the AD7245A.

LDAC

Load DAC Input (Active LOW). This is
an asynchronous input which when active
transfers data from the input latch to the
DAC latch.

CLR

Clear Input (Active LOW). When this in-
put is active the contents of the DAC latch
are reset to all 0s.

Positive Supply Voltage.

Feedback Resistor. This allows access to
the amplifier's feedback loop.

OUT

Output Voltage. Three different output
voltage ranges can be chosen: 0 V to +5 V,
0 V to +10 V or 5 V to +5 V.

PLCC

AD7245A PIN CONFIGURATIONS

DIP and SOIC

LCCC

AD7245A/AD7248A

REV. A

AD7248A PIN FUNCTION DESCRIPTION

(ANY PACKAGE)

Pin

Mnemonic

Description

Negative Supply Voltage (0 V for single

supply operation).

OFS

Bipolar Offset Resistor. This provides

access to the on-chip application resistors
and allows different output voltage ranges.

REF OUT

Reference Output. The on-chip reference

is provided at this pin and is used when
configuring the part for bipolar outputs.

AGND

Analog Ground.

DB7

Data Bit 7.

DB6

Data Bit 6.

DB5

Data Bit 5.

DB4

Data Bit 4.

DB3

Data Bit 3.

DGND

Digital Ground.

DB2

Data Bit 2/Data Bit 10.

DB1

Data Bit 1/Data Bit 9.

DB0

Data Bit 0 (LSB)/Data Bit 8.

Pin

Mnemonic

Description

CSMSB

Chip Select Input for MS Nibble. (Active
LOW). This selects the upper 4 bits of the
input latch. Input data is right justified.

CSLSB

Chip Select Input for LS byte. (Active
LOW). This selects the lower 8 bits of the
input latch.

Write Input. This is used in conjunction
with CSMSB and CSLSB to load data
into the input latch of the AD7248A.

LDAC

Load DAC Input (Active LOW). This is
an asynchronous input which when active
transfers data from the input latch to the
DAC latch.

Positive Supply Voltage.

Feedback Resistor. This allows access to
the amplifier's feedback loop.

OUT

Output Voltage. Three different output
voltage ranges can be chosen: 0 V to

0 V to +10 V or 5 V to +5 V.

AD7248A PIN CONFIGURATIONS

LCCC

PLCC

DIP and SOIC

AD7245A/AD7248A

REV. A

CIRCUIT INFORMATION

D/A SECTION

The AD7245A/AD7248A contains a 12-bit voltage mode digi-
tal-to-analog converter. The output voltage from the converter
has the same positive polarity as the reference voltage allowing
single supply operation. The reference voltage for the DAC is
provided by an on-chip buried Zener diode.

The DAC consists of a highly stable, thin-film, R2R ladder and
twelve high-speed NMOS single-pole, double-throw switches.
The simplified circuit diagram for this DAC is shown in Figure 1.

Figure 1. D/A Simplified Circuit Diagram

The input impedance of the DAC is code dependent and can
vary from 8 k

to infinity. The input capacitance also varies

with code, typically from 50 pF to 200 pF.

OP AMP SECTION

The output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. The user has access to two gain
setting resistors which can be connected to allow different out-
put voltage ranges (discussed later). The buffer amplifier is ca-
pable of developing up to 10 V across a 2 k

load to GND.

The output amplifier can be operated from a single positive
power supply by tying V

= AGND = 0 V. The amplifier can

also be operated from dual supplies to allow a bipolar output
range of 5 V to +5 V. The advantages of having dual supplies
for the unipolar output ranges are faster settling time to voltages
near 0 V, full sink capability of 2.5 mA maintained over the en-
tire output range and elimination of the effects of negative offset
on the transfer characteristic (outlined previously). Figure 2
shows the sink capability of the amplifier for single supply
operation.

Figure 2. Typical Single Supply Sink Current vs.
Output Voltage

The small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. The output noise from the ampli-
fier is low with a figure of 25 nV/

at a frequency of 1 kHz.

The broadband noise from the amplifier has a typical peak-to-
peak figure of 150

V for a 1 MHz output bandwidth. There is

no significant difference in the output noise between single and
dual supply operation.

VOLTAGE REFERENCE

The AD7245A/AD7248A contains an internal low noise buried
Zener diode reference which is trimmed for absolute accuracy
and temperature coefficient. The reference is internally con-
nected to the DAC. Since the DAC has a variable input imped-
ance at its reference input the Zener diode reference is buffered.
This buffered reference is available to the user to drive the cir-
cuitry required for bipolar output ranges. It can be used as a ref-
erence for other parts in the system provided it is externally
buffered. The reference will give long-term stability comparable
with the best discrete Zener reference diodes. The performance
of the AD7245A/AD7248A is specified with internal reference,
and all the testing and trimming is done with this reference. The
reference should be decoupled at the REF OUT pin and recom-
mended decoupling components are 10

F and 0.1

F capaci-

tors in series with a 10

resistor. A simplified schematic of the

reference circuitry is shown in Figure 3.

Figure 3. Internal Reference

DIGITAL SECTION

The AD7245A/AD7248A digital inputs are compatible with ei-
ther TTL or 5 V CMOS levels. All data inputs are static pro-
tected MOS gates with typical input currents of less than 1 nA.
The control inputs sink higher currents (150

A max) as a result

of the fast digital interfacing. Internal input protection of all
logic inputs is achieved by on-chip distributed diodes.

The AD7245A/AD7248A features a very low digital feedthrough
figure of 10 nV-s in a 5 V output range. This is due to the volt-
age mode configuration of the DAC. Most of the impulse is ac-
tually as a result of feedthrough across the package.

INTERFACE LOGIC INFORMATION--AD7245A

Table I shows the truth table for AD7245A operation. The part
contains two 12-bit latches, an input latch and a DAC latch. CS
and WR control the loading of the input latch while LDAC con-
trols the transfer of information from the input latch to the
DAC latch. All control signals are level triggered; and therefore,
either or both latches may be made transparent, the input latch
by keeping CS and WR "LOW", the DAC latch by keeping
LDAC

"LOW." Input data is latched on the rising edge of WR.

AD7245A/AD7248A

REV. A

The data held in the DAC latch determines the analog output of
the converter. Data is latched into the DAC latch on the rising
edge of LDAC. This LDAC signal is an asynchronous signal
and is independent of WR. This is useful in many applications.
However, in systems where the asynchronous LDAC can occur
during a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. For ex-
ample, if LDAC goes LOW while WR is "LOW", then the
LDAC

signal must stay LOW for t

or longer after WR goes

high to ensure correct data is latched through to the output.

Table I. AD7245A Truth Table

CLR

LDAC WR

Function

Both Latches are Transparent

Both Latches are Latched

Input Latches Transparent

Input Latches Latched

DAC Latches Transparent

DAC Latches Latched

DAC Latches Loaded with all 0s

DAC Latches Latched with All
0s and Output Remains at
0 V or 5 V

Both Latches are Transparent
and Output Follows Input Data

H = High State L = Low State X = Don't Care

The contents of the DAC latch are reset to all 0s by a low level
on the CLR line. With both latches transparent, the CLR line
functions like a zero override with the output brought to 0 V in
the unipolar mode and 5 V in the bipolar mode for the dura-
tion of the CLR pulse. If both latches are latched, a "LOW"
pulse on the CLR input latches all 0s into the DAC latch and
the output remains at 0 V (or 5 V) after the CLR line has re-
turned "HIGH." The CLR line can be used to ensure powerup
to 0 V on the AD7245A output in unipolar operation and is also
useful, when used as a zero override, in system calibration
cycles.

Figure 4 shows the input control logic for the AD7245A and the
write cycle timing for the part is shown in Figure 5.

Figure 4. AD7245A Input Control Logic

Figure 5. AD7245A Write Cycle Timing Diagram

INTERFACE LOGIC INFORMATION--AD7248A

The input loading structure on the AD7248A is configured for
interfacing to microprocessors with an 8-bit wide data bus. The
part contains two 12-bit latches--an input latch and a DAC
latch. Only the data held in the DAC latch determines the ana-
log output from the converter. The truth table for AD7248A
operation is shown in Table II, while the input control logic dia-
gram is shown in Figure 6.

Figure 6. AD7248A Input Control Logic

CSMSB

, CSLSB and WR control the loading of data from the

external data bus to the input latch. The eight data inputs on
the AD7248A accept right justified data. This data is loaded to
the input latch in two separate write operations. CSLSB and
WR

control the loading of the lower 8-bits into the 12-bit wide

latch. The loading of the upper 4-bit nibble is controlled by
CSMSB

and WR. All control inputs are level triggered, and in-

put data for either the lower byte or upper 4-bit nibble is latched
into the input latches on the rising edge of WR (or either
CSMSB

or CSLSB). The order in which the data is loaded to

the input latch (i.e., lower byte or upper 4-bit nibble first) is not
important.

The LDAC input controls the transfer of 12-bit data from the
input latch to the DAC latch. This LDAC signal is also level
triggered, and data is latched into the DAC latch on the rising
edge of LDAC. The LDAC input is asynchronous and indepen-
dent of WR. This is useful in many applications especially in

AD7245A/AD7248A

REV. A

the simultaneous updating of multiple AD7248A outputs. How-
ever, in systems where the asynchronous LDAC can occur dur-
ing a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. In other
words, if LDAC goes low while WR and either CS input are low
(or WR and either CS go low while LDAC is low), then the
LDAC

signal must stay low for t

or longer after WR returns

high to ensure correct data is latched through to the output.
The write cycle timing diagram for the AD7248A is shown in
Figure 7.

Figure 7. AD7248A Write Cycle Timing Diagram

An alternate scheme for writing data to the AD7248A is to tie
the CSMSB and LDAC inputs together. In this case exercising
CSLSB

and WR latches the lower 8 bits into the input latch.

The second write, which exercises CSMSB, WR and LDAC
loads the upper 4-bit nibble to the input latch and at the same
time transfers the 12-bit data to the DAC latch. This automatic
transfer mode updates the output of the AD7248A in two write
operations. This scheme works equally well for CSLSB and
LDAC

tied together provided the upper 4-bit nibble is loaded to

the input latch followed by a write to the lower 8 bits of the in-
put latch.

Table II. AD7248A Truth Table

CSLSB CSMSB WR

LDAC

Function

I.oad LS Byte into Input Latch

Latches LS Byte into Input Latch

Loads MS Nibble into Input Latch

Latches MS Nibble into Input Latch

Loads Input Latch into DAC Latch

Latches Input Latch into DAC Latch

Loads MS Nibble into Input Latch and
Loads Input Latch into DAC Latch

No Data Transfer Operation

H = High State L = Low State

APPLYING THE AD7245A/AD7248A

The internal scaling resistors provided on the AD7245A/
AD7248A allow several output voltage ranges. The part can
produce unipolar output ranges of 0 V to +5 V or 0 V to +10 V
and a bipolar output range of 5 V to +5 V. Connections for the
various ranges are outlined below.

UNIPOLAR (0 V TO +10 V) CONFIGURATION

The first of the configurations provides an output voltage range
of 0 V to +10 V. This is achieved by connecting the bipolar off-
set resistor, R

OFS

, to AGND and connecting R

to V

OUT

this configuration the AD7245A/AD7248A can be operated
single supply (V

= 0 V = AGND). If dual supply performance

is required, a V

of 12 V to 15 V should be applied. Figure 8

shows the connection diagram for unipolar operation while the
table for output voltage versus the digital code in the DAC latch
is shown in Table III.

Figure 8. Unipolar (0 to +10 V) Configuration

Table III. Unipolar Code Table (0 V to +10 V Range)

DAC Latch Contents
MSB

LSB

Analog Output, V

OUT

1 1 1 1

+2 V

REF

4095

4096

1 0 0 0

0 0 0 0

0 0 0 1

+2 V

REF

2049

4096

1 0 0 0

0 0 0 0

+2 V

REF

2048

4096

= +

REF

0 1 1 1

1 1 1 1

+2 V

REF

2047

4096

0 0 0 0

0 0 0 1

+2 V

REF

4096

0 0 0 0

0 V

NOTE:

1 LSB = 2 V

REF

) = V

REF

2048

UNIPOLAR (0 V TO +5 V) CONFIGURATION

The 0 V to +5 V output voltage range is achieved by tying R

OFS

and V

OUT

together. For this output range the AD7245A/

AD7248A can be operated single supply (V

= 0 V) or dual

supply. The table for output voltage versus digital code is as in
Table III, with 2 · V

REF

replaced by V

REF

. Note that for this

range

1 LSB = V

REF

) = V

REF

4096

AD7245A/AD7248A

REV. A

BIPOLAR CONFIGURATION

The bipolar configuration for the AD7245A/AD7248A, which
gives an output voltage range from 5 V to +5 V, is achieved by
connecting the R

OFS

input to REF OUT and connecting R

and V

OUT

. The AD7245A/AD7248A must be operated from

dual supplies to achieve this output voltage range. The code
table for bipolar operation is shown in Table IV.

Table IV. Bipolar Code Table

DAC Latch Contents
MSB

LSB

Analog Output, V

OUT

1 1 1 1

REF

2047

2048

1 0 0 0

0 0 0 0

0 0 0 1

REF

2048

1 0 0 0

0 0 0 0

0 V

0 1 1 1

1 1 1 1

REF

2048

0 0 0 0

0 0 0 1

REF

2047

2048

0 0 0 0

REF

2048

REF

NOTE:

1 LSB = 2

REF

) = V

REF

2048

AGND BIAS

The AD7245A/AD7248A AGND pin can be biased above sys-
tem GND (AD7245A/AD7248A DGND) to provide an offset
"zero" analog output voltage level. With unity gain on the am-
plifier (R

OFS

= V

OUT

= R

) the output voltage, V

OUT

is ex-

pressed as:

OUT

= V

BIAS

+ D V

REF

where D is a fractional representation of the digital word in the
DAC latch and V

BIAS

is the voltage applied to the AD7245A/

AD7248A AGND pin.

Because the current flowing out of the AGND pin varies with
digital code, the AGND pin should be driven from a low imped-
ance source. A circuit configuration is outlined for AGND bias
in Figure 9 using the AD589, a +1.23 V bandgap reference.

If a gain of 2 is used on the buffer amplifier the output voltage,
V

OUT

is expressed as

OUT

= 2(V

BIAS

+ D V

REF

)

In this case care must be taken to ensure that the maximum out-
put voltage is not greater than V

3 V. The V

OUT

over-

head must be greater than 3 V to ensure correct operation of the
part. Note that V

and V

for the AD7245A/AD7248A must

be referenced to DGND (system GND). The entire circuit can
be operated in single supply with the V

pin of the AD7245A/

AD7248A connected to system GND.

Figure 9. AGND Bias Circuit

PROGRAMMABLE CURRENT SINK

Figure 10 shows how the AD7245A/AD7248A can be config-
ured with a power MOSFET transistor, the VN0300M, to pro-
vide a programmable current sink from V

or V

SOURCE

. The

VN0300M is placed in the feedback of the AD7245A/
AD7248A amplifier. The entire circuit can be operated in single
supply by tying the V

of the AD7245A/AD7248A to AGND.

The sink current, I

SINK

, can be expressed as:

SINK

REF

Figure 10. Programmable Current Sink

Using the VN0300M, the voltage drop across the load can typi-
cally be as large as V

SOURCE

6 V) with V

OUT

of the DAC at

+5 V. Therefore, for a current of 50 mA flowing in the R1 (with
all 1s in the DAC register) the maximum load is 200

with

SOURCE

= +15 V. The VN0300M can actually handle currents

up to 500 mA and still function correctly in the circuit, but in
practice the circuit must be used with larger values of V

SOURCE

otherwise it requires a very small load.

Since the tolerance value on the reference voltage of the
AD7245A/AD7248A is

0.2%, then the absolute value of I

SINK

can vary by

0.2% from device to device for a fixed value of R1.

Because the input bias current of the AD7245A/AD7248A's op
amp is only of the order of picoamps, its effect on the sink cur-
rent is negligible. Tying the R

OFS

input to R

input reduces this

effect even further and prevents noise pickup which could occur
if the R

OFS

pin was left unconnected.

AD7245A/AD7248A

REV. A

The circuit of Figure 10 can be modified to provide a program-
mable current source to AGND or V

SINK

(for V

SINK

, dual sup-

plies are required on the AD7245A/AD7248A). The AD7245A/
AD7248A is configured as before. The current through R1 is
mirrored with a current mirror circuit to provide the program-
mable source current (see CMOS DAC Application Guide,
Publication No. G872-30-10/84, for suitable current mirror cir-
cuit). As before the absolute value of the source current will be
affected by the

0.2% tolerance on V

REF

. In this case the per-

formance of the current mirror will also affect the value of the
source current.

FUNCTION GENERATOR WITH PROGRAMMABLE
FREQUENCY

Figure 11 shows how the AD7245A/AD7248A with the AD537,
voltage-to-frequency converter and the AD639, trigonometric
function generator to provide a complete function generator
with programmable frequency. The circuit provides square
wave, triwave and sine wave outputs, each output of

10 V

amplitude.

The AD7245A/AD7248A provides a programmable voltage to
the AD537 input. Since both the AD7245A/AD7248A and
AD537 are guaranteed monotonic, the output frequency will al-
ways increase with increasing digital code. The AD537 provides
a square wave output which is conditioned for

10 V by ampli-

fier A1. The AD537 also provides a differential triwave output.
This is conditioned by amplifiers A2 and A3 to provide the

1.8 V triwave required at the input of the AD639. The triwave

is further scaled by amplifier A4 to provide a

10 V output.

Adjusting the triwave applied to the AD639 adjust the distortion
performance of the sine wave output, (+10 V in configuration
shown). Amplitude, offset and symmetry of the triwave can af-
fect the distortion. By adjusting these, via VR1 and VR2, an
output sine wave with harmonic distortion of better than 50 dB
can be achieved at low and intermediate frequencies.

Using the capacitor value shown in Figure 11 for C

(i.e.,

680 pF) the output frequency range is 0 to 100 kHz over the
digital input code range. The step size for frequency increments
is 25 Hz. The accuracy of the output frequency is limited to 8 or
9 bits by the AD537, but is guaranteed monotonic to 12 bits.

MICROPROCESSOR INTERFACING--AD7245

AD7245A--8086A INTERFACE

Figure 12 shows the 8086 16-bit processor interfacing to the
AD7245A. In the setup shown the double buffering feature of
the DAC is not used and the LDAC input is tied LOW. AD0
AD11 of the 16-bit data bus are connected to the AD7245A
data bus (DB0-DB11). The 12-bit word is written to the
AD7245A in one MOV instruction and the analog output re-
sponds immediately. In this example the DAC address is D000.
A software routine for Figure 12 is given in Table V.

Figure 12. AD7245A to 8086 Interface

Figure 11. Programmable Function Generator

Table V. Sample Program for Loading AD7245A from 8086

ASSUME DS: DACLOAD, CS: DACLOAD

DACLOAD SEGMENT AT 000

00 8CC9

MOV CS,

: DEFINE DATA SEGMENT

02 8ED9

MOV DS,

: EQUAL TO CODE

SEGMENT REGISTER

04 BF00D0

0MOV DI,

: LOAD DI WITH D000

#D000

07 C705

MOV MEM, : DAC LOADED WITH WXYZ

"YZWX" #YZWX

0B EA00 00

: CONTROL IS RETURNED TO

0E 00 FF

THE MONITOR PROGRAM

AD7245A/AD7248A

REV. A

In a multiple DAC system the double buffering of the AD7245A
allows the user to simultaneously update all DACs. In Figure
13, a 12-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropri-
ate address, CS4 (i.e., LDAC) is brought LOW, updating all the
DACs simultaneously.

Figure 13. AD7245A to 8086 Multiple DAC Interface

AD7245A--MC68000 INTERFACE

Interfacing between the MC68000 and the AD7245A is accom-
plished using the circuit of Figure 14. Once again the AD7245A
is used in the single buffered mode. A software routine for load-
ing data to the AD7245A is given in Table VI. In this example
the AD7245A is located at address E000, and the 12-bit word is
written to the DAC in one MOVE instruction.

Figure 14. AD7245A to 68000 Interface

Table Vl. Sample Routine for Loading AD7245A from 68000

01000

MOVE.W

#X,D0

The desired DAC data, X,
is loaded into Data Re-
gister 0. X may be any
value between 0 and 4094
(decimal) or 0 and OFFF
(hexadecimal).

MOVE.W

D0,$E000

The Data X is transferred
between D0 and the
DAC Latch.

MOVE.B

#228,D7

Control is returned to the
System Monitor Program
using these two

TRAP

#14

instructions.

MICROPROCESSOR INTERFACE--AD7248A

Figure 15 shows the connection diagram for interfacing the
AD7248A to both the 8085A and 8088 microprocessors. This
scheme is also suited to the Z80 microprocessor, but the Z80
address/data bus does not have to be demultiplexed. Data to be
loaded to the AD7248A is right justified. The AD7248A is
memory mapped with a separate memory address for the input
latch high byte, the input latch low byte and the DAC latch.
Data is first written to the AD7248A input latch in two write
operations. Either the high byte or the low byte data can be
written first to the AD7248A input latch. A write to the
AD7248A DAC latch address transfers the input latch data to
the DAC latch and updates the output voltage. Alternatively,
the LDAC input can be asynchronous or can be common to a
number of AD7248As for simultaneous updating of a number of
voltage channels.

Figure 15. AD7248A to 8085A/8088 Interface

A connection diagram for the interface between the AD7248A
and 68008 microprocessor is shown in Figure 16. Once again
the AD7248A acts as a memory mapped device and data is right
justified. In this case the AD7248A is configured in the auto-
matic transfer mode which means that the high byte of the input
latch has the same address as the DAC latch. Data is written to
the AD7248A by first writing data to the AD7248A low byte.
Writing data to the high byte of the input latch also transfers the
input latch contents to the DAC latch and updates the output.

AD7245A/AD7248A

REV. A

Figure 16. AD7248A to 68008 Interface

An interface circuit for connections to the 6502 or 6809 micro-
processors is shown in Figure 17. Once again, the AD7248A is
memory mapped and data is right justified. The procedure for
writing data to the AD7248A is as outlined for the 8085A/8088.
For the 6502 microprocessor the

2 clock is used to generate

the WR, while for the 6809 the E signal is used.

Figure 17. AD7248A to 6502/6809 Interface

Figure 18 shows a connection diagram between the AD7248A
and the 8051 microprocessor. The AD7248A is port mapped in
this interface and is configured in the automatic transfer mode.
Data to be loaded to the input latch low byte is output to Port 1.
Output Line P3.0, which is connected to CSLSB of the
AD7248A, is pulsed to load data into the low byte of the input
latch. Pulsing the P3.1 line, after the high byte data has been set
up on Port 1, updates the output of the AD7248A. The WR in-
put of the AD7248A can be hardwired low in this application
because spurious address strobes on CSLSB and CSMSB do not
occur.

Figure 18. AD7248A to MCS-51 Interface

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