CONNECTION DIAGRAMS
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Ultralow Noise
BiFET Op Amp
AD743
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
PRODUCT HIGHLIGHTS
1. The low offset voltage and low input offset voltage drift of
the AD743 coupled with its ultralow noise performance
mean that the AD743 can be used for upgrading many
applications now using bipolar amplifiers.
2. The combination of low voltage and low current noise make
the AD743 ideal for charge sensitive applications such as
accelerometers and hydrophones.
3. The low input offset voltage and low noise level of the
AD743 provide >140 dB dynamic range.
4. The typical 10 kHz noise level of 2.9 nV/
Hz
permits a three
op amp instrumentation amplifier, using three AD743s, to be
built which exhibits less than 4.2 nV/
Hz
noise at 10 kHz
and which has low input bias currents.
100
1k
10k
100k
1
10
100
1000
1M
10M
SOURCE RESISTANCE
OP27 &
RESISTOR
AD743 + RESISTOR
RESISTOR NOISE ONLY
AD743 & RESISTOR
OR
OP27 & RESISTOR
R
SOURCE
R
SOURCE
O
E
INPUT NOISE VOLTAGE nV/ Hz
(
)
( )
( -- )
Input Noise Voltage vs. Source Resistance
FEATURES
ULTRALOW NOISE PERFORMANCE
2.9 nV/
Hz at 10 kHz
0.38 V p-p, 0.1 Hz to 10 Hz
6.9 fA/
Hz Current Noise at 1 kHz
EXCELLENT DC PERFORMANCE
0.5 mV max Offset Voltage
250 pA max Input Bias Current
1000 V/mV min Open-Loop Gain
AC PERFORMANCE
2.8 V/ s Slew Rate
4.5 MHz Unity-Gain Bandwidth
THD = 0.0003% @ 1 kHz
Available in Tape and Reel in Accordance with
EIA-481A Standard
APPLICATIONS
Sonar Preamplifiers
High Dynamic Range Filters (>140 dB)
Photodiode and IR Detector Amplifiers
Accelerometers
PRODUCT DESCRIPTION
The AD743 is an ultralow noise precision, FET input,
monolithic operational amplifier. It offers a combination of the
ultralow voltage noise generally associated with bipolar input op
amps and the very low input current of a FET-input device.
Furthermore, the AD743 does not exhibit an output phase
reversal when the negative common-mode voltage limit is
exceeded.
The AD743's guaranteed, maximum input voltage noise of
4.0 nV/
Hz
at 10 kHz is unsurpassed for a FET-input
monolithic op amp, as is the maximum 1.0
V p-p, 0.1 Hz to
10 Hz noise. The AD743 also has excellent dc performance with
250 pA maximum input bias current and 0.5 mV maximum
offset voltage.
The AD743 is specifically designed for use as a preamp in
capacitive sensors, such as ceramic hydrophones. It is available
in five performance grades. The AD743J and AD743K are rated
over the commercial temperature range of 0
C to +70
C. The
AD743A and AD743B are rated over the industrial temperature
range of 40
C to +85
C. The AD743S is rated over the
military temperature range of 55
C to +125
C and is available
processed to MIL-STD-883B, Rev. C.
The AD743 is available in 8-pin plastic mini-DIP, 8-pin cerdip,
16-pin SOIC, or in chip form.
AD743
8
TOP VIEW
1
2
3
7
6
8
5
4
OUT
NULL
NC
+V
S
NULL
IN
+IN
V
S
NC = NO CONNECT
OFFSET
NULL
AD743
IN
+IN
8
1
2
3
4
9
10
11
12
13
14
16
NC
NC
NC
OUTPUT
+V
S
V
S
NC
NC
15
8
7
6
5
NC
OFFSET
NULL
NC
NC
NC
NC = NO CONNECT
8-Pin Plastic Mini-DIP (N)
and
8-Pin Cerdip (Q) Packages
16-Pin SOIC (R) Package
REV. C
2
AD743SPECIFICATIONS
(@ +25 C and 15 V dc, unless otherwise noted)
AD743J
AD743K/B
AD743S
Model
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
INPUT OFFSET VOLTAGE
1
Initial Offset
0.25
1.0/0.8
0.1
0.5/0.25
0.25
1.0
mV
Initial Offset
T
MIN
to T
MAX
1.5
1.0/0.50
2.0
mV
vs. Temp.
T
MIN
to T
MAX
2
1
2
V/
C
vs. Supply (PSRR)
12 V to 18 V
2
90
96
100
106
90
96
dB
vs. Supply (PSRR)
T
MIN
to T
MAX
88
98
100
88
dB
INPUT BIAS CURRENT
3
Either Input
V
CM
= 0 V
150
400
150
250
150
400
pA
Either Input
@ T
MAX
V
CM
= 0 V
8.8/25.6
5.5/16
413
nA
Either Input
V
CM
= +10 V
250
600
250
400
300
600
pA
Either Input, V
S
=
5 V
V
CM
= 0 V
30
200
30
125
30
200
pA
INPUT OFFSET CURRENT
V
CM
= 0 V
40
150
30
75
40
150
pA
Offset Current
@ T
MAX
V
CM
= 0 V
2.2/6.4
1.1/3.2
102
nA
FREQUENCY RESPONSE
Gain BW, Small Signal
G = 1
4.5
4.5
4.5
MHz
Full Power Response
V
O
= 20 V p-p
25
25
25
kHz
Slew Rate, Unity Gain
G = 1
2.8
2.8
2.8
V/
s
Settling Time to 0.01%
6
6
6
s
Total Harmonic
f = 1 kHz
Distortion
4
(Figure 16)
G = 1
0.0003
0.0003
0.0003
%
INPUT IMPEDANCE
Differential
1 10
10
||
20
1 10
10
||
20
1 10
10
||
20
||
pF
Common Mode
3 10
11
||
18
3 10
11
||
18
3 10
11
||
18
||
pF
INPUT VOLTAGE RANGE
Differential
5
20
20
20
V
Common-Mode Voltage
+13.3, 10.7
+13.3, 10.7
+13.3, 10.7
V
Over Max Operating Range
6
10
+12
10
+12
10
+12
V
Common-Mode
Rejection Ratio
V
CM
=
10 V
80
95
90
102
80
95
dB
T
MIN
to T
MAX
78
88
78
dB
INPUT VOLTAGE NOISE
0.1 Hz to 10 Hz
0.38
0.38
1.0
0.38
V p-p
f = 10 Hz
5.5
5.5
10.0
5.5
nV/
Hz
f = 100 Hz
3.6
3.6
6.0
3.6
nV/
Hz
f = 1 kHz
3.2
5.0
3.2
5.0
3.2
5.0
nV/
Hz
f = 10 kHz
2.9
4.0
2.9
4.0
2.9
4.0
nV/
Hz
INPUT CURRENT NOISE
f = 1 kHz
6.9
6.9
6.9
fA/
Hz
OPEN LOOP GAIN
V
O
=
10 V
R
LOAD
2 k
1000
4000
2000
4000
1000
4000
V/mV
T
MIN
to T
MAX
800
1800
800
V/mV
R
LOAD
= 600
1200
1200
1200
V/mV
OUTPUT CHARACTERISTICS
Voltage
R
LOAD
600
+13, 12
+13, 12
+13, 12
V
R
LOAD
600
+13.6, 12.6
+13.6, 12.6
+13.6, 12.6
V
T
MIN
to T
MAX
+12, 10
+12, 10
+12, 10
V
R
LOAD
2 k
12
+13.8, 13.1
12
+13.8, 13.1
12
+13.8, 13.1
V
Current
Short Circuit
20
40
20
40
20
40
mA
POWER SUPPLY
Rated Performance
15
15
15
V
Operating Range
4.8
18
4.8
18
4.8
18
V
Quiescent Current
8.1
10.0
8.1
10.0
8.1
10.0
mA
TRANSISTOR COUNT
# of Transistors
50
50
50
NOTES
1
Input offset voltage specifications are guaranteed after 5 minutes of operation at T
A
= +25
C.
2
Test conditions: +V
S
= 15 V, V
S
= 12 V to 18 V and +V
S
= 12 V to +18 V, V
S
= 15 V.
3
Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T
A
= +25
C. For higher temperature, the current doubles every 10
C.
4
Gain = 1, R
L
= 2 k
, C
L
= 10 pF.
5
Defined as voltage between inputs, such that neither exceeds
10 V from common.
6
Thc AD743 does not exhibit an output phase reversal when the negative common-mode limit is exceeded.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
AD743
REV. C
3
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Internal Power Dissipation
2
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +V
S
and V
S
Storage Temperature Range (Q) . . . . . . . . . . 65
C to +150
C
Storage Temperature Range (N, R) . . . . . . . . 65
C to +125
C
Operating Temperature Range
AD743J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
C to +70
C
AD743A/B . . . . . . . . . . . . . . . . . . . . . . . . . . 40
C to +85
C
AD743S . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
C to +125
C
Lead Temperature Range (Soldering 60 seconds) . . . . . 300
C
NOTES
1
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
8-pin plastic package:
JA
= 100
C/Watt,
JC
= 50
C/Watt
8-pin cerdip package:
JA
= 110
C/Watt,
JC
= 30
C/Watt
16-pin plastic SOIC package:
JA
= 100
C/Watt,
JC
= 30
C/Watt
ESD SUSCEPTIBILITY
An ESD classification per method 3015.6 of MIL-STD-883C
has been performed on the AD743. The AD743 is a class 1
device, passing at 1000 V and failing at 1500 V on null pins 1
and 5, when tested, using an IMCS 5000 automated ESD
tester. Pins other than null pins fail at greater than 2500 V.
ORDERING GUIDE
Package
Model
Temperature Range
Option*
AD743JN
0
C to +70
C
N-8
AD743KN
0
C to +70
C
N-8
AD743JR-16
0
C to +70
C
R-16
AD743KR-16
0
C to +70
C
R-16
AD743BQ
40
C to +85
C
Q-8
AD743SQ/883B
55
C to +125
C
Q-8
AD743JR-16-REEL
0
C to +70
C
Tape & Reel
AD743KR-16-REEL
0
C to +70
C
Tape & Reel
*N = Plastic DIP; R = Small Outline IC; Q = Cerdip.
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
AD743
REV. C
4
Typical Characteristics
(@ +25 C, V
S
= +15 V)
0
5
10
15
20
20
5
10
15
0
OUTPUT VOLTAGE SWING Volts
R = 10k
POSITIVE
SUPPLY
NEGATIVE
SUPPLY
LOAD
SUPPLY VOLTAGE
VOLTS
Figure 2. Output Voltage Swing vs.
Supply Voltage
60 40
20
0
20
40
60
80
100
120
140
10
9
10
8
10
7
10
6
10
10
11
10
10
12
INPUT BIAS CURRENT Amps
TEMPERATURE
C
Figure 5. Input Bias Current vs.
Temperature
60
40
20
0
20
40
60
80
100 120
140
0
40
30
20
10
50
60
70
80
CURRENT LIMIT mA
+ OUTPUT
CURRENT
OUTPUT
CURRENT
TEMPERATURE
C
Figure 8. Short Circuit Current
Limit vs. Temperature
10
100
1k
10k
5
10
15
20
25
30
35
0
LOAD RESISTANCE
OUTPUT VOLTAGE SWING Volts p-p
Figure 3. Output Voltage Swing vs.
Load Resistance
0.01
0.1
1
10
100
10k
100k
1M
10M
100M
200
FREQUENCY Hz
OUTPUT IMPEDANCE
Figure 6. Output Impedance vs.
Frequency (Closed Loop Gain = 1)
60 40
20
0
20
40
60
80
100
120
140
3.0
4.0
5.0
6.0
7.0
2.0
TEMPERATURE
C
GAIN BANDWIDTH PRODUCT MHz
Figure 9. Gain Bandwidth Product
vs. Temperature
0
5
10
15
20
0
5
10
15
20
INPUT VOLTAGE SWING Volts
R = 10k
V
IN
+V
IN
LOAD
SUPPLY VOLTAGE
VOLTS
Figure 1. Input Voltage Swing
vs. Supply Voltage
0
5
10
15
20
6
12
9
3
0
QUIESCENT CURRENT mA
SUPPLY VOLTAGE
VOLTS
Figure 4. Quiescent Current vs.
Supply Voltage
0
12
12
COMMON MODE VOLTAGE Volts
INPUT BIAS CURRENT pA
9
6
3
3
6
9
300
200
100
0
Figure 7. Input Bias Current vs.
Common-Mode Voltage
AD743
REV. C
5
60 40
20
0
20
40
60
80 100 120 140
2.0
2.5
3.0
3.5
SLEW RATE Volts/
s
TEMPERATURE
C
Figure 11. Slew Rate vs.
Temperature (Gain = 1)
100
1k
10k
100k
1M
10M
100M
100
80
60
40
20
0
120
POWER SUPPLY REJECTION dB
FREQUENCY Hz
+ SUPPLY
SUPPLY
Figure 14. Power Supply Rejection
vs. Frequency
100
1k
10k
100k
1.0
10
100
10
1M
0.1
1
10M
FREQUENCY Hz
CLOSED-LOOP GAIN = 1
CLOSED-LOOP GAIN = 10
NOISE VOLTAGE (REFERRED TO INPUT) nV Hz
Figure 17. Input Noise Voltage
Spectral Density
0
5
10
15
20
80
120
130
140
150
100
OPEN-LOOP GAIN dB
SUPPLY VOLTAGE
VOLTS
Figure 12. Open-Loop Gain vs.
Supply Voltage, R
LOAD
= 2K
35
30
25
20
15
10
5
0
1M
1k
10k
100k
FREQUENCY Hz
OUTPUT VOLTAGE Volts p-p
R = 2k
L
Figure 15. Large Signal Frequency
Response
100
1k
10k
100k
1.0
10
100
10
1
1k
FREQUENCY Hz
CURRENT NOISE SPECTRAL DENSITY fA/ Hz
Figure 18. Input Noise Current
Spectral Density
100
1k
10k
100k
1M
10M
100M
100
80
60
40
20
0
20
100
60
0
20
40
80
20
FREQUENCY Hz
OPEN-LOOP GAIN dB
PHASE MARGIN Degrees
PHASE
GAIN
Figure 10. Open-Loop Gain and
Phase vs. Frequency
100
1k
10k
100k
1M
100
80
60
40
20
0
120
FREQUENCY Hz
COMMON-MODE REJECTION dB
V =
10V
CM
Figure 13. Common-Mode Rejec-
tion vs. Frequency
140
130
120
110
100
90
80
70
THD dB
100k
10
100
1k
10k
FREQUENCY Hz
GAIN = +10
GAIN = 1
Figure 16. Total Harmonic Distor-
tion vs. Frequency
AD743
REV. C
6
Typical Characteristics
(@ +25
C, V
S
= +15 V)
2.5
3
9
15
21
27
33
39
45
51
57
63
69
2.7
2.9
3.1
3.3
3.5
3.8
NUMBER OF UNITS
INPUT VOLTAGE NOISE nV Hz
Figure 19. Typical Noise Distribution
@ 10 kHz (602 Units)
Figure 20. Offset Null Configuration
Figure 21. Unity-Gain Follower
Figure 22a. Unity-Gain Follower
Large Signal Pulse Response
Figure 22b. Unity-Gain Follower
Small Signal Pulse Response
AD743
1
F
+V
S
0.1
F
4
V
IN
2k
3
2
6
2k
SQUARE WAVE
INPUT
V
OUT
100pF
C
L
7
100pF
V
S
0.1
F
1
F
Figure 23a. Unity-Gain Inverter
Figure 23b. Unity-Gain Inverter
Large Signal Pulse Response
Figure 23c. Unity-Gain Inverter
Small Signal Pulse Response
AD743
REV. C
7
OP AMP PERFORMANCE: JFET VS. BIPOLAR
The AD743 is the first monolithic JFET op amp to offer the low
input voltage noise of an industry-standard bipolar op amp
without its inherent input current errors. This is demonstrated
in Figure 24, which compares input voltage noise vs. input
source resistance of the OP27 and the AD743 op amps. From
this figure, it is clear that at high source impedance the low
current noise of the AD743 also provides lower total noise. It is
also important to note that with the AD743 this noise reduction
extends all the way down to low source impedances. The lower
dc current errors of the AD743 also reduce errors due to offset
and drift at high source impedances (Figure 25).
100
1k
10k
100k
1
10
100
1000
1M
10M
SOURCE RESISTANCE
OP27 &
RESISTOR
AD743 + RESISTOR
RESISTOR NOISE ONLY
AD743 & RESISTOR
OR
OP27 & RESISTOR
R
SOURCE
R
SOURCE
O
E
INPUT NOISE VOLTAGE nV/ Hz
(
)
( )
( -- )
Figure 24. Total Input Noise Spectral Density @ 1 kHz vs.
Source Resistance
INPUT OFFSET VOLTAGE mV
SOURCE RESISTANCE
ADOP27G
AD743 KN
100
10
1.0
0.1
100
1k
10k
100k
1M
10M
Figure 25. Input Offset Voltage vs. Source Resistance
DESIGNING CIRCUITS FOR LOW NOISE
An op amp's input voltage noise performance is typicaly divided
into two regions: flatband and low frequency noise. The AD743
offers excellent performance with respect to both. The figure of
2.9 nV/
Hz
@ 10 kHz is excellent for JFET input amplifier.
The 0.1 Hz to 10 Hz noise is typically 0.38
V p-p. The user
should pay careful attention to several design details in order to
optimize low frequency noise performance. Random air currents
can generate varying thermocouple voltages that appear as low
frequency noise: therefore sensitive circuitry should be well
shielded from air flow. Keeping absolute chip temperature low
also reduces low frequency noise in two ways: first, the low
frequency noise is strongly dependent on the ambient
temperature and increases above +25
C. Secondly, since the
gradient of temperature from the IC package to ambient is
greater, the noise generated by random air currents, as
previously mentioned, will be larger in magnitude. Chip
temperature can be reduced both by operation at reduced
supply voltages and by the use of a suitable clip-on heat sink, if
possible.
Low frequency current noise can be computed from the
magnitude of the dc bias current (
~
I
n
=
2qI
B
f ) and increases
below approximately 100 Hz with a 1/f power spectral density.
For the AD743 the typical value of current noise is 6.9 fA/
Hz
at 1 kHz. Using the formula,
~
I
n
=
4kT /R
f , to compute the
Johnson noise of a resistor, expressed as a current, one can see
that the current noise of the AD743 is equivalent to that of a
3.45 10
8
source resistance.
At high frequencies, the current noise of a FET increases
proportionately to frequency. This noise is due to the "real" part
of the gate input impedance, which decreases with frequency.
This noise component usually is not important, since the voltage
noise of the amplifier impressed upon its input capacitance is an
apparent current noise of approximately the same magnitude.
In any FET input amplifier, the current noise of the internal
bias circuitry can be coupled externally via the gate-to-source
capacitances and appears as input current noise. This noise is
totally correlated at the inputs, so source impedance matching
will tend to cancel out its effect. Both input resistance and input
capacitance should be balanced whenever dealing with source
capacitances of less than 300 pF in value.
LOW NOISE CHARGE AMPLIFIERS
As stated, the AD743 provides both low voltage and low current
noise. This combination makes this device particularly suitable
in applications requiring very high charge sensitivity, such as
capacitive accelerometers and hydrophones. When dealing with
a high source capacitance, it is useful to consider the total input
charge uncertainty as a measure of system noise.
Charge (Q) is related to voltage and current by the simply stated
fundamental relationships:
Q
=
CV and I
=
dQ
dt
As shown, voltage, current and charge noise can all be directly
related. The change in open circuit voltage (
V) on a capacitor
will equal the combination of the change in charge (
Q/C) and
the change in capacitance with a built in charge (Q/
C).
AD743
REV. C
8
Figures 26 and 27 show two ways to buffer and amplify the
output of a charge output transducer. Both require using an
amplifier which has a very high input impedance, such as the
AD743. Figure 26 shows a model of a charge amplifier circuit.
Here, amplification depends on the principle of conservation of
charge at the input of amplifier A1, which requires that the
charge on capacitor C
S
be transferred to capacitor C
F
, thus
yielding an output voltage of
Q/C
F
. The amplifiers input
voltage noise will appear at the output amplified by the noise
gain (1 + (C
S
/C
F
)) of the circuit.
Figure 26. A Charge Amplifier Circuit
Figure 27. Model for a High Z Follower with Gain
The second circuit, Figure 27, is simply a high impedance
follower with gain. Here the noise gain (1 + (R1/R2)) is the
same as the gain from the transducer to the output. Resistor R
B
,
in both circuits, is required as a dc bias current return.
There are three important sources of noise in these circuits.
Amplifiers A1 and A2 contribute both voltage and current noise,
while resistor R
B
contributes a current noise of:
~
N =
4k
T
R
B
f
where:
k = Boltzman's Constant = 1.381 x 10
23
Joules/Kelvin
T = Absolute Temperature, Kelvin (0
C = +273.2 Kelvin)
f = Bandwidth in Hz (Assuming an Ideal "Brick Wall"
Filter)
This must be root-sum-squared with the amplifier's own current
noise.
Figure 28 shows that these two circuits have an identical
frequency response and the same noise performance (provided
that C
S
/C
F
= R1/ R2). One feature of the first circuit is that a
"T" network is used to increase the effective resistance of R
B
and improve the low frequency cutoff point by the same factor.
100
110
120
130
140
150
160
170
180
190
200
210
220
10M
100M
1
10
100
1k
10k
100k
FREQUENCY Hz
TOTAL OUTPUT
NOISE
NOISE DUE TO
R ALONE
B
NOISE DUE TO
I ALONE
B
DECIBELS REFERENCED TO 1V/
Hz
Figure 28. Noise at the Outputs of the Circuits of Figures
26 and 27. Gain = 10, C
S
= 3000 pF, R
B
= 22 M
However, this does not change the noise contribution of R
B
which, in this example, dominates at low frequencies. The graph
of Figure 29 shows how to select an R
B
large enough to minimize
this resistor's contribution to overall circuit noise. When the
equivalent current noise of R
B
((
4kT
)/R) equals the noise of I
B
(
2qI
B
), there is diminishing return in making R
B
larger.
1pA
10pA
100pA
1nA
10nA
5.2 x 10
10
5.2 x 10
9
5.2 x 10
8
5.2 x 10
7
5.2 x 10
6
INPUT BIAS CURRENT
RESISTANCE IN
Figure 29. Graph of Resistance vs. Input Bias Current
where the Equivalent Noise
4kT/R, Equals the Noise
of the Bias Current
2qI
B
To maximize dc performance over temperature, the source
resistances should be balanced on each input of the amplifier.
This is represented by the optional resistor R
B
in Figures 26 and
27. As previously mentioned, for best noise performance care
should be taken to also balance the source capacitance designated
by C
B
. The value for C
B
in Figure 26 would be equal to C
S
, in
Figure 27. At values of C
B
over 300 pF, there is a diminishing
impact on noise; capacitor C
B
can then be simply a large bypass
of 0.01
F or greater.
AD743
HOW CHIP PACKAGE TYPE AND POWER DISSIPATION
AFFECT INPUT BIAS CURRENT
As with all JFET input amplifiers, the input bias current of the
AD743 is a direct function of device junction temperature, I
B
approximately doubling every 10C. Figure 30 shows the
relationship between bias current and junction temperature for
the AD743. This graph shows that lowering the junction
temperature will dramatically improve I
B
.
60 40
20
0
20
40
60
80 100 120
140
11
10
10
9
10
8
10
7
10
6
10
10
10
12
JUNCTION TEMPERATURE C
V = 15V
T = 25C
S
A
+
Figure 30. Input Bias Current vs. Junction Temperature
The dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 31 where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance (
in C/Watt).
= DEVICE DISSIPATION
= AMBIENT TEMPERATURE
= JUNCTION TEMPERATURE
= THERMAL RESISTANCE JUNCTION TO CASE
= THERMAL RESISTANCE CASE TO AMBIENT
P
IN
T
J
JC
CA
T
A
WHERE:
P
IN
CA
T
A
T
J
JC
JA
Figure 31. A Device Thermal Model
From this model T
J
= T
A
+
JA
Pin. Therefore, I
B
can be
determined in a particular application by using Figure 30
together with the published data for
JA
and power dissipation.
The user can modify
JA
by use of an appropriate clip-on heat
sink such as the Aavid #5801.
JA
is also a variable when using
the AD743 in chip form. Figure 32 shows bias current vs.
supply voltage with
JA
as the third variable. This graph can be
used to predict bias current after
JA
has been computed. Again
bias current will double for every 10C. The designer using the
AD743 in chip form (Figure 33) must also be concerned with
both
JC
and
CA
, since
JC
can be affected by the type of die
mount technology used.
Typically,
JC
's will be in the 3C to 5C/watt range; therefore,
for normal packages, this small power dissipation level may be
ignored. But, with a large hybrid substrate,
JC
will dominate
proportionately more of the total
JA
.
300
0
100
200
5 10 15
T = +25C
A
SUPPLY VOLTAGE Volts
= 165C/W
A
= 115C/W
A
= 0C/W
A
J
J
J
Figure 32. Input Bias Current vs. Supply Voltage for
Various Values of
JA
Figure 33. A Breakdown of Various Package Thermal
Resistances
REDUCED POWER SUPPLY OPERATION FOR
LOWER I
B
Reduced power supply operation lowers I
B
in two ways: first, by
lowering both the total power dissipation and second, by
reducing the basic gate-to-junction leakage (Figure 32). Figure
34 shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac coupling capacitor, over the 40C to
+85C temperature range. If the optional coupling capacitor is
used, this circuit will operate over the entire 55C to +125C
military temperature range.
Figure 34. A Piezoelectric Transducer
AD743
REV. C
10
AN INPUT-IMPEDANCE-COMPENSATED,
SALLEN-KEY FILTER
The simple high pass filter of Figure 35 has an important source
of error which is often overlooked. Even 5 pF of input capacitance
in amplifier "A" will contribute an additional 1% of passband
amplitude error, as well as distortion, proportional to the C/V
characteristics of the input junction capacitance. The addition
of the network designated "Z" will balance the source
impedanceas seen by "A"and thus eliminate these errors.
Figure 35. An Input Impedance Compensated
Sallen-Key Filter
TWO HIGH PERFORMANCE
ACCELEROMETER AMPLIFIERS
Two of the most popular charge-out transducers are hydrophones
and accelerometers. Precision accelerometers are typically
calibrated for a charge output (pC/g).* Figures 36a and 36b
show two ways in which to configure the AD743 as a low noise
charge amplifier for use with a wide variety of piezoelectric
accelerometers. The input sensitivity of these circuits will be
determined by the value of capacitor C1 and is equal to:
V
OUT
=
Q
OUT
C1
The ratio of capacitor C1 to the internal capacitance (C
T
) of the
transducer determines the noise gain of this circuit (1 + C
T
/C1).
The amplifiers voltage noise will appear at its output amplified
by this amount. The low frequency bandwidth of these circuits
will be dependent on the value of resistor R1. If a "T" network
is used, the effective value is: R1 (1 + R2/R3).
Figure 36a. A Basic Accelerometer Circuit
*pC = Picocoulombs
g = Earth's Gravitational Constant
Figure 36b. An Accelerometer Circuit Employing a
DC Servo Amplifier
A dc servo-loop (Figure 36b) can be used to assure a dc output
which is <10 mV, without the need for a large compensating
resistor when dealing with bias currents as large as 100 nA. For
optimal low frequency performance, the time constant of the
servo loop (R4C2 = R5C3) should be:
Time Constant
10 R1 1
+
R2
R3
C1
A LOW NOISE HYDROPHONE AMPLIFIER
Hydrophones are usually calibrated in the voltage-out mode.
The circuits of Figures 37a and 37b can be used to amplify the
output of a typical hydrophone. Figure 37a shows a typical dc
coupled circuit. The optional resistor and capacitor serve to
counteract the dc offset caused by bias currents flowing through
resistor R1. Figure 37b, a variation of the original circuit, has a
low frequency cutoff determined by an RC time constant equal
to:
Time Constant
=
1
2
C
C
100
Figure 37a. A Basic Hydrophone Amplifier
AD743
REV. C
11
Figure 37b. An AC-Coupled, Low Noise
Hydrophone Amplifier
Figure 37c. A Hydrophone Amplifier Incorporating a
DC Servo Loop
Where the dc gain is 1 and the gain above the low frequency
cutoff (1/(2
C
C
(100
))) is the same as the circuit of Figure
37a. The circuit of Figure 37c uses a dc servo loop to keep the
dc output at 0 V and to maintain full dynamic range for I
B
's up
to 100 nA. The time constant of R7 and C2 should be larger
than that of R1 and C
T
for a smooth low frequency response.
The transducer shown has a source capacitance of 7500 pF. For
smaller transducer capacitances (
300 pF), lowest noise can be
achieved by adding a parallel RC network (R4 = R1, C1 = C
T
)
in series with the inverting input of the AD743.
BALANCING SOURCE IMPEDANCES
As mentioned previously, it is good practice to balance the
source impedances (both resistive and reactive) as seen by the
inputs of the AD743. Balancing the resistive components will
optimize dc performance over temperature because balancing
will mitigate the effects of any bias current errors. Balancing
input capacitance will minimize ac response errors due to the
amplifier's input capacitance and, as shown in Figure 38, noise
performance will be optimized. Figure 39 shows the required
external components for noninverting (A) and inverting (B)
configurations.
Figure 38. RTI Voltage Noise vs. Input Capacitance
Figure 39. Optional External Components for Balancing Source Impedances
AD743
REV. C
12
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Plastic Mini-DIP (N)
8-Pin Cerdip (Q) Packages
16-Pin SOIC (R) Package
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