FUNCTIONAL BLOCK DIAGRAM
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
LC
2
MOS
(8+4) Loading Dual 12-Bit DAC
AD7537
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Two 12-Bit DACs in One Package
DAC Ladder Resistance Matching: 0.5%
Space Saving Skinny DIP and Surface Mount Packages
4-Quadrant Multiplication
Low Gain Error (1 LSB max Over Temperature)
Byte Loading Structure
Fast Interface Timing
APPLICATIONS
Automatic Test Equipment
Programmable Filters
Audio Applications
Synchro Applications
Process Control
GENERAL DESCRIPTION
The AD7537 contains two 12-bit current output DACs on one
monolithic chip. A separate reference input is provided for each
DAC. The dual DAC saves valuable board space, and the
monolithic construction ensures excellent thermal tracking.
Both DACs are guaranteed 12-bit monotonic over the full tem-
perature range.
The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure.
It is designed for right-justified data format. The control signals
for register loading are A0, A1, CS, WR and UPD. Data is
loaded to the input registers when CS and WR are low. To
transfer this data to the DAC registers, UPD must be taken low
with WR.
Added features on the AD7537 include an asynchronous CLR
line which is very useful in calibration routines. When this is
taken low, all registers are cleared. The double buffering of the
data inputs allows simultaneous update of both DACs. Also,
each DAC has a separate AGND line. This increases the device
versatility; for instance one DAC may be operated with
AGND biased while the other is connected in the standard
configuration.
The AD7537 is manufactured using the Linear Compatible
CMOS (LC
2
MOS) process. It is speed compatible with most
microprocessors and accepts TTL, 74HC and 5 V CMOS logic
level inputs.
PRODUCT HIGHLIGHTS
1. DAC to DAC Matching:
Since both DACs are fabricated on the same chip, precise
matching and tracking is inherent. Many applications which
are not practical using two discrete DACs are now possible.
Typical matching: 0.5%.
2. Small Package Size:
The AD7537 is packaged in small 24-pin 0.3" DIPs and in
28-terminal surface mount packages.
3. Wide Power Supply Tolerance:
The device operates on a +12 V to +15 V V
DD
, with
10%
tolerance on this nominal figure. All specifications are
guaranteed over this range.
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2
AD7537SPECIFICATIONS
(V
DD
= +12 V to +15 V, 10%, V
REFA
= V
REFB
= 10 V; I
OUTA
= AGND = 0 V,
I
OUTB
= AGNDB = 0 V. All specifications T
MIN
to T
MAX
unless otherwise noted.)
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for Design Guidance only and are not subject to test.
(V
DD
= +12 V to +15 V; V
REFA
= V
REFB
= +10 V; I
OUTA
= AGNDA = 0 V, I
OUTB
= AGNDB = 0 V. Output Amplifiers are AD644 except where noted.)
Parameter
T
A
= +25 C
T
A
= T
MIN
, T
MAX
Units
Test Conditions/Comments
Output Current Settling Time
1.5
s max
To 0.01% of full-scale range. I
OUT
load = 100
, C
EXT
= 13 pF.
DAC output measured from falling edge of WR.
Typical Value of Settling Time is 0.8
s.
Digital-to-Analog Glitch lmpulse
7
nV-s typ
Measured with V
REFA
= V
REFB
= 0 V. I
OUTA
, I
OUTB
load = 100
,
C
EXT
= 13 pF. DAC registers alternately loaded with all 0s and all 1s.
AC Feedthrough
4
V
REFA
to I
OUTA
70
65
dB max
V
REFA
, V
REFB
= 20 V p-p 10 kHz sine wave.
V
REFB
to I
OUTB
70
65
dB max
DAC registers loaded with all 0s.
Power Supply Rejection
Gain/
V
DD
0.01
0.02
% per % max
V
DD
= V
DD
max V
DD
min
Output Capacitance
C
OUTA
70
70
pF max
DAC A, DAC B loaded with all 0s
C
OUTB
70
70
pF max
C
OUTA
140
140
pF max
DAC A, DAC B loaded with all 1s
C
OUTB
140
140
pF max
Channel-to-Channel Isolation
V
REFA
to I
OUTB
84
dB typ
V
REFA
= 20 V p-p 10 kHz sine wave, V
REFB
= 0 V.
Both DACs loaded with all 1s.
V
REFB
to I
OUTA
84
dB typ
V
REFB
= 20 V p-p 10 kHz sine wave, V
REFA
= 0 V.
Both DACs loaded with all 1s.
Digital Crosstalk
7
nV-s typ
Measured for a Code Transition of all 0s to all 1s.
I
OUTA
, I
OUTB
load = 100
, C
EXT
= 13 pF.
Output Noise Voltage Density
25
nV/
Hz
typ
Measured between R
FBA
and I
OUTA
or R
FBB
and I
OUTB.
(10 Hz100 kHz)
Frequency of measurement is 10 Hz100 kHz.
Total Harmonic Distortion
82
dB typ
V
IN
= 6 V rms, 1 kHz. Both DACs loaded with all 1s.
NOTES
1
Temperature range as follows:
J, K, L Versions: 40
C to +85
C;
A, B, C Versions: 40
C to +85
C;
S, T, U Versions: 55
C to +125
C
Specifications subject to change without notice.
2
Sample tested at +25
C to ensure compliance.
3
Functional at V
DD
= 5 V, with degraded specifications.
4
Pin 12 (DGND) on ceramic DIPs is connected to lid.
J, A
K, B
L, C
S
T
U
Parameter
Versions
Versions
Versions
Version
Version
Version
Units
Test Conditions/Comments
ACCURACY
Resolution
12
12
12
12
12
12
Bits
Relative Accuracy
1
1/2
1/2
1
1/2
1/2
LSB max
Differential Nonlinearity
1
1
1
1
1
1
LSB max
All grades guaranteed mono-
tonic over temperature.
Gain Error
6
3
1
6
3
2
LSB max
Measured using R
FBA
, R
FBB
.
Both DAC registers loaded
with all 1s.
Gain Temperature Coefficient
2
;
Gain/
Temperature
5
5
5
5
5
5
ppm/
C max Typical value is 1 ppm/
C
Output Leakage Current
I
OUTA
+25
C
10
10
10
10
10
10
nA max
DAC A Register loaded
T
MIN
to T
MAX
150
150
150
250
250
250
nA max
with all 0s
I
OUTB
+25
C
10
10
10
10
10
10
nA max
DAC B Register loaded
T
MIN
to T
MAX
150
150
150
250
250
250
nA max
with all 0s
REFERENCE INPUT
Input Resistance
9
9
9
9
9
9
k
min
Typical Input Resistance = 14 k
20
20
20
20
20
20
k
max
V
REFA
, V
REFB
Input Resistance Match
3
3
1
3
3
1
% max
Typically
0.5%
DIGITAL INPUTS
V
IH
(lnput High Voltage)
2.4
2.4
2.4
2.4
2.4
2.4
V min
V
IIL
(Input Low Voltage)
0.8
0.8
0.8
0.8
0.8
0.8
V max
I
IN
(Input Current)
+25
C
1
1
1
1
1
1
A max
V
IN
= V
DD
T
MIN
to T
MAX
10
10
10
10
10
10
A max
C
IN
(lnput Capacitance)
2
10
10
10
10
10
10
pF max
POWER SUPPLY
3
V
DD
10.8/16.5
10.8/16.5
10.8/16.5
10.8/16.5
10.8/16.5
10.8/16.5
V min/V max
I
DD
2
2
2
2
2
2
mA max
AD7537
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3
TIMING CHARACTERISTICS
Limit at
Limit at
Limit at
T
A
= 40 C
T
A
= +55 C
Parameter
T
A
= +25 C
to +85 C
to +125 C
Units
Test Conditions/Comments
t
1
15
15
30
ns min
Address Valid to Write Setup Time
t
2
15
15
25
ns min
Address Valid to Write Hold Time
t
3
60
80
80
ns min
Data Setup Time
t
4
25
25
25
ns min
Data Hold Time
t
5
0
0
0
ns min
Chip Select or Update to Write Setup Time
t
6
0
0
0
ns min
Chip Select or Update to Write Hold Time
t
7
80
80
100
ns min
Write Pulse Width
t
8
80
80
100
ns min
Clear Pulse Width
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25
C unless otherwise stated)
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +17 V
V
REFA
, V
REFB
to AGNDA, AGNDB . . . . . . . . . . . . . . . .
25 V
V
RFBA
, V
RFBB
to AGNDA, AGNDB . . . . . . . . . . . . . . . .
25 V
Digital Input Voltage to DGND . . . . . . . 0.3 V, V
DD
+0.3 V
I
OUTA
, I
OUTB
to DGND . . . . . . . . . . . . . . 0.3 V, V
DD
+0.3 V
AGNDA, AGNDB to DGND . . . . . . . . . 0.3 V, V
DD
+0.3 V
Power Dissipation (Any Package)
To +75
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW
Derates Above +75
C . . . . . . . . . . . . . . . . . . . . . 6 mW/
C
Operating Temperature Range
Commercial Plastic (J, K, L Versions) . . . . 40
C to +85
C
Industrial Hermetic (A, B, C Versions) . . . 40
C to +85
C
Extended Hermetic (S, T, U Versions) . . 55
C to +125
C
Storage Temperature . . . . . . . . . . . . . . . . 65
C to +150
C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300
C
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7537 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Figure 1. Timing Diagram
ORDERING GUIDE
1
Temperature
Relative
Gain
Package
Model
2
Range
Accuracy Error
Option
3
AD7537JN
40
C to +85
C
1 LSB
6 LSB N-24
AD7537KN
40
C to +85
C
1/2 LSB
3 LSB N-24
AD7537LN
40
C to +85
C
1/2 LSB
1 LSB N-24
AD7537JP
40
C to +85
C
1 LSB
6 LSB P-28A
AD7537KP
40
C to +85
C
1/2 LSB
3 LSB P-28A
AD7537LP
40
C to +85
C
1/2 LSB
1 LSB P-28A
AD7537AQ
40
C to +85
C
1 LSB
6 LSB Q-24
AD7537BQ
40
C to +85
C
1/2 LSB
3 LSB Q-24
AD7537CQ
40
C to +85
C
1/2 LSB
1 LSB Q-24
AD7537SQ
55
C to +125
C
1 LSB
6 LSB Q-24
AD7537TQ
55
C to +125
C
1/2 LSB
3 LSB Q-24
AD7537UQ
55
C to +125
C
1/2 LSB
2 LSB Q-24
AD7537SE
55
C to +125
C
1 LSB
6 LSB E-28A
AD7537TE
55
C to +125
C
1/2 LSB
3 LSB E-28A
AD7537UE
55
C to +125
C
1/2 LSB
2 LSB E-28A
NOTES
1
Analog Devices reserves the right to ship ceramic packages (D-24A) in lieu of
cerdip packages (Q-24).
2
To order MIL-STD-883, Class B processed parts, add/883B to part number.
Contact your local sales office for military data sheet.
3
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip.
(V
DD
= +10.8 V to +16.5 V, V
REFA
= V
REFB
= +10 V; I
OUTA
= AGNDA = 0 V, I
OUTB
= AGNDB = 0 V.)
AD7537
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4
PIN FUNCTION DESCRIPTION (DIP)
PIN
MNEMONIC
DESCRIPTION
1
AGNDA
Analog Ground for DAC A.
2
I
OUTA
Current output terminal of DAC A.
3
R
FBA
Feedback resistor for DAC A.
4
V
REFA
Reference input to DAC A.
5
CS
Chip Select Input Active low.
614
DB0DB7
Eight data inputs, DB0DB7.
12
DGND
Digital Ground.
15
A0
Address Line 0.
16
A1
Address Line 1.
17
CLR
Clear Input. Active low. Clears all
registers.
18
WR
Write Input. Active low.
19
UPD
Updates DAC Registers from inputs
registers.
20
V
DD
Power supply input. Nominally +12 V
to +15 V, with
10% tolerance.
21
V
REFB
Reference input to DAC B.
22
R
FBB
Feedback resistor for DAC B.
23
I
OUTB
Current output terminal of DAC B.
24
AGNDB
Analog Ground for DAC B.
LCCC
DIP
PLCC
PIN CONFIGURATIONS
CIRCUIT INFORMATION D/A SECTION
The AD7537 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between I
OUTA
and AGNDA. The
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor R
FBA
is used with an op amp
(see Figures 4 and 5) to convert the current flowing in I
OUTA
to
a voltage output.
Figure 2. Simplified Circuit Diagram for DAC A
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the D/A con-
verters (DAC A) in the AD7537. A similar equivalent circuit
can be drawn for DAC B.
C
OUT
is the output capacitance due to the N-channel switches
and varies from about 50 pF to 150 pF with digital input code.
The current source I
LKG
is composed of surface and junction
leakages and approximately doubles every 10
C. R
0
is the
equivalent output resistance of the device which varies with
input code.
DIGITAL CIRCUIT INFORMATION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA.
Table I. AD7537 Truth Table
CLR UPD CS WR
A1 A0 FUNCTION
1
1
1
X
X
X
No Data Transfer
1
1
X
1
X
X
No Data Transfer
0
X
X
X
X
X
All Registers Cleared
1
1
0
0
0
0
DAC A LS Input Register
Loaded with DB7DB0 (LSB)
1
1
0
0
0
1
DAC A MS Input Register
Loaded with DB3 (MSB)DB0
1
1
0
0
1
0
DAC B LS Input Register
Loaded with DB7DB0 (LSB)
1
1
0
0
1
1
DAC B MS Input Register
Loaded with DB3 (MSB)DB0
1
0
1
0
X
X
DAC A, DAC B Registers
Updated Simultaneously from
Input Registers
1
0
0
0
X
X
DAC A, DAC B Registers are
Transparent
NOTES: X = Don't care
Figure 3. Equivalent Analog Circuit for DAC A
AD7537
REV. 0
5
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the circuit diagram for unipolar binary opera-
tion. With an ac input, the circuit performs 2-quadrant multipli-
cation. The code table for Figure 4 is given in Table II.
Operational amplifiers A1 and A2 can be in a single package
(AD644, AD712) or separate packages (AD544, AD711,
AD OP27). Capacitors C1 and C2 provide phase compensation
to help prevent overshoot and ringing when high-speed op amps
are used.
For zero offset adjustment, the appropriate DAC register is
loaded with all 0s and amplifier offset adjusted so that V
OUTA
or
V
OUTB
is 0 V. Full-scale trimming is accomplished by loading
the DAC register with all 1s and adjusting R1 (R3) so that
V
OUTA
(V
OUTB
) = V
IN
(4095/4096). For high temperature op-
eration, resistors and potentiometers should have a low Tem-
perature Coefficient. In many applications, because of the
excellent Gain T.C. and Gain Error specifications of the
AD7537, Gain Error trimming is not necessary. In fixed refer-
ence applications, full scale can also be adjusted by omitting R1,
R2, R3, R4 and trimming the reference voltage magnitude.
Figure 4. AD7537 Unipolar Binary Operation
Table II. Unipolar Binary Code Table for
Circuit of Figure 4
Binary Number in
DAC Register
Analog Output,
MSB
LSB
V
OUTA
or V
OUTB
1111 1111 1111
-
V
IN
4095
4096
1000 0000 0000
-
V
IN
2048
4096
= -
1
2
V
IN
0000 0000 0001
-
V
IN
1
4096
0000 0000 0000
0 V
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit diagram for bipolar operation is
shown in Figure 5. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust R1 (R3) so that V
OUTA
(V
OUTB
) = 0 V. Alternatively, R1,
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10)
varied for V
OUTA
(V
OUTB
) = 0 V. Full-scale trimming can be ac-
complished by adjusting the amplitude of V
IN
or by varying the
value of R5 (R8).
If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,
R9, R10) should be ratio matched to 0.01% to ensure gain error
performance to the data sheet specification. When operating
over a wide temperature range, it is important that the resistors
be of the same type so that their temperature coefficients match.
The code table for Figure 5 is given in Table III.
Figure 5. Bipolar Operation (Offset Binary Coding)
Table III. Bipolar Code Table for Offset Binary
Circuit of Figure 5
Binary Number in
DAC Register
Analog Output,
MSB LSB
V
OUTA
or V
OUTB
1111 1111 1111
+
V
IN
2047
2048
1000 0000 0001
+
V
IN
1
2048
1000 0000 0000
0 V
0111 1111 1111
-
V
IN
1
2048
0000 0000 0000
-
V
IN
2048
2048
= -
V
IN
Applications
AD7537
REV. 0
6
SEPARATE AGND PINS
The DACs in the AD7537 have separate AGND lines taken to
pins AGNDA and AGNDB on the package. This increases the
applications versatility of the part. Figure 6 is an example of
this. DAC A is connected in standard fashion as a program-
mable attenuator. AGNDA is at ground potential. DAC B is op-
erating with AGND B biased to +5 V by the AD584. This gives
an output range of +5 V to +10 V.
Figure 6. AD7537 DACs Used in Different Modes
PROGRAMMABLE OSCILLATOR
Figure 7 shows a conventional state variable oscillator in which
the AD7537 controls the programmable integrators. The fre-
quency of oscillation is given by:
f
=
1
2
R6
R5
1
C1
C2
R
EQ1
R
EQ2
where R
EQ1
and R
EQ2
are the equivalent resistances of the
DACs. The same digital code is loaded into both DACs.
If C1 = C2 and R5 = R6, the expression reduces to
f
=
1
2
1
C
1
R
EQ1
R
EQ2
Since
R
EQ
=
2
n
R
LAD
N
, (R
LAD
= DAC ladder resistance).
f
=
1
2
1
C
(N / 2
n
)
2
R
LAD1
R
LAD2
=
1
2
D
C
1
R
LAD1
R
LAD2
D
=
N
2
n
=
1
2
D
C
R
LAD m
where m is the DAC ladder resistance mismatch ratio, typically
1.005.
With the values shown in Figure 7, the output frequency varies
from 0 Hz to 1.38 kHz. The amplitude of the output signal at
the A3 output is 10 V peak-to-peak and is constant over the
entire frequency span.
Figure 7. Programmable State Variable Oscillator
AD7537
REV. 0
7
APPLICATION HINTS
Output Offset: CMOS D/A converters in circuits such as Fig-
ures 4 and 5 exhibit a code dependent output resistance which
in turn can cause a code dependent error voltage at the output
of the amplifier. The maximum amplitude of this error, which
adds to the D/A converter nonlinearity, depends on V
OS
, where
V
OS
is the amplifier input offset voltage. To maintain specified
operation, it is recommended that V
OS
be no greater than
(25 10
6
) (V
REF
) over the temperature range of operation.
Suitable op amps are the AD711C and its dual version, the
AD712C. These op amps have a wide bandwidth and high slew
rate and are recommended for wide bandwidth ac applications.
AD711/AD712 settling time to 0.01% is typically 3
s.
Temperature Coefficients: The gain temperature coefficient
of the AD7537 has a maximum value of 5 ppm/
C and typical
value of 1 ppm/
C. This corresponds to worst case gain shifts of
2 LSBs and 0.4 LSBs respectively over a 100
C temperature
range. When trim resistors R1 (R3) and R2 (R4) are used to ad-
just full scale range as in Figure 4, the temperature coefficient of
R1 (R3) and R2 (R4) should also be taken into account. For
further information see "Gain Error and Gain Temperature Co-
efficient of CMOS Multiplying DACs", Application Note, Pub-
lication Number E630c-5-3/86 available from Analog Devices.
High Frequency Considerations: AD7537 output capaci-
tance works in conjunction with the amplifier feedback resis-
tance to add a pole to the open loop response. This can cause
ringing or oscillation. Stability can be restored by adding a
phase compensation capacitor in parallel with the feedback re-
sistor. This is shown as C1 and C2 in Figures 4 and 5.
Feedthrough: The dynamic performance of the AD7537 de-
pends upon the gain and phase stability of the output amplifier,
together with the optimum choice of PC board layout and de-
coupling components. A suggested printed circuit layout for
Figure 4 is shown in Figure 8 which minimizes feedthrough
from V
REFA
, V
REFB
to the output in multiplying applications.
Figure 8. Suggested Layout for AD7537
MICROPROCESSOR INTERFACING
The byte loading structure of the AD7537 makes it very easy to
interface the device to any 8-bit microprocessor system. Figures
9 and 10 show two interfaces: one for the MC6809 and the
other for the MC68008. Figure 11 shows how an AD7537 sys-
tem can be easily expanded by tying all the UPD lines together
and using a single decoder output to control these. This ex-
panded system is shown using a Z80 microprocessor but it is
just as easily configured using any other 8-bit microprocessor
system. Note how the system shown in Figure 11 produces 4
analog outputs with a minimum amount of hardware.
Figure 9. AD7537MC6809 Interface
Figure 10. AD7537MC68008 Interface
Figure 11. Expanded AD7537 System
AD7537
REV. 0
8
C978a510/87
PRINTED IN U.S.A.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Plastic DIP (N-24)
24-Pin Cerdip (Q-24)
28-Terminal Leadless Ceramic Chip Carrier
(E-28A)
28-Terminal Plastic Leaded Chip Carrier
(P-28A)
24-Pin Ceramic DIP (D-24A)
PDF 
ZIP