REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD7541A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

World Wide Web Site: http://www.analog.com

Fax: 617/326-8703

© Analog Devices, Inc., 1997

CMOS

12-Bit Monolithic Multiplying DAC

FUNCTIONAL BLOCK DIAGRAM

10k

20k

S12

REF

OUT2

OUT1

FEEDBACK

BIT 12 (LSB)

BIT 3

BIT 2

BIT 1 (MSB)

DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)

LOGIC: A SWITCH IS CLOSED TO I

OUT1

FOR

ITS DIGITAL INPUT IN A "HIGH" STATE.

10k

FEATURES
Improved Version of AD7541
Full Four-Quadrant Multiplication
12-Bit Linearity (Endpoint)
All Parts Guaranteed Monotonic
TTL/CMOS Compatible
Low Cost
Protection Schottky Diodes Not Required
Low Logic Input Leakage

GENERAL DESCRIPTION

The Analog Devices AD7541A is a low cost, high performance
12-bit monolithic multiplying digital-to-analog converter. It is
fabricated using advanced, low noise, thin film on CMOS
technology and is available in a standard 18-lead DIP and in
20-terminal surface mount packages.

The AD7541A is functionally and pin compatible with the in-
dustry standard AD7541 device and offers improved specifica-
tions and performance. The improved design ensures that the
device is latch-up free so no output protection Schottky diodes
are required.

This new device uses laser wafer trimming to provide full 12-bit
endpoint linearity with several new high performance grades.

PRODUCT HIGHLIGHTS

Compatibility: The AD7541A can be used as a direct replace-
ment for any AD7541-type device. As with the Analog Devices
AD7541, the digital inputs are TTL/CMOS compatible and
have been designed to have a

A maximum input current

requirement so as not to load the driving circuitry.

Improvements: The AD7541A offers the following improved
specifications over the AD7541:

1. Gain Error for all grades has been reduced with premium

grade versions having a maximum gain error of

3 LSB.

2. Gain Error temperature coefficient has been reduced to

2 ppm/

C typical and 5 ppm/

C maximum.

3. Digital-to-analog charge injection energy for this new device

is typically 20% less than the standard AD7541 part.

4. Latch-up proof.

5. Improvements in laser wafer trimming provides 1/2 LSB max

differential nonlinearity for top grade devices over the operat-
ing temperature range (vs. 1 LSB on older 7541 types).

6. All grades are guaranteed monotonic to 12 bits over the

operating temperature range.

ORDERING GUIDE

Relative

Gain

Temperature

Accuracy

Error

Package

Model

Range

MIN

to T

MAX

= +25 C

Options

AD7541AJN

C to +70

1 LSB

6 LSB

N-18

AD7541AKN 0

C to +70

1/2 LSB

1 LSB

N-18

AD7541AJP

C to +70

1 LSB

P-20A

AD7541AKP

C to +70

1/2 LSB

P-20A

AD7541AKR

C to +70

1/2 LSB

R-18

AD7541AAQ

C to +85

1 LSB

6 LSB

Q-18

AD7541ABQ

C to +85

1/2 LSB

1 LSB

Q-18

AD7541ASQ

C to +125

1 LSB

6 LSB

Q-18

AD7541ATQ

C to +125

1/2 LSB

1 LSB

Q-18

AD7541ASE

C to +125

1 LSB

6 LSB

E-20A

AD7541ATE

C to +125

1/2 LSB

1 LSB

E-20A

NOTES

Analog Devices reserves the right to ship either ceramic (D-18) or cerdip (Q-18)

hermetic packages.

To order MIL-STD-883, Class B process parts, add /883B to part number. Contact

local sales office for military data sheet.

E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip

Carrier; Q = Cerdip; R = Small Outline IC.

REV. B

AD7541ASPECIFICATIONS

Parameter

Version

+25 C

MIN,

MAX

Units

Test Conditions/Comments

ACCURACY

Resolution

All

Bits

Relative Accuracy

J, A, S

LSB max

1 LSB =

0.024% of Full Scale

K, B, T

1/2

LSB max

1/2 LSB =

0.012% of Full Scale

Differential Nonlinearity

J, A, S

LSB max

All Grades Guaranteed Monotonic

K, B, T

1/2

LSB max

to 12 Bits, T

MIN

to T

MAX

Gain Error

J, A, S

LSB max

Measured Using Internal R

and Includes

K, B, T

LSB max

Effect of Leakage Current and Gain TC.
Gain Error Can Be Trimmed to Zero.

Gain Temperature Coefficient

Gain/ Temperature

All

ppm/

C max

Typical Value Is 2 ppm/

Output Leakage Current

OUT1 (Pin 1)

J, K

nA max

All Digital Inputs = 0 V.

A, B

nA max

S, T

200

nA max

OUT2 (Pin 2)

J, K

nA max

All Digital Inputs = V

A, B

nA max

S, T

200

nA max

REFERENCE INPUT

Input Resistance (Pin 17 to GND)

All

718

min/max

Typical Input Resistance = 11 k

Typical Input Resistance Temperature
Coefficient = 300 ppm/

DIGITAL INPUTS

(Input HIGH Voltage)

All

2.4

V min

(Input LOW Voltage)

All

0.8

V max

(Input Current)

All

A max

Logic Inputs Are MOS Gates. I

typ (25

C) = 1 nA.

(Input Capacitance)

All

pF max

= 0 V

POWER SUPPLY REJECTION

Gain/ V

All

0.01

0.02

% per % max

POWER SUPPLY

Range

All

+5 to +16

V min/V max

Accuracy Is Not Guaranteed Over This Range.

All

mA max

All Digital Inputs V

or V

100

500

A max

All Digital Inputs 0 V or V

AC PERFORMANCE CHARACTERISTICS

These Characteristics are included for Design Guidance only and are not subject to test. V

= +15 V, V

= +10 V except where noted,

OUT1 = 0UT2 = GND = 0 V, Output Amp is AD544 except where noted.

Parameter

Version

+25 C

MIN,

MAX

Units

Test Conditions/Comments

PROPAGATION DELAY (From Digital Input

OUT 1 Load = 100

, C

EXT

= 13 pF.

Change to 90% of Final Analog Output)

All

100

ns typ

Digital Inputs = 0 V to V

or V

to 0 V.

DIGITAL TO ANALOG GLITCH

REF

= 0 V. All digital inputs 0 V to V

IMPULSE

to 0 V.

All

1000

nV-sec typ

Measured using Model 50K as output amplifier.

MULTIPLYING FEEDTHROUGH ERROR

REF

to OUT1)

All

1.0

mV p-p typ

REF

10 V, 10 kHz sine wave.

OUTPUT CURRENT SETTLING TIME

All

0.6

s typ

To 0.01% of full-scale range.
OUT 1 Load = 100

, C

EXT

= 13 pF.

Digital Inputs = 0 V to V

or V

to 0 V.

OUTPUT CAPACITANCE

OUT1

(Pin 1)

All

200

pF max

Digital Inputs

OUT2

(Pin 2)

All

pF max

= V

OUT1

(Pin 1)

All

pF max

Digital Inputs

OUT2

(Pin 2)

All

200

pF max

= V

NOTES

Temperature range as follows: J, K versions, 0

C to +70

C; A, B versions, 25

C to +85

C; S, T versions, 55

C to +125

Guaranteed by design but not production tested.

To minimize feedthrough in the ceramic package (Suffix D) the user must ground the metal lid.

Specifications subject to change without notice.

= +15 V, V

REF

= +10 V; OUT 1 = OUT 2 = GND = 0 V unless otherwise noted)

AD7541A

REV. B

ABSOLUTE MAXIMUM RATINGS*

= +25

C unless otherwise noted)

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V

REF

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25 V

RFB

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25 V

Digital Input Voltage to GND . . . . . . . . 0.3 V, V

+ 0.3 V

OUT 1, OUT 2 to GND . . . . . . . . . . . . 0.3 V, V

+ 0.3 V

Power Dissipation (Any Package)

To +75

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW

Derates above +75

C . . . . . . . . . . . . . . . . . . . . . . 6 mW/

TERMINOLOGY

RELATIVE ACCURACY

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is expressed in % of full-
scale range or (sub)multiples of 1 LSB.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the difference between the measured
change and the ideal l LSB change between any two adjacent
codes. A specified differential nonlinearity of

1 LSB max over

the operating temperature range insures monotonicity.

GAIN ERROR

Gain error is a measure of the output error between an ideal
DAC and the actual device output. For the AD7541A, ideal
maximum output is

4095

4096

REF

Gain error is adjustable to zero using external trims as shown in
Figures 4, 5 and 6.

OUTPUT LEAKAGE CURRENT

Current which appears at OUTI with the DAC loaded to all 0s
or at OUT2 with the DAC loaded to all 1s.

MULTIPLYING FEEDTHROUGH ERROR

AC error due to capacitive feedthrough from V

REF

terminal to

OUT1 with DAC loaded to all 0s.

OUTPUT CURRENT SETTLING TIME

Time required for the output function of the DAC to settle to
within 1/2 LSB for a given digital input stimulus, i.e., 0 to full
scale.

PROPAGATION DELAY

This is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
the analog output at OUT1 reaches 90% of its final value.

DIGITAL-TO-ANALOG CHARGE INJECTION (QDA)

This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with V

REF

= GND and a Model 50K as the

output op amp, C1 (phase compensation) = 0 pF.

Operating Temperature Range

Commercial (J, K Versions) . . . . . . . . . . . . . 0

C to +70

Industrial (A, B Versions) . . . . . . . . . . . . . 25

C to +85

Extended (S, T Versions) . . . . . . . . . . . . . 55

C to +125

Storage Temperature . . . . . . . . . . . . . . . . . . 65

C to +150

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7541A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

DIP/SOIC LCCC PLCC

TOP VIEW

(Not to Scale)

AD7541A

OUT1

BIT 12 (LSB)

(+)

REF

FEEDBACK

OUT2

GND

BIT 1 (MSB)

BIT 9

BIT 10

BIT 11

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

20 19

OUT 2

OUT 1

REF

BIT 5

BIT 6

9 10 11 12 13

TOP VIEW

(Not to Scale)

AD7541A

GND

BIT 1 (MSB)

BIT 2

BIT 3

BIT 4

BIT 12 (LSB)

BIT 11

BIT 10

BIT 9

NC = NO CONNECT

BIT 7

BIT 8

20 19

11 12 13

TOP VIEW

(Not to Scale)

PIN 1
IDENTIFIER

GND

BIT 1 (MSB)

BIT 2

BIT 3

BIT 4

BIT 12 (LSB)

BIT 11

BIT 10

BIT 9

NC = NO CONNECT

OUT 2

OUT 1

REF

AD7541A

BIT 5

BIT 6

BIT 7

BIT 8

AD7541A

REV. B

GENERAL CIRCUIT INFORMATION
The simplified D/A circuit is shown in Figure 1. An inverted
R-2R ladder structure is used--that is, the binarily weighted
currents are switched between the OUT1 and OUT2 bus lines,
thus maintaining a constant current in each ladder leg indepen-
dent of the switch state.

10k

20k

S12

REF

OUT2

OUT1

FEEDBACK

BIT 12 (LSB)

BIT 3

BIT 2

BIT 1 (MSB)

DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)

LOGIC: A SWITCH IS CLOSED TO I

OUT1

FOR

ITS DIGITAL INPUT IN A "HIGH" STATE.

10k

Figure 1. Functional Diagram (Inputs HIGH)

The input resistance at V

REF

(Figure 1) is always equal to R

LDR

is the R/2R ladder characteristic resistance and is equal to

value "R"). Since R

at the V

REF

pin is constant, the reference

terminal can be driven by a reference voltage or a reference
current, ac or dc, of positive or negative polarity. (If a current
source is used, a low temperature coefficient external R

recommended to define scale factor.)

EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs LOW and all digital
inputs HIGH are shown in Figures 2 and 3. In Figure 2 with all
digital inputs LOW, the reference current is switched to OUT2.
The current source I

LEAKAGE

is composed of surface and junc-

tion leakages to the substrate, while the I/

4096

current source

represents a constant 1-bit current drain through the termina-
tion resistor on the R-2R ladder. The ON capacitance of the
output N-channel switch is 200 pF, as shown on the OUT2
terminal. The OFF switch capacitance is 70 pF, as shown on
the OUT1 terminal. Analysis of the circuit for all digital inputs
HIGH, as shown in Figure 3 is similar to Figure 2; however, the
ON switches are now on terminal OUT1, hence the 200 pF at
that terminal.

LEAKAGE

70pF

LEAKAGE

200pF

/4096

REF

R 15k

REF

RFB

OUT1

OUT2

Figure 2. DAC Equivalent Circuit All Digital Inputs LOW

LEAKAGE

70pF

LEAKAGE

200pF

/4096

REF

R 15k

REF

RFB

OUT2

OUT1

Figure 3. DAC Equivalent Circuit All Digital Inputs HIGH

APPLICATIONS

UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the analog circuit connections required for uni-
polar binary (2-quadrant multiplication) operation. With a dc
reference voltage or current (positive or negative polarity) ap-
plied at Pin 17, the circuit is a unipolar D/A converter. With an
ac reference voltage or current, the circuit provides 2-quadrant
multiplication (digitally controlled attenuation). The input/
output relationship is shown in Table II.

R1 provides full-scale trim capability [i.e., load the DAC register
to 1111 1111 1111, adjust R1 for V

OUT

= V

REF

(4095/4096)].

Alternatively, Full Scale can be adjusted by omitting R1 and R2
and trimming the reference voltage magnitude.

C1 phase compensation (10 pF to 25 pF) may be required for
stability when using high speed amplifiers. (C1 is used to cancel
the pole formed by the DAC internal feedback resistance and
output capacitance at OUT1).

Amplifier A1 should be selected or trimmed to provide V

10% of the voltage resolution at V

OUT

. Additionally, the ampli-

fier should exhibit a bias current which is low over the tempera-
ture range of interest (bias current causes output offset at V

OUT

equal to I

times the DAC feedback resistance, nominally 11 k

The AD544L is a high speed implanted FET input op amp with
low factory-trimmed V

AD7541A

REF

PINS 415

DGND

OUT1

OUT2

BIT 1 BIT 12

DIGITAL
GROUND

ANALOG
COMMON

C1
33pF

AD544L
(SEE TEXT)

OUT

REFER TO TABLE 1

Figure 4. Unipolar Binary Operation

Table I. Recommended Trim Resistor Values vs. Grades

Trim
Resistor

JN/AQ/SD

KN/BQ/TD

100

Table II. Unipolar Binary Code Table for Circuit of Figure 4

Binary Number in DAC
MSB

LSB

Analog Output, V

OUT

1 1 1 1

4095

4096

1 0 0 0

0 0 0 0

2048

4096

= 1/2 V

0 0 0 0

0 0 0 1

4096

0 0 0 0

0 Volts

AD7541A

REV. B

BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)

Figure 5 and Table III illustrate the circuitry and code relation-
ship for bipolar operation. With a dc reference (positive or nega-
tive polarity) the circuit provides offset binary operation. With
an ac reference the circuit provides full 4-quadrant multiplication.

With the DAC loaded to 1000 0000 0000, adjust R1 for
V

OUT

= 0 V (alternatively, one can omit R1 and R2 and adjust

the ratio of R3 to R4 for V

OUT

= 0 V). Full-scale trimming can

be accomplished by adjusting the amplitude of V

REF

or by vary-

ing the value of R5.

As in unipolar operation, A1 must be chosen for low V

and

low I

. R3, R4 and R5 must be selected for matching and track-

ing. Mismatch of 2R3 to R4 causes both offset and full-scale
error. Mismatch of R5 to R4 or 2R3 causes full-scale error. C1
phase compensation (10 pF to 50 pF) may be required for sta-
bility, depending on amplifier used.

AD7541A

REF

PINS 415

GND

OUT1

OUT2

BIT 1 BIT 12

DIGITAL

GROUND

ANALOG

COMMON

C1
33pF

AD544L

OUT

AD544J

R4
20k

20k

10k

10%

FOR VALUES OF R1 AND R2

SEE TABLE 1.

Figure 5. Bipolar Operation (4-Quadrant Multiplication)

Table III. Bipolar Code Table for Offset Binary Circuit of
Figure 5

Binary Number in DAC
MSB

LSB

Analog Output, V

OUT

1 1 1 1

2047

2048

1 0 0 0

0 0 0 0

0 0 0 1

2048

1 0 0 0

0 0 0 0

0 Volts

0 1 1 1

1 1 1 1

2048

0 0 0 0

2048

Figure 6 and Table IV show an alternative method of achieving
bipolar output. The circuit operates with sign plus magnitude
code and has the advantage of giving 12-bit resolution in each
quadrant, compared with 11-bit resolution per quadrant for the
circuit of Figure 5. The AD7592 is a fully protected CMOS
changeover switch with data latches. R4 and R5 should match
each other to 0.01% to maintain the accuracy of the D/A con-
verter. Mismatch between R4 and R5 introduces a gain error.

AD7541A

REF

PINS 415

GND

OUT1

OUT2

BIT 1 BIT 12

DIGITAL
GROUND

ANALOG
COMMON

C1
33pF

AD544L

OUT

AD544J

20k

FOR VALUES OF R1 AND R2

SEE TABLE 1.

20k

10k

10%

1/2 AD7592JN

SIGN BIT

Figure 6. 12-Bit Plus Sign Magnitude Operation

Table IV. 12-Bit Plus Sign Magnitude Code Table for Circuit
of Figure 6

Sign

Binary Number in DAC

Bit

MSB

LSB

Analog Output, V

OUT

1 1 1 1

4095

4096

0 0 0 0

0 Volts

0 0 0 0

0 Volts

1 1 1 1 1 1 1 1

1 1 1 1

4095

4096

Note: Sign bit of "0" connects R3 to GND.

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