REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD7545

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

World Wide Web Site: http://www.analog.com

Fax: 617/326-8703

© Analog Devices, Inc., 1997

CMOS 12-Bit

Buffered Multiplying DAC

FUNCTIONAL BLOCK DIAGRAM

AD7545

OUT 1

AGND

DGND

DB11DB0

(PINS 415)

12-BIT

MULTIPLYING DAC

INPUT DATA LATCHES

REF

FEATURES
12-Bit Resolution
Low Gain TC: 2 ppm/ C typ
Fast TTL Compatible Data Latches
Single +5 V to +15 V Supply
Small 20-Lead 0.3" DIP and 20-Terminal Surface Mount

Packages

Latch Free (Schottky Protection Diode Not Required)
Low Cost
Ideal for Battery Operated Equipment

PIN CONFIGURATIONS

DIP LCCC PLCC

GENERAL DESCRIPTION

The AD7545 is a monolithic 12-bit CMOS multiplying DAC
with onboard data latches. It is loaded by a single 12-bit wide
word and directly interfaces to most 12- and 16-bit bus systems.
Data is loaded into the input latches under the control of the CS
and WR inputs; tying these control inputs low makes the input
latches transparent, allowing direct unbuffered operation of the
DAC.

The AD7545 is particularly suitable for single supply operation
and applications with wide temperature variations.

The AD7545 can be used with any supply voltage from +5 V to
+15 V. With CMOS logic levels at the inputs the device dissi-
pates less than 0.5 mW for V

= +5 V.

20 19

DB6

DB5

DB4

DB3

DB2

11 12

DGND

TOP VIEW

(Not to Scale)

PIN 1
IDENTIFIER

AGND

DB11 (MSB)

DB10

DB9

REF

DB8

DB7

OUT 1

DB0 (LSB)

DB1

AD7545

TOP VIEW

(Not to Scale)

AD7545

OUT 1

REF

AGND

DGND

DB11 (MSB)

DB1

DB0 (MSB)

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

20 19

9 10 11 12 13

TOP VIEW

(Not to Scale)

AD7545

DB11 (MSB)

DB10

DB9

DB8

DB7

DB0 (LSB)

DB1

DB6

DB5

DB4

DB3

DB2

DGND

AGND

OUT 1

REF

REV. A

AD7545SPECIFICATIONS

= +5 V

= +15 V

Limits

Parameter

Version

= + 25 C T

MIN,

MAX

= + 25 C

MIN,

MAX

Units

Test Conditions/Comments

STATIC PERFORMANCE

Resolution

All

Bits

J, A, S

±2

LSB max

K, B, T

±1

LSB max

L, C, U

±1/2

LSB max

GL, GC, GU

±1/2

LSB max

Differential Nonlinearity

J, A, S

±4

LSB max

10-Bit Monotonic T

MIN

to T

MAX

K, B, T

±1

LSB max

12-Bit Monotonic T

MIN

to T

MAX

L, C, U

±1

LSB max

12-Bit Monotonic T

MIN

to T

MAX

GL, GC, GU

±1

LSB max

12-Bit Monotonic T

MIN

to T

MAX

Gain Error (Using Internal RFB)

J, A, S

±20

±25

LSB max

DAC Register Loaded with

K, B, T

±10

±15

LSB max

1111 1111 1111

L, C, U

±5

±6

±10

LSB max

Gain Error Is Adjustable Using

GL, GC, GU

±1

±2

±6

±7

LSB max

the Circuits of Figures 4, 5, and 6

Gain Temperature Coefficient

Gain/Temperature

All

±5

±10

ppm/

°C max

Typical Value is 2 ppm/

°C for V

= +5 V

DC Supply Rejection

Gain/V

All

0.015

0.03

0.01

0.02

% per % max

±5%

Output Leakage Current at OUT1

J, K, L, GL

nA max

DB0DB11 = 0 V; WR, CS = 0 V

A, B, C, GC

nA max

S, T, U, GU

200

nA max

DYNAMIC PERFORMANCE

Current Settling Time

All

µs max

To 1/2 LSB. OUT1 Load = 100

. DAC

Output Measured from Falling Edge of
WR, CS = 0.

Propagation Delay

(from Digital

Input Change to 90%
of Final Analog Output)

All

300

250

ns max

OUT1 Load = 100

, C

EXT

= 13 pF

Digital-to-Analog Glitch Inpulse

All

400

250

nV sec typ

REF

= AGND

AC Feedthrough

At OUT1

All

mV p-p typ

REF

±10 V, 10 kHz Sinewave

REFERENCE INPUT

Input Resistance

All

min

Input Resistance TC = 300 ppm/

°C typ

(Pin 19 to GND)

max

Typical Input Resistance = 11 k

ANALOG OUTPUT

Output Capacitance

OUT1

All

pF max

DB0DB11 = 0 V, WR, CS = 0 V

OUT1

200

pF max

DB0DB11 = V

, WR, CS = 0 V

DIGITAL INPUTS

Input High Voltage

All

2.4

13.5

V min

Input Low Voltage

All

0.8

1.5

V max

Input Current

All

±1

±10

±1

±10

µA max

= 0 or V

Input Capacitance

DB0DB11

All

pF max

= 0

WR, CS

All

pF max

= 0

SWITCHING CHARACTERISTICS

Chip Select to Write Setup Time

All

280

380

180

200

ns min

See Timing Diagram

200

270

120

150

ns typ

Chip Select to Write Hold Time

All

ns min

Write Pulse Width

All

250

400

160

240

ns min

, t

175

280

100

170

ns typ

Data Setup Time

All

140

210

120

ns min

100

150

ns typ

Data Hold Time

All

ns min

POWER SUPPLY

All

mA max

All Digital Inputs V

or V

100

500

100

500

µA max

All Digital Inputs 0 V to V

µA typ

All Digital Inputs 0 V to V

NOTES

Temperature range as follows: J, K, L, GL versions, 0

°C to +70°C; A, B, C, GC versions, 25°C to +85°C; S, T, U GU versions, 55°C to +125°C.

This includes the effect of 5 ppm max gain TC.

Guaranteed but not tested.

DB0DB11 = 0 V to V

or V

to 0 V.

Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND.

Logic inputs are MOS gates. Typical input current (+25

°C) is less than 1 nA.

Sample tested at +25

°C to ensure compliance.

Specifications subject to change without notice.

REF

= +10 V, V

OUT1

= O V, AGND = DGND unless otherwise noted)

AD7545

REV. A

ABSOLUTE MAXIMUM RATINGS*

= + 25

°C unless otherwise noted)

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3, +17 V

Digital Input Voltage to DGND . . . . . . . 0.3 V, V

+0.3 V

RFB

, V

REF

to DGND . . . . . . . . . . . . . . . . . . . . . . . . .

±25 V

PIN1

to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V, V

+0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . 0.3 V, V

+ 0.3 V

Power Dissipation (Any Package) to +75

°C . . . . . . . 450 mW

Derates above +75

°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

Operating Temperature

TERMINOLOGY

RELATIVE ACCURACY

The amount by which the D/A converter transfer function
differs from the ideal transfer function after the zero and full-
scale points have been adjusted. This is an endpoint linearity

measurement.

DIFFERENTIAL NONLINEARITY

The difference between the measured change and the ideal
change between any two adjacent codes. If a device has a differ-
ential nonlinearity of less than 1 LSB it will be monotonic, i.e.,
the output will always increase for an increase in digital code
applied to the D/A converter.

PROPAGATION DELAY

This is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which

the analog output at OUT1 reaches 90% of its final value.

DIGITAL-TO-ANALOG GLITCH IMPULSE

This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with V

REF

= AGND and an ADLH0032CG as

the output op amp, C1 (phase compensation) = 33 pF.

Commercial (J, K, L, GL) Grades . . . . . . . . 0

°C to +70°C

Industrial (A, B, C, GC) Grades . . . . . . . . 25

°C to +85°C

Extended (S, T, U, GU) Grades . . . . . . . 55

°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . 65

°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300

°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7545 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Maximum
Gain Error

Temperature

Relative

= +25 C

Package

Model

Range

Accuracy

= +5 V

Options

AD7545JN

°C to +70°C

± 2 LSB

±20 LSB

N-20

AD7545AQ

°C to +85°C

± 2 LSB

±20 LSB

Q-20

AD7545SQ

°C to +125°C ± 2 LSB

±20 LSB

Q-20

AD7545KN

°C to +70°C

± 1 LSB

±10 LSB

N-20

AD7545BQ

°C to +85°C

± 1 LSB

±10 LSB

Q-20

AD7545TQ

°C to +125°C ± 1 LSB

±10 LSB

Q-20

AD7545LN

°C to +70°C

± 1/2 LSB

±5 LSB

N-20

AD7545CQ

°C to +85°C

± 1/2 LSB

±5 LSB

Q-20

AD7545UQ

°C to +125°C ± 1/2 LSB

±5 LSB

Q-20

AD7545GLN

°C to +70°C

± 1/2 LSB

±1 LSB

N-20

AD7545GCQ

°C to +85°C

± 1/2 LSB

±1 LSB

Q-20

AD7545GUQ

°C to +125°C ± 1/2 LSB

±1 LSB

Q-20

AD7545JP

°C to +70°C

± 2 LSB

±20 LSB

P-20A

AD7545SE

°C to +125°C ± 2 LSB

±20 LSB

E-20A

AD7545KP

°C to +70°C

± 1 LSB

±10 LSB

P-20A

AD7545TE

°C to +125°C ± 1 LSB

±10 LSB

E-20A

AD7545LP

°C to +70°C

± 1/2 LSB

±5 LSB

P-20A

AD7545UE

°C to +125°C ± 1/2 LSB

±5 LSB

E-20A

AD7545GLP

°C to +70°C

± 1/2 LSB

±1 LSB

P-20A

AD7545GUE

°C to +125°C ± 1/2 LSB

±1 LSB

E-20A

NOTES

Analog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip

packages (Q-20).

To order MIL-STD-883, Class B process parts, add /883B to part number.

Contact local sales office for military data sheet. For U.S. Standard Military
DRAWING (SMD) see DESC drawing 5962-87702.

E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip

Carrier; Q = Cerdip.

Write Cycle Timing Diagram

CHIP

SELECT

WRITE

DATA IN

(DB0DB11)

DATA VALID

MODE SELECTION

CS AND WR LOW, DAC RESPONDS
TO DATA BUS (DB0DB11) INPUTS.

WRITE MODE:

HOLD MODE:

EITHER CS OR WR HIGH, DATA BUS
(DB0DB11) IS LOCKED OUT; DAC
HOLDS LAST DATA PRESENT WHEN
WR OR CS ASSUMED HIGH STATE.

NOTES:
V

= +5V; t

= t

= 20ns

= +15V; t

= t

= 40ns

ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO
90% OF V

TIMING MEASUREMENT REFERENCE LEVEL IS V

+ V

/2.

AD7545

REV. A

CIRCUIT INFORMATION--D/A CONVERTER SECTION

Figure 1 shows a simplified circuit of the D/A converter section
of the AD7545 and Figure 2 gives an approximate equivalent
circuit. Note that the ladder termination resistor is connected to
AGND. R is typically 11 k

REF

OUT 1

AGND

DB11

(MSB)

DB0

(LSB)

DB10

DB9

DB1

Figure 1. Simplified D/A Circuit of AD7545

The binary weighted currents are switched between the OUT1
bus line and AGND by N-channel switches, thus maintaining a
constant current in each ladder leg independent of the switch
state.

The capacitance at the OUT1 bus line, C

OUT1

, is code depen-

dent and varies from 70 pF (all switches to AGND) to 200 pF
(all switches to OUT1).

One of the current switches is shown in Figure 2. The input
resistance at V

REF

(Figure 1) is always equal to R

LDR

the R/2R ladder characteristic resistance and is equal to value
"R"). Since R

at the V

REF

pin is constant, the reference termi-

nal can be driven by a reference voltage or a reference current,
ac or dc, of positive or negative polarity. (If a current source is
used, a low temperature coefficient external R

is recommended

to define scale factor.)

TO LADDER

AGND

OUT 1

FROM

INTERFACE

LOGIC

Figure 2. N-Channel Current Steering Switch

CIRCUIT INFORMATION--DIGITAL SECTION

Figure 3 shows the digital structure for one bit.

The digital signals CONTROL and CONTROL are generated
from CS and WR.

INPUT BUFFERS

CONTROL

TO AGND SWITCH

TO OUT1 SWITCH

Figure 3. Digital Input Structure

The input buffers are simple CMOS inverters designed so that
when the AD7545 is operated with V

= 5 V, the buffers con-

vert TTL input levels (2.4 V and 0.8 V) into CMOS logic levels.
When V

is in the region of 2.0 volts to 3.5 volts, the input

buffers operate in their linear region and draw current from the

power supply. To minimize power supply currents it is recom-
mended that the digital input voltages be as close as practicably
possible to the supply rails (V

and DGND).

The AD7545 may be operated with any supply voltage in the
range 5

15 volts. With V

= +15 V the input logic

levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.

BASIC APPLICATIONS

Figures 4 and 5 show simple unipolar and bipolar circuits using
the AD7545. Resistor R1 is used to trim for full scale. The
"G" versions (AD7545GLN, AD7545GCQ, AD7545GUD)
have a guaranteed maximum gain error of

± 1 LSB at +25°C

= +5 V), and in many applications it should be possible to

dispense with gain trim resistors altogether. Capacitor C1 provides
phase compensation and helps prevent overshoot and ringing when
using high speed op amps. Note that all the circuits of Figures 4, 5
and 6 have constant input impedance at the V

REF

terminal.

The circuit of Figure 1 can either be used as a fixed reference
D/A converter so that it provides an analog output voltage in the
range 0 to V

(note the inversion introduced by the op amp),

or V

can be an ac signal in which case the circuit behaves as

an attenuator (2-Quadrant Multiplier). V

can be any voltage

in the range 20

+ 20 volts (provided the op amp can

handle such voltages) since V

REF

is permitted to exceed V

Table II shows the code relationship for the circuit of Figure 4.

DB11DB0

ANALOG

COMMON

C1
33pF

AD544L
(SEE TEXT)

OUT

REFER TO TABLE I

AD7545

REF

DGND

OUT1

AGND

Figure 4. Unipolar Binary Operation

Table I. Recommended Trim Resistor Values vs. Grades for
V

= +5 V

Trim
Resistor

J/A/S

K/B/T

L/C/U

GL/GC/GU

500

200

100

150

6.8

Table II. Unipolar Binary Code Table for Circuit of Figure 4

Binary Number in DAC Register

Analog Output

1 1 1 1

4095

4096

1 0 0 0

0 0 0 0

2048

4096

= 1/2 V

0 0 0 0

0 0 0 1

4096

0 0 0 0

0 Volts

AD7545

REV. A

Figure 5 and Table III illustrate the recommended circuit and
code relationship for bipolar operation. The D/A function itself
uses offset binary code and inverter U

on the MSB line con-

verts twos complement input code to offset binary code. If ap-
propriate; inversion of the MSB may be done in software using
an exclusive OR instruction and the inverter omitted. R3, R4
and R5 must be selected to match within 0.01% and they should
be the same type of resistor (preferably wire-wound or metal
foil), so their temperature coefficients match. Mismatch of R3
value to R4 causes both offset and full-scale error. Mismatch of
R5 and R4 and R3 causes full-scale error.

DATA INPUT

ANALOG

COMMON

C1
33pF

AD544L

OUT

AD544J

R4
20k

20k

10k

10%

FOR VALUES OF R1 AND R2

SEE TABLE I.

AD7545

REF

DB10DB0

OUT1

AGND

DB11

(SEE TEXT)

Figure 5. Bipolar Operation (Twos Complement Code)

Table III. Twos Complement Code Table for Circuit of
Figure 5

Data Input

Analog Output

0 1 1 1

1 1 1 1

2047

2048

0 0 0 0

0 0 0 1

2048

0 0 0 0

0 Volts

1 1 1 1

2048

1 0 0 0

0 0 0 0

2048

Figure 6 shows an alternative method of achieving bipolar out-
put. The circuit operates with sign plus magnitude code and has
the advantage of giving 12-bit resolution in each quadrant, com-
pared with 11-bit resolution per quadrant for the circuit of Fig-
ure 5. The AD7592 is a fully protected CMOS change-over
switch with data latches. R4 and R5 should match each other to
0.01% to maintain the accuracy of the D/A converter. Mismatch
between R4 and R5 introduces a gain error.

ANALOG
COMMON

C1
33pF

AD544L

OUT

AD544J

20k

FOR VALUES OF R1 AND R2

SEE TABLE I.

20k

10k

10%

1/2 AD7592JN

SIGN BIT

AD7545

REF

DB11DB0

OUT1

AGND

Figure 6. 12-Bit Plus Sign Magnitude D/A Converter

Table IV. 12-Plus Sign Magnitude Code Table for Circuit of
Figure 6

Sign

Binary Number in DAC

Bit

MSB

LSB

Analog Output, V

OUT

1 1 1 1

+ V

4095

4096

0 0 0 0

0 Volts

0 0 0 0

0 Volts

1 1 1 1

4095

4096

Note: Sign bit of "0" connects R3 to GND.

APPLICATIONS HINTS

Output Offset:

(CMOS D/A converters exhibit a code depen-

dent output resistance which, in turn, causes a code dependent
amplifier noise gain. The effect is a code dependent differential
nonlinearity term at the amplifier output that depends on V

where V

is the amplifier input offset voltage. To maintain

monotonic operation it is recommended that V

be no greater

than 25

× 10

) (V

REF

) over the temperature range of operation.

Suitable op amps are AD517L and AD544L. The AD517L is
best suited for fixed reference applications with low bandwidth
requirements: it has extremely low offset (50

µV) and in most

applications will not require an offset trim. The AD544L has a
much wider bandwidth and higher slew rate and is recommended
for multiplying and other applications requiring fast settling. An
offset trim on the AD544L may be necessary in some circuits.

General Ground Management:

AC or transient voltages

between AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages at
AGND and DGND are equal is to tie AGND and DGND
together at the AD7545. In more complex systems where the
AGND and DGND intertie is on the backplane, it is recom-
mended that two diodes be connected in inverse parallel
between the AD7545 AGND and DGND pins (IN914 or
equivalent).

Digital Glitches:

When WR and CS are both low the latches

are transparent and the D/A converter inputs follow the data
inputs. In some bus systems, data on the data bus is not always
valid for the whole period during which WR is low and as a
result invalid data can briefly occur at the D/A converter inputs
during a write cycle. Such invalid data can cause unwanted
glitches at the output of the D/A converter. The solution to this
problem, if it occurs, is to retime the write pulse WR so that it
only occurs when data is valid.

Another cause of digital glitches is capacitive coupling from the
digital lines to the OUT1 and AGND terminals. This should be
minimized by screening the analog pins of the AD7545 (Pins 1,
2, 19, 20) from the digital pins by a ground track run between
Pins 2 and 3 and between Pins 18 and 19 of the AD7545. Note
how the analog pins are at one end of the package and separated
from the digital pins by V

and DGND to aid screening at

the board level. On-chip capacitive coupling can also give rise
to crosstalk from the digital-to-analog sections of the AD7545,
particularly in circuits with high currents and fast rise and
fall times. This type of crosstalk is minimized by using

AD7545

REV. A

= +5 volts. However, great care should be taken to ensure

that the +5 V used to power the AD7545 is free from digitally
induced noise.

Temperature Coefficients:

The gain temperature coefficient

of the AD7545 has a maximum value of 5 ppm/

°C and a typical

value of 2 ppm/

°C. This corresponds to worst case gain shifts of

2 LSBs and 0.8 LSBs respectively over a 100

°C temperature

range. When trim resistors Rl and R2 are used to adjust full-
scale range, the temperature coefficient of R1 and R2 should
also be taken into account. The reader is referred to Analog
Devices Application Note "Gain Error and Gain Temperature
Coefficient of CMOS Multiplying DACs," Publication Number
E630106/81.

SINGLE SUPPLY OPERATION

The ladder termination resistor of the AD7545 (Figure 1) is
connected to AGND. This arrangement is particularly suitable
for single supply operation because OUT1 and AGND may be
biased at any voltage between DGND and V

. OUT1 and

AGND should never go more than 0.3 volts less than DGND or
an internal diode will be turned on and a heavy current may
flow which will damage the device. (The AD7545 is, however,
protected from the SCR latch-up phenomenon prevalent in
many CMOS devices.)

Figure 7 shows the AD7545 connected in a voltage switching
mode. OUT1 is connected to the reference voltage and AGND
is connected to DGND. The D/A converter output voltage is
available at the V

REF

pin and has a constant output impedance

equal to R. R

is not used in this circuit.

AD7545

DB11DB0

OUT1

AGND

+15V

REF

REFERENCE

VOLTAGE

DGND

15 VOLT CMOS DIGITAL INPUTS

Figure 7. Single Supply Operation Using Voltage
Switching Mode

The loading on the reference voltage source is code dependent
and the response time of the circuit is often determined by the
behavior of the reference voltage with changing load conditions.

To maintain linearity, the voltages at OUT1 and AGND should
remain within 2.5 volts of each other, for a V

of 15 volts. If

is reduced from 15 V, or the differential voltage between

OUT1 and AGND is increased to more than 2.5 V, the differ-
ential nonlinearity of the DAC will increase and the linearity of
the DAC will be degraded. Figures 8 and 9 show typical curves
illustrating this effect for various values of reference voltage and
V

. If the output voltage is required to be offset from ground

by some value, then OUT1 and AGND may be biased up. The
effect on linearity and differential nonlinearity will be the same
as reducing V

by the amount of the offset.

 Volts

DNL

LSB

Figure 8. Differential Nonlinearity vs. V

for Figure 7

Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows
Range of Values of Differential Nonlinearity that Typically
Occur for L, C and U Grades.

REF

 Volts

0.5

0.0

2.0

DNL

LSB

0.5

1.0

1.5

Figure 9. Differential Nonlinearity vs. Reference Voltage
for Figure 7 Circuit. V

= 15 Volts. Shaded Area Shows

Range of Values of Differential Nonlinearity that Typically
Occur for L, C and U Grades.

The circuits of Figures 4, 5 and 6 can all be converted to single
supply operation by biasing AGND to some voltage between
V

and DGND. Figure 10 shows the twos complement bipolar

circuit of Figure 5 modified to give a range from +2 V to +8 V
about a "pseudo-analog ground" of 5 V. This voltage range
would allow operation from a single V

of +10 V to +15 V.

The AD584 pin-programmable reference fixes AGND at +5 V.
V

is set at +2 V by means of the series resistors R1 and R2.

There is no need to buffer the V

REF

input to the AD7545

with an amplifier because the input impedance of the D/A con-
verter is constant. Note, however, that since the temperature
coefficient of the D/A reference input resistance is typically
300 ppm/

°C; applications that experience wide temperature

variations may require a buffer amplifier to generate the +2.0 V
at the AD7545 V

REF

pin. Other output voltage ranges can be

obtained by changing R4 to shift the zero point and (R1 + R2)
to change the slope, or gain, of the D/A transfer function. V

must be kept at least 5 V above OUT1 to ensure that linearity is
preserved.

AD7545

REV. A

10K

CMOS DATA BUS

= +10V TO +15V

C1
33pF

AD544L

AD544J

20k

10k

+2V

R2
2k

33.3k

DATA

AD7545

REF

DB10DB0

OUT1

AGND

MSB

DGND

AD584J

+5V

= +10V TO +15V

Figure 10. Single Supply "Bipolar" Twos Complement

D/A Converter

MICROPROCESSOR INTERFACING OF THE AD7545

The AD7545 can directly interface to both 8- and 16-bit micro-
processors via its 12-bit wide data latch using standard CS and
WR control signals.

A typical interface circuit for an 8-bit processor is shown in
Figure 11. This arrangement uses two memory addresses, one
for the lower eight bits of data to the DAC and one for the up-
per four bits of data into the DAC via the latch.

LATCH

AD7545

DB11

DB8

DB7

DB0

ADDRESS BUS

8-BIT DATA BUS

ADDRESS

DECODE

CPU

A15

= DECODED ADDRESS FOR DAC

= DECODED ADDRESS FOR LATCH

Figure 11. 8-Bit Processor to AD7545 Interface

Figure 12 shows an alternative approach for use with 8-bit
processors which have a full 16-bit wide address bus such as
6800, 8080, Z80 This technique uses the 12 lower address lines
of the processor address bus to supply data to the DAC, thus
each AD7545 connected in this way uses 4k bytes of address
locations. Data is written to the DAC using a single memory
write instruction. The address field of the instruction is orga-
nized so that the lower 12 bits contain the data for the DAC and
the upper 4 bits contain the address of the 4k block at which the
DAC resides.

AD7545

DB11

DB0

16-BIT ADDRESS BUS

DATA BUS

ADDRESS

DECODE

CPU

A15

Figure 12. Connecting the AD7545 to 8-Bit Processors via
the Address Bus

SUPPLEMENTAL APPLICATION MATERIAL

For further information on CMOS multiplying D/A converters
the reader is referred to the following texts:

Application Guide to CMOS Multiplying D/A converters
available from Analog Devices, Publication Number G479.

Gain Error and Gain Temperature Coefficient of CMOS
Multiplying DACS--Application Note, Publication Number
E630106/81 available from Analog Devices.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD7545SQ

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD7545SQ