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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
AD7654
*
Dual 2-Channel Simultaneous Sampling
SAR 500 kSPS 16-Bit ADC
*Patent pending
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
FEATURES
Dual 16-Bit 2-Channel Simultaneous Sampling ADC
16 Bits Resolution with No Missing Codes
Throughput:
500 kSPS (Normal Mode)
444 kSPS (Impulse Mode)
INL: 3.5 LSB Max ( 0.0053% of Full Scale)
SNR: 89 dB Typ @ 100 kHz
THD: 100 dB @ 100 kHz
Analog Input Voltage Range: 0 V to 5 V
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
SPITM/QSPITM/MICROWIRETM/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
120 mW Typical,
2.6 mW @ 10 kSPS
Package: 48-Lead Quad Flatpack (LQFP)
or 48-Lead Frame Chip Scale Package (LFCSP)
Low Cost
APPLICATIONS
AC Motor Control
3-Phase Power Control
4-Channel Data Acquisition
Uninterrupted Power Supplies
Communications
FUNCTIONAL BLOCK DIAGRAM
CLOCK AND
CONTROL LOGIC
A/
B
16
D[15:0]
BUSY
CS
SER/
PAR
OGND
OVDD
DGND
DVDD
SERIAL
PORT
PARALLEL
INTERFACE
BYTESWAP
RD
AVDD AGND
REFx
REFGND
PD
RESET
CNVST
INAN
SWITCHED
CAP DAC
AD7654
INA1
TRACK/HOLD
2
IMPULSE
MUX
MUX
EOC
MUX
INA2
A0
INB1
INBN
INB2
GENERAL DESCRIPTION
The AD7654 is a low cost, dual-channel, 16-bit, charge
redistribution SAR, analog-to-digital converter that operates
from a single 5 V power supply. It contains two low noise, wide
bandwidth track-and-hold amplifiers that allow simultaneous
sampling, a high speed 16-bit sampling ADC, an internal con-
version clock, error correction circuits, and both serial and parallel
system interface ports. Each track-and-hold has a multiplexer in
front to provide a 4-channel input ADC.
The part features a very high sampling rate mode (Normal) and,
for low power applications, a reduced power mode (Impulse)
where the power is scaled with the throughput. It is available in
48-lead LQFP or 48-lead LFCSP packages with operation
specified from 40
C to +85C.
PRODUCT HIGHLIGHTS
1. Simultaneous Sampling
The AD7654 features two sample-and-hold circuits that
allow simultaneous sampling. It provides 4-channel inputs.
2. Fast Throughput
The AD7654 is a very high speed (500 kSPS in Normal
Mode and 444 kSPS in Impulse Mode), charge redistribution,
16-bit SAR ADC that avoids pipeline delay.
3. Superior INL and No Missing Code
The AD7654 has a maximum integral nonlinearity of 3.5 LSB
with no missing codes at the 16-bit level.
4. Single-Supply Operation
The AD7654 operates from a single 5 V supply and dissipates
only 120 mW typical, even lower when a reduced throughput
is used with the reduced power mode (Impulse) and power-
down mode.
5. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V or 5 V logic.
PulSAR Selection
Type/kSPS
100250
500570
8001000
Pseudo
AD7651
AD7650/
AD7653
Differential
AD7660/
AD7652
AD7667
AD7661
AD7664/
AD7666
True Bipolar
AD7663
AD7665
AD7671
True Differential
AD7675
AD7676
AD7677
18 Bit
AD7678
AD7679
AD7674
Multichannel/
AD7654
Simultaneous
REV. 0
2
AD7654SPECIFICATIONS
(40 C to +85 C, V
REF
= 2.5 V, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless
otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
16
Bits
ANALOG INPUT
Voltage Range
V
INx
V
INxN
0
2 V
REF
Common-Mode Input Voltage
V
INxN
0.1
+0.5
V
Analog Input CMRR
f
IN
= 100 kHz
55
dB
Input Current
500 kSPS Throughput
45
A
Input Impedance
See Analog Input Section
THROUGHPUT SPEED
Complete Cycle
In Normal Mode
2
s
Throughput Rate
In Normal Mode
0
500
kSPS
Complete Cycle
In Impulse Mode
2.25
s
Throughput Rate
In Impulse Mode
0
444
kSPS
DC ACCURACY
Integral Linearity Error
3.5
+3.5
LSB
1
No Missing Codes
16
Bits
Transition Noise
0.7
LSB
Full-Scale Error
2
T
MIN
to T
MAX
0.25
0.5
% of FSR
Full-Scale Error Drift
2
2
ppm/
C
Unipolar Zero Error
2
T
MIN
to T
MAX
0.25
% of FSR
Unipolar Zero Error Drift
2
0.8
ppm/
C
Power Supply Sensitivity
AVDD = 5 V
5%
0.8
LSB
AC ACCURACY
Signal-to-Noise
f
IN
= 20 kHz
88
90
dB
3
f
IN
= 100 kHz
89
dB
Spurious Free Dynamic Range
f
IN
= 100 kHz
105
dB
Total Harmonic Distortion
f
IN
= 100 kHz
100
dB
Signal-to-(Noise+Distortion)
f
IN
= 20 kHz
87.5
90
dB
f
IN
= 100 kHz
88.5
dB
f
IN
= 100 kHz, 60 dB Input
30
dB
Channel-to-Channel Isolation
f
IN
= 100 kHz
92
dB
3 dB Input Bandwidth
10
MHz
SAMPLING DYNAMICS
Aperture Delay
4
2
ns
Aperture Delay Matching
4
30
ps
Aperture Jitter
4
5
ps rms
Transient Response
Full-Scale Step
250
ns
REFERENCE
External Reference Voltage Range
2.3
2.5
AVDD/2
V
External Reference Current Drain
500 kSPS Throughput
180
A
DIGITAL INPUTS
Logic Levels
V
IL
0.3
+0.8
V
V
IH
+2.0
OVDD + 0.3
V
I
IL
1
+1
A
I
IH
1
+1
A
DIGITAL OUTPUTS
Data Format
Parallel or Serial 16-Bit Straight Binary Coding
Pipeline Delay
Conversion Results Available Immediately
after Completed Conversion
V
OL
I
SINK
= 1.6 mA
0.4
V
V
OH
I
SOURCE
= 500
A
OVDD 0.2
V
REV. 0
AD7654
3
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES
Specified Performance
AVDD
4.75
5
5.25
V
DVDD
4.75
5
5.25
V
OVDD
2.25
5.255
V
Operating Current
6
500 kSPS Throughput
AVDD
15.5
mA
DVDD
8.5
mA
OVDD
100
A
Power Dissipation
500 kSPS Throughput
6
120
135
mW
10 kSPS Throughput
7
2.6
mW
444 kSPS Throughput
7
114
125
mW
TEMPERATURE RANGE
8
Specified Performance
T
MIN
to T
MAX
40
+85
C
NOTES
1
LSB means least significant bit. Within the 0 V to 5 V input range, one LSB is 76.294
V.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to as full-scale input FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified.
4
Sample tested during initial release.
5
The maximum should be the minimum of 5.25 V and DVDD + 0.3 V.
6
In Normal Mode.
7
In Impulse Mode.
8
Contact factory for extended temperature range.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 8 and 9
Convert Pulsewidth
t
1
5
ns
Time between Conversions
(Normal Mode/Impulse Mode)
t
2
2/2.25
s
CNVST LOW to BUSY HIGH Delay
t
3
32
ns
BUSY HIGH All Modes Except in Master Serial Read
after Convert Mode
(Normal Mode/Impulse Mode)
t
4
1.75/2
s
Aperture Delay
t
5
2
ns
End of Conversions to BUSY LOW Delay
t
6
10
ns
Conversion Time
(Normal Mode/Impulse Mode)
t
7
1.75/2
s
Acquisition Time
t
8
250
ns
RESET Pulsewidth
t
9
10
ns
CNVST LOW to EOC HIGH Delay
t
10
30
ns
EOC HIGH for Channel A Conversion
(Normal Mode/Impulse Mode)
t
11
1/1.25
s
EOC LOW after Channel A Conversion
t
12
45
ns
EOC HIGH for Channel B Conversion
t
13
0.75
s
Channel Selection Setup Time
t
14
250
ns
Channel Selection Hold Time
t
15
30
ns
Refer to Figures 1014 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t
16
1.75/2
s
DATA Valid to BUSY LOW Delay
t
17
14
ns
Bus Access Request to DATA Valid
t
18
40
ns
Bus Relinquish Time
t
19
5
15
ns
A/
B LOW to Data Valid Delay
t
20
40
ns
(40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
REV. 0
4
AD7654
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 15 and 16 (Master Serial Interface Modes)
CS LOW to SYNC Valid Delay
t
21
10
ns
CS LOW to Internal SCLK Valid Delay
t
22
10
ns
CS LOW to SDOUT Delay
t
23
10
ns
CNVST LOW to SYNC Delay (Read during Convert)
(Normal Mode/Impulse Mode)
t
24
250/500
ns
SYNC Asserted to SCLK First Edge Delay
*
t
25
3
ns
Internal SCLK Period
*
t
26
23
40
ns
Internal SCLK HIGH
*
t
27
12
ns
Internal SCLK LOW
*
t
28
7
ns
SDOUT Valid Setup Time
*
t
29
4
ns
SDOUT Valid Hold Time
*
t
30
2
ns
SCLK Last Edge to SYNC Delay
*
t
31
1
CS HIGH to SYNC HI-Z
t
32
10
ns
CS HIGH to Internal SCLK HI-Z
t
33
10
ns
CS HIGH to SDOUT HI-Z
t
34
10
ns
BUSY HIGH in Master Serial Read after Convert
(Normal Mode/Impulse Mode)
t
35
See Table I
CNVST LOW to SYNC Asserted Delay
(Normal Mode/Impulse Mode)
t
36
0.75/1
s
SYNC Deasserted to BUSY LOW Delay
t
37
25
ns
Refer to Figures 17 and 18 (Slave Serial Interface Modes)
External SCLK Setup Time
t
38
5
ns
External SCLK Active Edge to SDOUT Delay
t
39
3
18
ns
SDIN Setup Time
t
40
5
ns
SDIN Hold Time
t
41
5
ns
External SCLK Period
t
42
25
ns
External SCLK HIGH
t
43
10
ns
External SCLK LOW
t
44
10
ns
*In Serial Master Read during Convert Mode. See Table I for Serial Master Read after Convert Mode.
Specifications subject to change without notice.
Table I. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
0
1
0
1
Unit
SYNC to SCLK First Edge Delay Minimum
t
25
3
17
17
17
ns
Internal SCLK Period Minimum
t
26
25
50
100
200
ns
Internal SCLK Period Typical
t
26
40
70
140
280
ns
Internal SCLK HIGH Minimum
t
27
12
22
50
100
ns
Internal SCLK LOW Minimum
t
28
7
21
49
99
ns
SDOUT Valid Setup Time Minimum
t
29
4
18
18
18
ns
SDOUT Valid Hold Time Minimum
t
30
2
4
30
80
ns
SCLK Last Edge to SYNC Delay Minimum
t
31
1
3
30
80
ns
Busy High Width Maximum (Normal)
t
35
3.25
4.25
6.25
10.75
s
Busy High Width Maximum (Impulse)
t
35
3.5
4.5
6.5
11
s
TIMING SPECIFICATIONS
(continued)
REV. 0
AD7654
5
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7654 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
1
Analog Input
INAx
2
, INBx
2
, REFx, INxN, REFGND . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . AGND 0.3 V to AVDD + 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . .
0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . 0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . .
7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Digital Inputs . . . . . . . . . . . . . . . . . 0.3 V to DVDD + 0.3 V
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation
4
. . . . . . . . . . . . . . . . . . . . . . . 2.5 W
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD7654AST
40
C to +85C
Quad Flatpack (LQFP)
ST-48
AD7654ASTRL
40
C to +85C
Quad Flatpack (LQFP)
ST-48
AD7654ACP
40
C to +85C
Chip Scale Package (LFCSP)
CP-48
AD7654ACPRL
40
C to +85C
Chip Scale Package (LFCSP)
CP-48
EVAL-AD7654CB
1
Evaluation Board
EVAL-CONTROL BRD2
2
Controller Board
NOTES
1
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
2
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
TO OUTPUT
PIN
C
L
60pF*
500 A
I
OH
1.6mA
I
OL
1.4V
*IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, C
L
= 10 pF
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150
C
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
See Analog Input section.
3
Specification is for device in free air: 48-Lead LQFP:
JA
= 91
C/W,
JC
= 30
C/W.
4
Specification is for device in free air: 48-Lead LFCSP:
JA
= 26
C/W.
0.8V
2V
2V
0.8V
t
DELAY
2V
0.8V
t
DELAY
Figure 2. Voltage Reference Levels for Timing
REV. 0
6
AD7654
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type
Description
1, 47, 48
AGND
P
Analog Power Ground Pin
2
AVDD
P
Input Analog Power Pin. Nominally 5 V.
3
A0
DI
Multiplexer Select. When LOW, the analog inputs INA1 and INB1 are sampled simul-
taneously, then converted. When HIGH, the analog inputs INA2 and INB2 are sampled
simultaneously, then converted.
4
BYTESWAP
DI
Parallel Mode Selection (8 Bit, 16 Bit). When LOW, the LSB is output on D[7:0]
and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and
the MSB is output on D[7:0].
5
A/
B
DI
Data Channel Selection. In parallel mode, when LOW, the data from channel B is
read. When HIGH, the data from channel A is read. In serial mode, when HIGH,
channel A is output first followed by channel B. When LOW, channel B is output
first followed by channel B.
6, 20
DGND
P
Digital Power Ground
7
IMPULSE
DI
Mode Selection. When HIGH, this input selects a reduced power mode. In this mode,
the power dissipation is approximately proportional to the sampling rate.
8
SER/
PAR
DI
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DATA bus are used as a serial port.
9, 10
D[0:1]
DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
PAR is HIGH, these
outputs are in high impedance.
11, 12
D[2:3] or
DI/O
When SER/
PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port
Data Output Bus.
DIVSCLK[0:1]
When SER/
PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is the
serial master read after convert mode, these inputs, part of the serial port, are used to
slow down if desired the internal serial clock that clocks the data output. In the other
serial modes, these inputs are not used.
13
D[4]
DI/O
When SER/
PAR is LOW, this output is used as Bit 4 of the Parallel Port Data
Output Bus.
or EXT/INT
When SER/
PAR is HIGH, this input, part of the serial port, is used as a digital select
input for choosing the internal or an external data clock, called respectively, Master
and Slave Mode. With EXT/INT tied LOW, the internal clock is selected on SCLK
output. With EXT/INT set to a logic HIGH, output data is synchronized to an external
clock signal connected to the SCLK input.
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
DVDD
CNVST
PD
RESET
CS
RD
EOC
AGND
AVDD
A0
BYTESWAP
A/
B
DGND
IMPULSE
SER/
PAR
D0
D1
D2/DIVSCLK[0]
BUSY
D15
D14
D13
AD7654
D3/DIVSCLK[1]
D12
A
GND
A
GND
INA1
INAN
INA2
REF
A
REFB
INB2
INBN
INB1
REFGND
REF
D4/EXT/
INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OV
D
D
DV
D
D
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERR
OR
PIN CONFIGURATION
REV. 0
AD7654
7
14
D[5]
DI/O
When SER/
PAR is LOW, this output is used as Bit 5 of the Parallel Port Data
Output Bus.
or INVSYNC
When SER/
PAR is HIGH, this input, part of the serial port, is used to select the
active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
15
D[6]
DI/O
When SER/
PAR is LOW, this output is used as Bit 6 of the Parallel Port Data
Output Bus.
or INVSCLK
When SER/
PAR is HIGH, this input, part of the serial port, is used to invert the
SCLK signal. It is active in both Master and Slave modes.
16
D[7]
DI/O
When SER/
PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Out-
put Bus.
or RDC/SDIN
When SER/
PAR is HIGH, this input, part of the serial port, is used as either an exter-
nal data input or a read mode selection input, depending on the state of EXT/
INT.
When EXT/
INT is HIGH, RDC/SDIN can be used as a data input to daisy-chain the
conversion results from two or more ADCs onto a single SDOUT line. The digital
data level on SDIN is output on SDOUT with a delay of 32 SCLK periods after the
initiation of the read sequence.
When EXT/
INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN
is HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is
LOW, the data can be output on SDOUT only when the conversion is complete.
17
OGND
P
Input/Output Interface Digital Power Ground
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of
the host interface (5 V or 3 V).
19, 36
DVDD
P
Digital Power. Nominally at 5 V.
21
D[8]
DO
When SER/
PAR is LOW, this output is used as Bit 8 of the Parallel Port Data
Output Bus.
or SDOUT
When SER/
PAR is HIGH, this output, part of the serial port, is used as a serial data
output synchronized to SCLK. Conversion results are stored in a 32-bit on-chip regis-
ter. The AD7654 provides the two conversion results, MSB first, from its internal shift
register. The order of channel outputs is controlled by A/B. In serial mode, when
EXT/
INT is LOW, SDOUT is valid on both edges of SCLK.
In Serial Mode, when EXT/
INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the
next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on
the next rising edge.
22
D[9]
DI/O
When SER/
PAR is LOW, this output is used as Bit 9 of the Parallel Port Data
Output Bus.
or SCLK
When SER/
PAR is HIGH, this pin, part of the serial port, is used as a serial data clock
input or output, dependent upon the logic state of the EXT/
INT pin. The active edge
where the data SDOUT is updated depends on the logic state of the INVSCLK pin.
23
D[10]
DO
When SER/
PAR is LOW, this output is used as Bit 10 of the Parallel Port Data
Output Bus.
or SYNC
When SER/
PAR is HIGH, this output, part of the serial port, is used as a digital output
frame synchronization for use with the internal data clock (EXT/
INT = Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH
and frames SDOUT. After the first channel is output, SYNC is pulsed LOW. When
a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and
remains LOW while SDOUT output is valid. After the first channel is output, SYNC
is pulsed HIGH.
Pin No.
Mnemonic
Type
Description
REV. 0
8
AD7654
Pin No.
Mnemonic
Type
Description
24
D[11]
DO
When SER/
PAR is LOW, this output is used as Bit 11 of the Parallel Port Data
Output Bus.
or RDERROR
When SER/
PAR is HIGH and EXT/INT is HIGH, this output, part of the serial
port, is used as an incomplete read error flag. In Slave mode, when a data read is
started and not complete when the following conversion is complete, the current data
is lost and RDERROR is pulsed high.
2528
D[12:15]
DO
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/
PAR is HIGH,
these outputs are in high impedance.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started and remains HIGH
until the two conversions are complete and the data are latched into the on-chip shift
register. The falling edge of BUSY can be used as a data ready clock signal.
30
EOC
DO
End of Convert Output. Goes LOW at each channel conversion.
31
RD
DI
Read Data. When
CS and RD are both LOW, the interface parallel or serial output
bus is enabled.
32
CS
DI
Chip Select. When
CS and RD are both LOW, the interface parallel or serial output
bus is enabled.
CS is also used to gate the external serial clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7654. Current conversion if any
is aborted. If not used, this pin could be tied to DGND.
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and
conversions are inhibited after the current one is completed.
35
CNVST
DI
Start Conversion. A falling edge on
CNVST puts the internal sample-and-hold into the
hold state and initiates a conversion. In Impulse Mode (IMPULSE HIGH), if
CNVST is held low when the acquisition phase (t
8
) is complete, the internal sample-
and-hold is put into the hold state and a conversion is immediately started.
37
REF
AI
This input pin is used to provide a reference to the converter.
38
REFGND
AI
Reference Input Analog Ground
39, 41
INB1, INB2
AI
Analog Inputs
40, 45
INBN, INAN
AI
Analog Inputs Ground Senses. Allow to sense each channel ground independently.
42, 43
REFB, REFA
AI
These inputs are the references applied to channel A and channel B, respectively.
44, 46
INA2, INA1
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
PIN FUNCTION DESCRIPTIONS (continued)
REV. 0
AD7654
9
DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code from
a line drawn from negative full scale through positive full scale.
The point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Full-Scale Error
The last transition (from 111 . . . 10 to 111 . . . 11) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale (4.999886 V for the 0 V to 5 V range). The full-scale error
is the deviation of the actual level of the last transition from the
ideal level.
Unipolar Zero Error
In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. The unipolar zero error is the
deviation of the actual transition from that point.
Spurious-Free Dynamic Range (SFDR)
The difference, in decibels, between the rms amplitude of the
input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:
ENOB
S N
D
dB
=
+
[
]
-
)
(
)
1 76 6 02
.
.
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic com-
ponents to the rms value of a full-scale input signal and is
expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise+Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the
CNVST input to when
the input signals are held for a conversion.
Transient Response
The time required for the AD7654 to achieve its rated accuracy
after a full-scale step function is applied to its input.
REV. 0
10
AD7654Typical Performance Characteristics
CODE
1
INL LSB
5
3
65535
0
2
4
32768
16384
49152
0
1
2
3
4
5
TPC 1. Integral Nonlinearity vs. Code
CODE IN HEXA
7FBF
0
COUNTS
8000
6000
4000
2000
0
7000
3000
1000
5000
7FC0
0
7FC1
14
7FC2
953
7FC3
7288
7FC4
7220
7FC5
903
7FC6
6
7FC7
0
7FC8
0
TPC 2. Histogram of 16,384 Conversions of a DC
Input at the Code Transition
FREQUENCY kHz
1
AMPLITUDE dB of Full Scale
5
3
150
0
2
4
100
50
125
0
1
2
3
4
5
25
75
175
200
225
250
8192 POINT FFT
f
S
= 500kHz
f
IN
= 100kHz, 0.5dB
SNR = 89.9dB
S/[N+D] = 89.4dB
THD = 99.3dB
SFDR = 101.6dB
TPC 3. FFT Plot
CODE
DNL LSD
3
0
2
16384
32768
1
0
1
2
3
49152
65535
TPC 4. Differential Nonlinearity vs. Code
CODE IN HEXA
8000
7FC0
0
COUNTS
7000
4000
2000
0
6000
3000
1000
5000
7FC1 7FC2 7FC3
176
7FC4 7FC5
132
7FC6 7FC7
0
0
7FBF
0
9366
9000
10000
3411
3299
TPC 5. Histogram of 16,384 Conversions of a DC
Input at the Code Center
TEMPERATURE C
96
SNR dB
84
90
25
125
55
93
87
35
65
45
5
105
15
85
98
THD dB
106
102
100
104
SNR
THD
TPC 6. SNR, THD vs. Temperature
REV. 0
AD7654
11
FREQUENCY kHz
100
SNR AND S/[N+D] dB
90
70
80
10
1000
1
100
95
85
75
16.0
ENOB Bits
15.0
13.0
14.0
15.5
14.5
13.5
SNR
S/[N+D]
ENOB
TPC 7. SNR, S/(N+D), and ENOB vs. Frequency
TEMPERATURE C
LSB
10
15
55
25
35
5
45
8
6
4
2
0
2
4
6
8
10
65
85
105
125
FULL-SCALE ERROR
ZERO ERROR
TPC 10. Full-Scale and Zero Error vs. Temperature
SAMPLING RATE kSPS
1
10
OPERA
TING CURRENCY mA
100
1000
0.001
0.01
0.1
1
10
100
NORMAL AVDD
IMPULSE AVDD
NORMAL DVDD
IMPULSE DVDD
OVDD 2.7V
TPC 11. Operating Currents vs. Sample Rate
C
L
pF
50
SNR (REFERRED
T
O FULL SCALE dB
20
0
10
100
200
0
150
50
30
40
OVDD = 2.7V @85 C
OVDD = 2.7V @25 C
OVDD = 5V @85 C
OVDD = 5V @25 C
TPC 12. Typical Delay vs. Load Capacitance C
L
INPUT LEVEL dB
92
SNR (REFERRED
T
O FULL SCALE dB
90
86
88
40
20
60
30
50
10
0
SNR
S/[N+D]
FREQUENCY kHz
THD
,
HARMONICS,
CR
OSST
ALK dB
115
105
10
1000
1
100
110
90
SFDR dB
80
60
70
85
75
65
100
95
90
85
80
75
70
65
60
95
100
105
110
115
SFDR
CROSSTALK B TO A
CROSSTALK A TO B
THD
THIRD
HARMONIC
SECOND
HARMONIC
TPC 8. SNR and S/(N+D) vs. Input Level (Referred
to Full Scale)
TPC 9. THD, Harmonics, Crosstalk, and SFDR vs.
Frequency
REV. 0
12
AD7654
CIRCUIT INFORMATION
The AD7654 is a very fast, low power, single-supply, precise
simultaneous sampling 16-bit analog-to-digital converter (ADC).
The AD7654 provides the user with two on-chip track-and-hold,
successive approximation ADCs that do not exhibit any pipeline
or latency, making it ideal for multiple multiplexed channel
applications. The AD7654 can be also used as a 4-channel ADC
with two pairs simultaneously sampled.
The AD7654 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in
48-lead LQFP or tiny 48-lead LFCSP packages that combine
space savings and allow flexible configurations as either a serial
or parallel interface. The AD7654 is pin-to-pin-compatible with
PulSAR ADCs.
Modes of Operation
The AD7654 features two modes of operation, Normal and
Impulse. Each of these modes is more suitable for specific
applications.
The Normal Mode is the fastest mode (500 kSPS). Except when it
is powered down (PD HIGH), the power dissipation is almost
independent of the sampling rate.
The Impulse Mode, the lowest power dissipation mode, allows
power saving between conversions. The maximum throughput
in this mode is 444 kSPS. When operating at 10 kSPS, for
example, it typically consumes only 2.6 mW. This feature makes
the AD7654 ideal for battery-powered applications.
Transfer Functions
The AD7654 data format is straight binary. The ideal transfer
characteristic for the AD7654 is shown in Figure 3 and Table I.
000...000
000...001
000...010
111...101
111...110
111...111
ANALOG INPUT
+FS1.5 LSB
+FS1 LSB
FS+1 LSB
FS
FS+0.5 LSB
ADC CODE Straight Binar
y
Figure 3. ADC Ideal Transfer Function
Table I. Output Codes and Ideal Input Voltages
Analog
Digital Output
Description
Input V
REF
= 2.5 V
Code (Hexa)
FSR 1 LSB
4.999924 V
FFFF
1
FSR 2 LSB
4.999847 V
FFFE
Midscale + 1 LSB
2.500076 V
8001
Midscale
2.5 V
8000
Midscale 1 LSB
2.499924 V
7FFF
FSR + 1 LSB
76.29
V
0001
FSR
0 V
0000
2
NOTES
1
This is also the code for overrange analog input (V
INx
V
INxN
above 2
(V
REF
V
REFGND
)).
2
This is also the code for underrange analog input (V
INx
below V
INxN
).
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7654.
Different circuitry shown on this diagram is optional and is
discussed below.
Analog Inputs
Figure 4 shows a simplified analog input section of the AD7654.
INAx
INBx
AGND
AVDD
C
S
C
S
R
B
= 500
R
A
= 500
Figure 4. Simplified Analog Input
The diodes shown in Figure 4 provide ESD protection for the
inputs. Care must be taken to ensure that the analog input
signal never exceeds the absolute ratings on these inputs. This
will cause these diodes to become forward-biased and start
conducting current. These diodes can handle a forward-biased
current of 120 mA maximum. This condition could eventually
occur when the input buffer's (U1) or (U2) supplies are different
from AVDD. In such case, an input buffer with a short-circuit
current limitation can be used to protect the part.
This analog input structure allows the sampling of the differential
signal between INx and INxN. Unlike other converters, the
INxN is sampled at the same time as the INx input. By using
these differential inputs, small signals common to both inputs
are rejected.
REV. 0
AD7654
13
AVDD
AGND
DGND
DVDD
OVDD
OGND
SER/
PAR
CNVST
BUSY
SDOUT
SCLK
RD
CS
RESET
PD
REFGND
C
REF
2.5V REF
NOTE 1
REF A/
REF B/
REF
30
D
CLOCK
AD7654
C/ P/DSP
SERIAL PORT
DIGITAL SUPPLY
(3.3V OR 5V)
ANALOG
SUPPLY
(5V)
DVDD
A/
B
NOTE 7
BYTESWAP
DVDD
50k
100nF
1M
INAx
ANALOG INPUT A
C
C
2.7nF
U1
NOTE 4
NOTE 5
50
AD8021
+
15
NOTE 2
NOTE 3
NOTE 6
AD780
10 F
100nF
+
10 F
100nF
+
100nF
+
10 F
INBN
ANALOG INPUT B
C
C
2.7nF
U2
NOTE 4
NOTE 5
50
AD8021
+
15
50
+
1 F
NOTES
1. SEE VOLTAGE REFERENCE INPUT SECTION.
2. WITH THE RECOMMENDED VOLTAGE REFERENCES, C
REF
IS 47 F. SEE VOLTAGE REFERENCE INPUT SECTION.
3. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION.
4. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
5. SEE ANALOG INPUT SECTION.
6. OPTION, SEE POWER SUPPLY SECTION.
7. OPTIONAL LOW JITTER
CNVST. SEE CONVERSION CONTROL SECTION.
A0
INBx
INAN
Figure 5. Typical Connection Diagram (Serial Interface)
During the acquisition phase, for ac signals, the AD7654 behaves
like a one-pole RC filter consisted of the equivalent resistance
R
A
, R
B
, and C
S
. The resistors R
A
and R
B
are typically 500
and
are a lumped component made up of some serial resistor and the
on resistance of the switches. The capacitor C
S
is typically 32 pF
and is mainly the ADC sampling capacitor. This one-pole filter with
a typical 3 dB cutoff frequency of 10 MHz reduces undesirable
aliasing effect and limits the noise coming from the inputs.
Because the input impedance of the AD7654 is very high, the
AD7654 can be driven directly by a low impedance source
without gain error. As shown in Figure 5 that allows the user
to put an external one-pole RC filter between the output of
the amplifier output and the ADC analog inputs to even
further improve the noise filtering done by the AD7654 ana-
log input circuit. However, the source impedance has to be
kept low because it affects the ac performance, especially the
total harmonic distortion. The maximum source impedance
depends on the amount of total harmonic distortion (THD)
that can be tolerated. The THD degrades with increase of the
source impedance.
Driver Amplifier Choice
Although the AD7654 is easy to drive, the driver amplifier
needs to meet at least the following requirements:
The driver amplifier and the AD7654 analog input circuit
together have to be able to settle for a full-scale step of the
capacitor array at a 16-bit level (0.0015%). In the amplifier's
data sheet, the settling at 0.1% or 0.01% is more commonly
specified. It could significantly differ from the settling time
at a 16-bit level and, therefore, it should be verified prior to
the driver selection. The tiny op amp AD8021, which com-
bines ultralow noise and a high gain bandwidth, meets this
settling time requirement even when used with a high gain
of up to 13.
REV. 0
14
AD7654
The noise generated by the driver amplifier needs to be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7654. The noise coming from the
driver is filtered by the AD7654 analog input circuit one-pole
low-pass filter made by R
A
, R
B
, and C
S
. The SNR degrada-
tion due to the amplifier is:
SNR
f
N e
LOSS
dB
N
=
+
(
)
20
56
56
2
2
3
2
log
where:
f
3 dB
is the 3 dB input bandwidth in MHz of the AD7654
(10 MHz) or the cutoff frequency of the input filter if any is
used.
N is the noise factor of the amplifier (1 if in buffer configu-
ration).
e
N
is the equivalent input noise voltage of the op amp in
nV/
Hz
1/2
.
For instance, a driver with an equivalent input noise of
2 nV/
Hz like the AD8021 and configured as a buffer, thus
with a noise gain of +1, will degrade the SNR by only 0.03 dB
with the filter in Figure 5, and 0.09 dB without.
The driver needs to have a THD performance suitable to
that of the AD7654.
The AD8021 meets these requirements and is usually appropri-
ate for almost all applications. The AD8021 needs an external
compensation capacitor of 10 pF. This capacitor should have
good linearity as an NPO ceramic or mica type.
The AD8022 could be used where a dual version is needed and
a gain of 1 is used.
The AD829 is another alternative where high frequency (above
100 kHz) performance is not required. In a gain of 1, it requires
an 82 pF compensation capacitor.
The AD8610 is another option where low bias current is needed
in low frequency applications.
Voltage Reference Input
The AD7654 requires an external 2.5 V reference. The reference
input should be applied to REFA and REFB. The voltage refer-
ence input REF of the AD7654 has a dynamic input impedance;
it should therefore be driven by a low impedance source with an
efficient decoupling. This decoupling depends on the choice of
the voltage reference but usually consists of a 1
F ceramic
capacitor and a low ESR tantalum capacitor connected to the
REFA, REFB, and REFGND inputs with minimum parasitic
inductance. 47
F is an appropriate value for the tantalum
capacitor when using one of the recommended reference voltages:
The low noise, low temperature drift AD780 voltage
reference
The low cost AD1582 voltage reference
For applications using multiple AD7654s, it is more effective to
buffer the reference voltage using the internal buffer. Each ADC
should be decoupled individually.
Care should be taken with the reference temperature coefficient
of the voltage reference, which directly affects the full-scale
accuracy if this parameter is applicable. For instance, a
15 ppm/C tempco of the reference changes the full-scale
accuracy by
1 LSB/C.
Power Supply
The AD7654 uses three sets of power supply pins: an analog 5 V
supply AVDD, a digital 5 V core supply DVDD, and a digital
input/output interface supply OVDD. The OVDD supply
allows direct interface with any logic working between 2.7 V and
DVDD + 0.3 V. To reduce the number of supplies needed, the
digital core (DVDD) can be supplied through a simple RC filter
from the analog supply, as shown in Figure 5. The AD7654 is
independent of power supply sequencing, once OVDD does not
exceed DVDD by more than 0.3 V, and thus free from supply
voltage induced latchup. Additionally, it is very insensitive to
power supply variations over a wide frequency range, as shown
in Figure 6.
FREQUENCY kHz
40
1
10
PSRR dB
100
1000
10000
45
50
55
60
65
70
Figure 6. PSRR vs. Frequency
POWER DISSIPATION
In Impulse Mode, the AD7654 automatically reduces its power
consumption at the end of each conversion phase. During the
acquisition phase, the operating currents are very low, which
allows significant power savings when the conversion rate is
reduced, as shown in Figure 7. This feature makes the AD7654
ideal for very low power battery applications.
It should be noted that the digital interface remains active even
during the acquisition phase. To reduce the operating digital
supply currents even further, the digital inputs need to be driven
close to the power rails (i.e., DVDD and DGND), and OVDD
should not exceed DVDD by more than 0.3 V.
REV. 0
AD7654
15
SAMPLING RATE kSPS
0.1
1
10
PO
WER DISSIP
A
TION mW
100
1000
1
10
100
1000
NORMAL
IMPULSE
Figure 7. Power Dissipation vs. Sample Rate
CONVERSION CONTROL
Figure 8 shows the detailed timing diagrams of the conversion
process. The AD7654 is controlled by the signal
CNVST, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conver-
sion is complete. The
CNVST signal operates independently of
the
CS and RD signals. The A0 signal is the MUX select sig-
nal that chooses which input signal will be sampled. When
high, INx1 is chosen and when low, INx2 is chosen, where x is
either A or B. It should be noted that this signal should not be
changed during the acquisition phase of the converter.
CNVST
BUSY
MODE
t
2
t
1
t
3
t
4
t
5
t
6
t
7
t
8
ACQUIRE
CONVERT A
ACQUIRE
CONVERT
CONVERT B
EOC
t
12
A0
t
14
t
15
t
13
t
11
t
10
Figure 8. Conversion Control
In Impulse mode, conversions can be automatically initiated. If
CNVST is held low when BUSY is low, the AD7654 controls
the acquisition phase and automatically initiates a new con-
version. By keeping
CNVST low, the AD7654 keeps the
conversion process running by itself. It should be noted that the
analog input has to be settled when BUSY goes low. Also, at
power-up,
CNVST should be brought low once to initiate the
conversion process. In this mode, the AD7654 could sometimes
run slightly faster than the guaranteed limits in the Impulse
mode of 444 kSPS. This feature does not exist in Normal mode.
Although
CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels, and with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical, the
CNVST signal
should have very low jitter. Some solutions to achieve this are to
use a dedicated oscillator for
CNVST generation or, at least, to
clock it with a high frequency low jitter clock, as shown in Figure 5.
t
9
RESET
DATA BUS
BUSY
CNVST
t
8
Figure 9. Reset Timing
DIGITAL INTERFACE
The AD7654 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7654 digital interface accommodates either 3 V or 5 V logic
by simply connecting the OVDD supply pin of the AD7654 to the
host system interface digital supply.
Signals
CS and RD control the interface. When at least one of
these signals is high, the interface outputs are in high impedance.
Usually,
CS allows the selection of each AD7654 in multicircuit
applications and is held low in a single AD7654 design.
RD is
generally used to enable the conversion result on the data bus.
In parallel mode, signal A/
B allows the choice of reading either
the output of channel A or channel B, whereas in serial mode,
signal A/
B controls which channel is output first.
REV. 0
16
AD7654
t
1
t
3
t
4
t
17
CNVST
BUSY
DATA BUS
CS = RD = 0
t
16
NEW A
OR B
EOC
PREVIOUS CHANNEL A
OR B
PREVIOUS CHANNEL B
OR NEW A
t
10
Figure 10. Master Parallel Data Timing for Read-
ing (Continuous Read)
DATA BUS
t
18
t
19
BUSY
CS
RD
CURRENT
CONVERSION
Figure 11. Slave Parallel Data Timing for Reading
(Read after Convert)
PREVIOUS
CONVERSION
t
1
t
3
t
18
t
19
t
4
CS = 0
CNVST, RD
BUSY
DATA BUS
EOC
t
13
t
11
t
12
t
10
Figure 12. Slave Parallel Data Timing for Reading
(Read during Convert)
PARALLEL INTERFACE
The AD7654 is configured to use the parallel interface (Figure 10)
when the SER/
PAR is held low. The data can be read either
after each conversion, which is during the next acquisition phase
or during the other channel's conversion, or during the following
conversion as shown, respectively, in Figures 11 and 12. When the
data is read during the conversion, however, it is recommended
that it is read only during the first half of the conversion
phase. This avoids any potential feedthrough between voltage
transients on the digital interface and the most critical analog
conversion circuitry.
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in Figure 13, the LSB byte is output on D[7:0] and
the MSB is output on D[15:8] when BYTESWAP is low. When
BYTESWAP is high, the LSB and MSB bytes are swapped, the
LSB is output on D[15:8], and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
CS
RD
BYTE
PINS D[15:8]
PINS D[7:0]
HI-Z
HI-Z
HIGH BYTE
LOW BYTE
LOW BYTE
HIGH BYTE
HI-Z
HI-Z
t
18
t
18
t
19
Figure 13. 8-Bit Parallel Interface
CS
A/
B
RD
HI-Z
CHANNEL A
t
18
DATA BUS
t
20
CHANNEL B
HI-Z
Figure 14. A/
B Channel Reading
The detailed functionality of A/
B is explained in Figure 15.
When high, the data from channel A is available on the data bus.
When low, the data bus now carries output from channel B.
Note that channel A can be read immediately after conversion is
done (
EOC), while channel B is still in its converting phase.
SERIAL INTERFACE
The AD7654 is configured to use the serial interface when the
SER/PAR is held high. The AD7654 outputs 32 bits of data,
MSB first, on the SDOUT pin. The order of the channels being
output is controlled by A/B. When high, channel A is output
first; when low, channel B is output first. Unlike in parallel
REV. 0
AD7654
17
mode, channel A data is updated only after channel B conver-
sion. This data is synchronized with the 32 clock pulses provided
on the SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7654 is configured to generate and provide the serial
data clock SCLK when the EXT/
INT pin is held low. The
AD7654 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. The output data is valid
on both the rising and falling edge of the data clock. Depending
on RDC/SDIN input, the data can be read after each conver-
sion or during the following conversion.
Figures 15 and 16 show the detailed timing diagrams of these
two modes.
Usually, because the AD7654 is used with a fast throughput,
the mode Master Read during Conversion is the most recom-
mended serial mode when it can be used.
In Read-after-Conversion Mode, it should be noted that unlike
in other modes, the signal BUSY returns low after the 32 data
bits are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width. One advantage of this
mode is that it can accommodate slow digital hosts because the
serial clock can be slowed down by using DIVSCLK.
In Read-during-Conversion Mode, the serial clock and data toggle
at appropriate instants, which minimizes potential feedthrough
between digital activity and the critical conversion decisions.
The SYNC signal goes low after the LSB of each channel has
been output.
SLAVE SERIAL INTERFACE
External Clock
The AD7654 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/
INT pin is held
high. In this mode, several methods can be used to read the
data. The external serial clock is gated by
CS and the data are
output when both
CS and RD are low. Thus, depending on CS,
the data can be read after each conversion or during the follow-
ing conversion. The external clock can be either a continuous or
discontinuous clock. A discontinuous clock can be either normally
high or normally low when inactive. Figures 17 and 18 show the
detailed timing diagrams of these methods.
While the AD7654 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is par-
ticularly important during the second half of the conversion
phase of each channel because the AD7654 provides error cor-
rection circuitry that can correct for an improper bit decision
made during the first half of the conversion phase. For this
reason, it is recommended that when an external clock is pro-
vided, it is a discontinuous clock that is toggling only when
BUSY is low or, more importantly, that it does not transition
during the latter half of EOC high.
t
3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
1
2
16
30
31
32
CH A
D15
CH A
D14
CH B
D2
CH B
D1
CH B D0
X
EXT/
INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t
21
t
27
t
22
t
23
t
29
t
30
t
36
t
25
t
28
t
37
t
32
t
31
t
33
t
34
A/
B = 1
EOC
t
12
t
13
17
t
35
t
26
Figure 15. Master Serial Data Timing for Reading (Read after Convert)
REV. 0
18
AD7654
EXT/
INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t
3
t
1
t
24
t
21
t
26
t
27
t
28
t
31
t
33
t
32
t
34
t
30
t
29
t
23
t
22
CH A
D15
X
1
2
16
1
2
t
25
BUSY
SYNC
SCLK
SDOUT
CS, RD
CNVST
16
CH B
D15
CH A D0
CH A
D14
CH B
D14
CH B D0
A/
B = 1
EOC
t
10
t
11
t
13
t
12
Figure 16. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
CS
SCLK
SDOUT
CH A
D15
BUSY
SDIN
INVSCLK = 0
t
42
t
43
t
44
t
38
t
39
t
23
t
40
t
41
X
1
2
3
30
31
32
33
34
EXT/
INT = 1
CH B D0
CH B D1
CH A
D13
CH A
D14
X CH A
D14
X CH A
D15
X CH A
D13
X CH A
D14
X CH A
D15
X CH B
D0
X CH B
D1
Y CH A
D14
Y CH A
D15
RD = 0
A/
B = 1
EOC
Figure 17. Slave Serial Data Timing for Reading (Read after Convert)
REV. 0
AD7654
19
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 18 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the results of this conversion can be read while both
CS
and
RD are low. The data from both channels are shifted out,
MSB first, with 32 clock pulses, and is valid on both rising and
falling edge of the clock.
One advantage of this method is that the conversion perfor-
mance is not degraded because there are no voltage transients on
the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz, which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7654 provides a daisy-chain
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing component
count and wiring connections when it is desired, as it is for
instance, in isolated multiconverters applications.
An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a common
CNVST signal. It should be noted that the RDC/SDIN input is
latched on the edge of SCLK opposite the one used to shift out
the data on SDOUT. Therefore, the MSB of the upstream
converter follows the LSB of the downstream converter on the
next SCLK cycle.
External Clock Data Read during Conversion
Figure 18 shows the detailed timing diagrams of this method.
During a conversion, while both
CS and RD are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 32 clock pulses, and is valid on both rising and
falling edges of the clock. The 32 bits have to be read before the
current conversion is complete. If that is not done, RDERROR
is pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain fea-
ture in this mode, and RDC/SDIN input should always be tied
either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been initiated.
CNVST
SDOUT
SCLK
X
CH A D15
1
2
3
31
32
t
3
t
42
t
43
t
44
t
38
t
39
t
23
BUSY
INVSCLK = 0
CS
EXT/
INT = 1
CH B D0
CH B D1
CH A D13
CH A D14
RD = 0
EOC
t
10
t
11
t
13
t
12
A/
B = 1
Figure 18. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
REV. 0
20
AD7654
BUSY
BUSY
AD7654
#2 (UPSTREAM)
AD7654
#1 (DOWNSTREAM)
RDC/SDIN
SDOUT
CNVST
CS
SCLK
RDC/SDIN
SDOUT
CNVST
CS
SCLK
DATA
OUT
SCLK IN
CS IN
CNVST IN
BUSY
OUT
Figure 19. Two AD7654s in a Daisy-Chain Configuration
MICROPROCESSOR INTERFACING
The AD7654 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7654 is designed to interface with either a parallel 8-bit
or 16-bit wide interface, a general-purpose serial port, or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7654 to prevent digital noise from coupling into
the ADC. The following section illustrates the use of the AD7654
with an SPI-equipped DSP, the ADSP-219x.
SPI Interface (ADSP-219x)
Figure 19 shows an interface diagram between the AD7654 and
an SPI-equipped DSP, ADSP-219x. To accommodate the slower
speed of the DSP, the AD7654 acts as a slave device and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command can be initiated in response
to an internal timer interrupt. The 32-bit output data are read
with two SPI 16-bit wide access. The reading process could
be initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The Serial Peripheral
Interface (SPI) on the ADSP-219x is configured for master mode
(MSTR) = 1, Clock Polarity Bit (CPOL) = 0, and Clock Phase Bit
(CPHA) = 1 by writing to the SPI Control Register (SPICLTx).
AD7654*
ADSP-219x*
SER/
PAR
PFx
MISOx
SCKx
PFx or TFSx
BUSY
SDOUT
SCLK
CNVST
EXT/
INT
CS
RD
INVSCLK
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
SPIxSEL (PFx)
Figure 20. Interfacing the AD7654 to SPI Interface
APPLICATION HINTS
Layout
The AD7654 has very good immunity to noise on the power
supplies, as seen in Figure 5. However, care should still be
taken with regard to grounding layout.
The printed circuit board that houses the AD7654 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7654, or, at least as close as possible to the
AD7654. If the AD7654 is in a system where multiple devices
require analog-to-digital ground connections, the connection
should still be made at one point only, a star ground point
that should be established as close as possible to the AD7654.
It is recommended to avoid running digital lines under the
device as these will couple noise onto the die. The analog
ground plane should be allowed to run under the AD7654 to
avoid noise coupling. Fast switching signals like
CNVST or
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board, and should never run near
analog signal paths. Crossover of digital and analog signals
should be avoided. Traces on different but close layers of the
board should run at right angles to each other. This will reduce
the effect of feedthrough through the board. The power supply
lines to the AD7654 should use as large a trace as possible to
provide low impedance paths and reduce the effect of glitches
on the power supply lines. Good decoupling is also important to
lower the supply's impedance presented to the AD7654 and
to reduce the magnitude of the supply spikes. Decoupling ceramic
capacitors, typically 100 nF, should be placed on each power
supply's pins, AVDD, DVDD, and OVDD, close to and ideally
right up against these pins and their corresponding ground pins.
Additionally, low ESR 10
F capacitors should be located in the
vicinity of the ADC to further reduce low frequency ripple.
The DVDD supply of the AD7654 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy or fast switching digital signals are present, it is recom-
mended that if no separate supply is available, the DVDD digital
supply should be connected to the analog supply AVDD through an
RC filter, as shown in Figure 5, and the system supply should
be connected to the interface digital supply OVDD and the
remaining digital circuitry. When DVDD is powered from the
system supply, it is useful to insert a bead to further reduce high
frequency spikes.
The AD7654 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage
and should be a low impedance return to the reference because
it carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground
plane depending on the configuration. OGND is connected to
the digital system ground.
The layout of the decoupling of the reference voltage is impor-
tant. The decoupling capacitor should be close to the ADC and
connected with short and large traces to minimize parasitic
inductances.
Evaluating the AD7654's Performance
A recommended layout for the AD7654 is outlined in the
documentation of the evaluation board for the AD7654. The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the Eval-Control BRD2.
REV. 0
AD7654
21
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4mm Thick
(ST-48)
Dimensions shown in millimeters
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
7.00
BSC
SEATING
PLANE
1.60 MAX
0.75
0.60
0.45
VIEW A
7
3.5
0
0.20
0.09
1.45
1.40
1.35
0.15
0.05
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90 CCW
PIN 1
INDICATOR
9.00 BSC
COMPLIANT TO JEDEC STANDARDS MS-026BBC
SEATING
PLANE
48-Lead Frame Chip Scale Package [LFCSP]
(CP-48)
Dimensions shown in millimeters
PIN 1
INDICATOR
TOP
VIEW
6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
BOTTOM
VIEW
5.25
4.70
2.25
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12
MAX
0.25
REF
0.70 MAX
0.65 NOM
1.00
0.90
0.80
5.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
COPLANARITY
0.08
SQ
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
22
23
C03057010/02(0)
PRINTED IN U.S.A.
24
Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- PRODUCT HIGHLIGHTS
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- ORDERING GUIDE
- PIN CONFIGURATION
- PIN FUNCTION DESCRIPTIONS
- DEFINITION OF SPECIFICATIONS
- Integral Nonlinearity Error (INL)
- Differential Nonlinearity Error (DNL)
- Full-Scale Error
- Unipolar Zero Error
- Spurious-Free Dynamic Range (SFDR)
- Effective Number of Bits (ENOB)
- Total Harmonic Distortion (THD)
- Signal-to-Noise Ratio (SNR)
- Signal-to-(Noise+Distortion) Ratio (S/[N+D])
- Aperture Delay
- Transient Response
- Typical Performance Characteristics
- CIRCUIT INFORMATION
- Modes of Operation
- Transfer Functions
- TYPICAL CONNECTION DIAGRAM
- Analog Inputs
- Driver Amplifier Choice
- Voltage Reference Input
- Power Supply
- POWER DISSIPATION
- CONVERSION CONTROL
- DIGITAL INTERFACE
- PARALLEL INTERFACE
- SERIAL INTERFACE
- MASTER SERIAL INTERFACE
- SLAVE SERIAL INTERFACE
- External Clock
- External Discontinuous Clock Data Read after Conversion
- External Clock Data Read during Conversion
- MICROPROCESSOR INTERFACING
- SPI Interface (ADSP-219x)
- APPLICATION HINTS
- Layout
- Evaluating the AD7654s Performance
- OUTLINE DIMENSIONS
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