Äîêóìåíòàöèÿ è îïèñàíèÿ www.docs.chipfind.ru

FUNCTIONAL BLOCK DIAGRAM

FEATURES
Charge Balancing ADC

24 Bits No Missing Codes

0.0015% Nonlinearity

Two-Channel Programmable Gain Front End

Gains from 1 to 128
One Differential Input
One Single-Ended Input

Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
RTD Excitation Current Sources
Bidirectional Microcontroller Serial Interface
Internal/External Reference Option
Single or Dual Supply Operation
Low Power (25 mW typ) with Power-Down Mode

(7 mW typ)

APPLICATIONS
RTD Transducers
Process Control
Smart Transmitters
Portable Industrial Instruments

MOS Signal Conditioning ADC

with RTD Excitation Currents

REV. F

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

GENERAL DESCRIPTION

The AD7711 is a complete analog front end for low frequency
measurement applications. The device accepts low level signals
directly from a transducer and outputs a serial digital word. It
employs a sigma-delta conversion technique to realize up to
24 bits of no missing codes performance. The input signal is
applied to a proprietary programmable gain front end based
around an analog modulator. The modulator output is pro-
cessed by an on-chip digital filter. The first notch of this digital
filter can be programmed via the on-chip control register allow-
ing adjustment of the filter cutoff and settling time.

The part features one differential analog input and one single
ended analog input as well as a differential reference input.
Normally, one of the input channels will be used as the main
channel with the second channel used as an auxiliary input to
periodically measure a second voltage. It can be operated from a
single supply (by tying the V

pin to AGND) provided that the

input signals on the analog inputs are more positive than
30 mV. By taking the V

pin negative, the part can convert

signals down to V

REF

on its inputs. The part provides two

current sources that can be used to provide excitation in three-
wire and four-wire RTD configurations. The AD7711 thus
performs all signal conditioning and conversion for a single or
dual channel system.

The AD7711 is ideal for use in smart, microcontroller based
systems. Gain settings, signal polarity, input channel selection

AD7711*

and RTD current control can be configured in software using
the bidirectional serial port. The AD7711 contains self-
calibration, system calibration and background calibration
options and also allows the user to read and write the on-chip
calibration registers.

CMOS construction ensures low power dissipation, and a soft-
ware programmable power-down mode reduces the standby
power consumption to only 7 mW typical. The part is available
in a 24-lead, 0.3 inch wide, plastic and hermetic dual-in-line
package (DIP) as well as a 24-lead small outline (SOIC)
package.

PRODUCT HIGHLIGHTS

1. The programmable gain front end allows the AD7711 to

accept input signals directly from an RTD transducer,
removing a considerable amount of signal conditioning.
On-chip current sources provide excitation for three-wire and
four-wire RTD configurations.

2. No Missing Codes ensure true, usable, 23-bit dynamic range

coupled with excellent

0.0015% accuracy. The effects of

temperature drift are eliminated by on-chip self-calibration,
which removes zero-scale and full-scale errors.

3. The AD7711 is ideal for microcontroller or DSP processor

applications with an on-chip control register which allows
control over filter cutoff, input gain, channel selection, signal
polarity, RTD current control and calibration modes.

4. The AD7711 allows the user to read and to write the on-chip

calibration registers. This means that the microcontroller has
much greater control over the calibration procedure.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1998

*Protected by U.S. Patent No. 5,134,401.

CLOCK

GENERATION

SERIAL INTERFACE

CONTROL

REGISTER

OUTPUT

REGISTER

CHARGE-BALANCING A/D

CONVERTER

AUTO-ZEROED

MODULATOR

DIGITAL

FILTER

AD7711

U
X

AGND DGND

MODE SDATA SCLK

MCLK
OUT

MCLK
IN

AIN1(+)

AIN1()

REF

IN ()

REF

IN (+)

SYNC

4.5 A

A = 1 128

DRDY

TFS

RFS

REF OUT

2.5V REFERENCE

200 A

AIN2

BIAS

PGA

RTD2

200 A

RTD1

Parameter

A, S Versions

Units

Conditions/Comments

STATIC PERFORMANCE

No Missing Codes

Bits min

Guaranteed by Design. For Filter Notches

60 Hz

Bits min

For Filter Notch = 100 Hz

Bits min

For Filter Notch = 250 Hz

Bits min

For Filter Notch = 500 Hz

Bits min

For Filter Notch = 1 kHz

Output Noise

See Tables I & II

Depends on Filter Cutoffs and Selected Gain

Integral Nonlinearity @ +25

0.0015

% FSR max

Filter Notches

60 Hz

MIN

to T

MAX

0.003

% FSR max

Typically

0.0003%

Positive Full-Scale Error

2, 3

See Note 4

Excluding Reference

Full-Scale Drift

C typ

Excluding Reference. For Gains of 1, 2

0.3

C typ

Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

Unipolar Offset Error

See Note 4

Unipolar Offset Drift

0.5

C typ

For Gains of 1, 2

0.25

C typ

For Gains of 4, 8, 16, 32, 64, 128

Bipolar Zero Error

See Note 4

Bipolar Zero Drift

0.5

C typ

For Gains of 1, 2

0.25

C typ

For Gains of 4, 8, 16, 32, 64, 128

Gain Drift

ppm/

C typ

Bipolar Negative Full-Scale Error

@ +25

0.003

% FSR max

Excluding Reference

MIN

to T

MAX

0.006

% FSR max

Typically

0.0006%

Bipolar Negative Full-Scale Drift

C typ

Excluding Reference. For Gains of 1, 2

0.3

C typ

Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128

ANALOG INPUTS/REFERENCE INPUTS

Normal-Mode 50 Hz Rejection

100

dB min

For Filter Notches of 10, 25, 50 Hz,

0.02

NOTCH

Normal-Mode 60 Hz Rejection

100

dB min

For Filter Notches of 10, 30, 60 Hz,

0.02

NOTCH

DC Input Leakage Current

@ +25

pA max

MIN

to T

MAX

nA max

Sampling Capacitance

pF max

AIN1/REF IN

Common-Mode Rejection (CMR)

100

dB min

At DC

Common-Mode 50 Hz Rejection

150

dB min

For Filter Notches of 10, 25, 50 Hz,

0.02

NOTCH

Common-Mode 60 Hz Rejection

150

dB min

For Filter Notches of 10, 30, 60 Hz,

0.02

NOTCH

Common-Mode Voltage Range

to AV

V min to V max

Analog Inputs

Input Voltage Range

For Normal Operation. Depends on Gain Selected

0 to +V

REF

max

Unipolar Input Range (B/U Bit of Control Register = 1)

REF

max

Bipolar Input Range (B/U Bit of Control Register = 0)

Input Sampling Rate, f

See Table III

AIN2 Offset Error

2.5

mV max

Removed by System Calibrations but not by Self-Calibration

AIN2 Offset Drift

1.5

C typ

Reference Inputs

REF IN(+) REF IN() Voltage

+2.5 to +5

V min to V max

For Specified Performance. Part Is Functional with
Lower V

REF

Voltages

Input Sampling Rate, f

CLK IN

/256

REFERENCE OUTPUT

Output Voltage

2.5

V nom

Initial Tolerance @ +25

% max

Drift

ppm/

C typ

Output Noise

V typ

pk-pk Noise. 0.1 Hz to 10 Hz Bandwidth

Line Regulation (AV

)

mV/V max

Load Regulation

1.5

mV/mA max

Maximum Load Current 1 mA

External Current

mA max

NOTES

Temperature range is as follows: A Version = 40

C to +85

C; S Version = 55

C to +125

C. See also Note 16.

Applies after calibration at the temperature of interest.

Positive full-scale error applies to both unipolar and bipolar input ranges.

These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20

V typical after self-calibration or

background calibration.

Recalibration at any temperature or use of the background calibration mode will remove these drift errors.

These numbers are guaranteed by design and/or characterization.

This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN() does not exceed AV

+ 30 mV and V

30 mV.

The analog inputs present a very high impedance dynamic load which varies with clock frequency and input sample rate. The maximum recommended source

resistance depends on the selected gain (see Tables IV and V).

The analog input voltage range on the AIN1(+) input is given here with respect to the voltage on the AIN1() input. The input voltage range on the AIN2 input is

with respect to AGND. The absolute voltage on the analog inputs should not go more positive than A V

+ 30 mV or go more negative than V

30 mV.

REF

= REF IN(+) REF IN().

The reference input voltage range may be restricted by the input voltage range requirement on the V

BIAS

input.

AD7711SPECIFICATIONS

REV. F

(AV

= +5 V

5%; DV

= +5 V 5%; V

= 0 V or 5 V 5%; REF IN(+) =

+2.5 V; REF IN() = AGND; MCLK IN = 10 MHz unless otherwise stated. All specifications T

MIN

to T

MAX

unless otherwise noted.)

Parameter

A, S Versions

Units

Conditions/Comments

BIAS

INPUT

Input Voltage Range

0.85

REF

See V

BIAS

Input Section

or AV

3.5

V max

Whichever Is Smaller; +5 V/5 V or +10 V/0 V
Nominal AV

or AV

2.1

V max

Whichever Is Smaller; +5 V/0 V Nominal AV

+ 0.85

REF

See V

BIAS

Input Section

or V

+ 3

V min

Whichever Is Greater; +5 V/5 V or +10 V/0 V
Nominal AV

or V

+ 2.1

V min

Whichever Is Greater; +5 V/0 V Nominal AV

BIAS

Rejection

65 to 85

dB typ

Increasing with Gain

LOGIC INPUTS

Input Current

A max

All Inputs except MCLK IN

INL

, Input Low Voltage

0.8

V max

INH

, Input High Voltage

2.0

V min

MCLK IN Only

INL

, Input Low Voltage

0.8

V max

INH

, Input High Voltage

3.5

V min

LOGIC OUTPUTS

, Output Low Voltage

0.4

V max

SINK

= 1.6 mA

, Output High Voltage

4.0

V min

SOURCE

= 100

Floating State Leakage Current

A max

Floating State Output Capacitance

pF typ

TRANSDUCER BURNOUT

Current

4.5

A nom

Initial Tolerance @ +25

% typ

Drift

0.1

C typ

RTD EXCITATION CURRENTS (RTD1, RTD2)

Output Current

200

A nom

Initial Tolerance @ +25

% max

Drift

ppm/

C typ

Initial Matching @ +25

% max

Matching Between RTD1 and RTD2 Currents

Drift Matching

ppm/

C typ

Matching Between RTD1 and RTD2 Current Drift

Line Regulation (AV

)

200

nA/V max

= +5 V

Load Regulation

200

nA/V max

Output Compliance

V max

SYSTEM CALIBRATION

Positive Full-Scale Calibration Limit

(1.05

REF

)/GAIN

V max