FUNCTIONAL BLOCK DIAGRAM
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
8-Bit 20 MSPS, 60 mW
Sampling A/D Converter
AD775
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
CMOS 8-Bit 20 MSPS Sampling A/D Converter
Low Power Dissipation: 60 mW
+5 V Single Supply Operation
Differential Nonlinearity: 0.3 LSB
Differential Gain: 1%
Differential Phase: 0.5 Degrees
Three-State Outputs
On-Chip Reference Bias Resistors
Adjustable Reference Input
Video Industry Standard Pinout
Small Packages:
24-Pin 300 Mil SOIC Surface Mount
24-Pin 400 Mil Plastic DIP
PRODUCT DESCRIPTION
The AD775 is a CMOS, low power, 8-bit, 20 MSPS sampling
analog-to-digital converter (ADC). The AD775 features a built-
in sampling function and on-chip reference bias resistors to pro-
vide a complete 8-bit ADC solution. The AD775 utilizes a
pipelined/ping pong two-step flash architecture to provide high
sampling rates (up to 35 MHz) while maintaining very low
power consumption (60 mW).
Its combination of excellent DNL, fast sampling rate, low dif-
ferential gain and phase errors, extremely low power dissipation,
and single +5 V supply operation make it ideally suited for a
variety of video and image acquisition applications, including
portable equipment. The AD775's reference ladder may be con-
nected in a variety of configurations to accommodate different
input ranges. The low input capacitance (11 pF typical) provides
an easy-to-drive input load compared to conventional flash
converters.
The AD775 is offered in both 300 mil SOIC and 400 mil DIP
plastic packages, and is designed to operate over an extended
commercial temperature range (20
C to +75
C).
PRODUCT HIGHLIGHTS
Low Power: The AD775 has a typical supply current of 12 mA,
for a power consumption of 60 mW. Reference ladder current
is also low: 6.6 mA typical, minimizing the reference power
consumption.
Complete Solution: The AD775's switched capacitor design
features an inherent sample/hold function: no external SHA is
required. On-chip reference bias resistors are included to allow
a supply-based reference to be generated without any external
resistors.
Excellent Differential Nonlinearity: The AD775 features a
typical DNL of 0.3 LSBs, with a maximum limit of 0.5 LSBs.
No missing codes is guaranteed.
Single +5 V Supply Operation: The AD775 is designed to oper-
ate on a single +5 V supply, and the reference ladder may be
configured to accommodate analog inputs inclusive of ground.
Low Input Capacitance: The 11 pF input capacitance of the
AD775 can significantly decrease the cost and complexity of
input driving circuitry, compared with conventional 8-bit flash
ADCs.
1
2
7
8
3
4
5
6
9
10
15
16
14
13
12
11
19
20
17
18
21
24
23
22
CLOCK LOGIC
FINE COMPARATORS
BANK B
FINE COMPARATORS
BANK A
COARSE
COMPARATORS
CORRECTION LOGIC
AV
DD
AV
SS
3-STATE OUTPUT LATCHES
D7 (MSB)
D0 (LSB)
RREF
15
SWITCH
MATRIX
V
RTS
V
RT
V
RB
V
RBS
OE
AV
SS
CLK
DV
SS
AV
DD
V
IN
DV
DD
AD775
4
8
5
255
LSB MULTIPLEXOR
REV. 0
2
AD775SPECIFICATIONS
AD775J
Parameter
Min
Typ
Max
Units
RESOLUTION
8
Bits
DC ACCURACY
Integral Nonlinearity (INL)
+0.5
1.3
LSB
Differential Nonlinearity (DNL)
0.3
0.5
LSB
No Missing Codes
GUARANTEED
Offset
To Top of Ladder V
RT
10
35
60
mV
To Bottom of Ladder V
RB
0
+15
+45
mV
VIDEO ACCURACY
1
Differential Gain Error
1.0
%
Differential Phase Error
0.5
Degrees
ANALOG INPUT
Input Range (V
RT
V
RB
)
2.0
V p-p
Input Capacitance
11
pF
AC SPECIFICATIONS
2
Signal-to-Noise and Distortion (S/(N + D))
f
IN
= 1 MHz
47
dB
f
IN
= 5 MHz
41
dB
Total Harmonic Distortion (THD)
f
IN
= 1 MHz
51
dB
f
IN
= 5 MHz
42
dB
REFERENCE INPUT
Reference Input Resistance (R
REF
)
230
300
450
Case 1: V
RT
= V
RTS
, V
RB
= V
RBS
Reference Bottom Voltage (V
RB
)
0.60
0.64
0.68
V
Reference Span (V
RT
V
RB
)
1.96
2.09
2.21
V
Reference Ladder Current (I
REF
)
4.4
7.0
9.6
mA
Case 2: V
RT
= V
RTS
, V
RB
= AV
SS
Reference Span (V
RT
V
RB
)
2.25
2.39
2.53
V
Reference Ladder Current (I
REF
)
5
8
11
mA
POWER SUPPLIES
Operating Voltages
AV
DD
+4.75
+5.25
Volts
DV
DD
+4.75
+5.25
Volts
Operating Current
IAV
DD
9.5
mA
IDV
DD
2.5
mA
IAV
DD
+ IDV
DD
12
17
mA
POWER CONSUMPTION
60
85
mW
TEMPERATURE RANGE
Operating
20
+75
C
NOTES
1
NSTC 40 IRE modulation ramp, CLOCK = 14.3 MSPS.
2
f
IN
amplitude = 0.3 dB full scale.
Specifications subject to change without notice. See Definition of Specifications for additional information.
(T
A
= +25 C with AV
DD
, DV
DD
= +5 V, AV
SS
, DV
SS
= 0 V, V
RT
= 2.6 V, V
RB
= +0.6 V,
CLOCK = 20 MHz unless otherwise noted)
3
REV. 0
AD775
DIGITAL SPECIFICATIONS
AD775J
Parameter
Symbol
DV
DD
Min
Typ
Max
Units
LOGIC INPUT
High Level Input Voltage
V
IH
5.0
4.0
V
Low Level Input Voltage
V
IL
5.0
1.0
V
High Level Input Current
(V
IH
= DV
DD
)
I
IH
5.25
5
A
Low Level Input Current
(V
IL
= 0 V)
I
IL
5.25
5
A
Logic Input Capacitance
C
IN
5
pF
LOGIC OUTPUTS
High Level Output Current
OE
= DV
SS
, V
OH
= DV
DD
0.5 V
I
OH
4.75
1.1
mA
OE
= DV
DD
, V
OH
= DV
DD
I
OZ
5.25
16
A
Low Level Output Current
OE
= DV
SS
, V
OL
= 0.4 V
I
OL
4.75
3.7
mA
OE
= DV
DD
, V
OL
= 0 V
I
OZ
5.25
16
A
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Units
Maximum Conversion Rate
20
35
MHz
Clock Period
t
C
50
ns
Clock High
t
CH
25
ns
Clock Low
t
CL
25
ns
Output Delay
t
OD
18
30
ns
Pipeline Delay (Latency)
2.5
Clock Cycles
Sampling Delay
t
DS
4
ns
Aperture Jitter
30
ps
Specifications subject to change without notice.
VIN
CLK
OUT
SAMPLE N
SAMPLE N+1
SAMPLE N+2
DATA N-3
DATA N-2
DATA N-1
DATA N
t
OD
t
C
t
CL
t
CH
t
DS
Figure 1. AD775 Timing Diagram
(T
A
= +25 C with AV
DD
, DV
DD
= +5 V, AV
SS
, DV
SS
= 0 V, V
RT
= 2.6 V, V
RB
= +0.6 V,
CLOCK = 20 MHz unless otherwise noted)
AD775
REV. 0
4
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD775 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN DESCRIPTION
Pin No.
Symbol
Type Name and Function
1
OE
DI
OE
= Low
OE
= High
Normal Operating Mode.
High Impedance Outputs.
2, 24
DV
SS
P
Digital Ground. Note: DV
SS
and AV
SS
pins should share a common ground plane on the circuit board.
3
D0 (LSB)
DO
Least Significant Bit, Data Bit 0.
49
D1D6
DO
Data Bits 1 Through 6.
10
D7 (MSB)
DO
Most Significant Bit, Data Bit 7.
11, 13
DV
DD
P
+5 V Digital Supply. Note: DV
DD
and AV
DD
pins should share a common supply on the circuit board.
12
CLK
DI
Clock Input.
16
V
RTS
AI
Reference Top Bias. Short to V
RT
for Self-Bias.
17
V
RT
AI
Reference Ladder Top.
23
V
RB
AI
Reference Ladder Bottom.
22
V
RBS
AI
Reference Bottom Bias. Short to V
RB
for Self-Bias.
14, 15, 18 AV
DD
P
+5 V Analog Supply. Note: DV
DD
and AV
DD
pins should share a common supply within 0.5 inches
of the AD775.
19
V
IN
AI
Analog Input. Input Span = V
RT
V
RB
.
20, 21
AV
SS
P
Analog Ground. Note: DV
SS
and AV
SS
pins should share a common ground within 0.5 inches of the
AD775.
NOTE
Type: AI = Analog Input; DI = Digital Input; DO = Digital Output; P = Power.
PIN CONFIGURATION
(DIP and SOIC)
MAXIMUM RATINGS*
Supply Voltage (AV
DD
, DV
DD
) . . . . . . . . . . . . . . . . . . . . 7 V
Supply Difference (AV
DD
DV
DD
) . . . . . . . . . . . . . . . . . . 0 V
Ground Difference (AV
SS
DV
SS
) . . . . . . . . . . . . . . . . . . . 0 V
Reference Voltage (V
RT
, V
RB
) . . . . . . . . . . . . . . . . V
DD
to V
SS
Analog Input Voltage (V
IN
) . . . . . . . . . . . . . . . . . . V
DD
to V
SS
Digital Input Voltage (CLK) . . . . . . . . . . . . . . . . . V
DD
to V
SS
Digital Output Voltage (V
OH
, V
OL
) . . . . . . . . . . . . V
DD
to V
SS
Storage Temperature . . . . . . . . . . . . . . . . . . 55
C to +150
C
*Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD775JN 20
C to +75
C 24-Pin 400 Mil Plastic DIP N-24B
AD775JR 20
C to +75
C 24-Pin 300 Mil SOIC
R-24A
AD775
REV. 0
5
30
54
0.1
1
10
36
42
48
f
IN
MHz
THD dB
Figure 5. THD vs. Input Frequency at 20 MSPS Clock Rate
(V
IN
= 0.3 dB)
0
100
10.0
70
90
1.0
80
0
40
60
50
30
20
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
FREQUENCY MHz
dB
Figure 6. Typical FFT at 5 MHz Input, 20 MSPS Clock Rate
(V
IN
= 0.5 dB)
+1
1
+FULLSCALE
FULLSCALE
0
INL LSB
Figure 7. Typical Integral Nonlinearity (INL)
54
48
0
0.1
1
10
42
36
30
24
18
12
6
f
IN
MHz
S/(N + D) dB
Figure 2. S/(N + D) vs. Input Frequency at 20 MSPS Clock
Rate (V
IN
= 0.3 dB)
0
100
10.0
70
90
1.0
80
0
40
60
50
30
20
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
FREQUENCY MHz
dB
Figure 3. Typical FFT at 1 MHz Input, 20 MSPS Clock Rate
(V
IN
= 0.5 dB)
+0.4
0.4
+FULLSCALE
0.2
0.3
FULLSCALE
0
0.1
+0.1
+0.2
+0.3
DNL LSB
Figure 4. Typical Differential Nonlinearity (DNL)
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