Document Outline
- FEATURES
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- PRODUCT HIGHLIGHTS
- SPECIFICATIONS
- Test Circuits
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATIONS
- ORDERING GUIDE
- Typical Performance Characteristics
- OPERATIONAL DIAGRAM
- CIRCUIT INFORMATION BASIC DESCRIPTION
- APPLYING THE AD7824/AD7828 REFERENCE AND INPUT
- INPUT CURRENT
- INHERENT SAMPLE-HOLD
- SINUSOIDAL INPUTS
- UNIPOLAR OPERATION
- BIPOLAR OPERATION
- TIMING AND CONTROL
- MODE 0
- MODE 1
- MICROPROCESSOR INTERFACING
- Z80 MICROPROCESSOR
- MC68000 MICROPROCESSOR
- TMS32010 MICROCOMPUTER
- OUTLINE DIMENSIONS
- Revision History
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
a
LC
2
MOS High Speed
4- and 8-Channel 8-Bit ADCs
AD7824/AD7828
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
2003 Analog Devices, Inc. All rights reserved.
FUNCTIONAL BLOCK DIAGRAM
RDY
CS
RD
INT
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
THREE-
STATE
DRIVERS
4-BIT
FLASH
ADC
(4LSB)
V
REF
(+)
16
TIMING AND CONTROL
CIRCUITRY
ADDRESS
LATCH
DECODE
AIN1
AIN4
AIN8
MUX*
*AD7824 4-CHANNEL MUX
**AD7828 8-CHANNEL MUX
A2 AD7828 ONLY
A0 A1 A2**
V
REF
(+)
V
REF
()
4-BIT
FLASH
ADC
(4MSB)
4-BIT
DAC
FEATURES
4 or 8 Analog Input Channels
Built-In Track-and-Hold Function
10 kHz Signal Handling on Each Channel
Fast Microprocessor Interface
Single 5 V Supply
Low Power: 50 mW
Fast Conversion Rate: 2.5 s/Channel
Tight Error Specification: 1/2 LSB
GENERAL DESCRIPTION
The AD7824 and AD7828 are high speed, multichannel, 8-bit
ADCs with a choice of four (AD7824) or eight (AD7828) multi-
plexed analog inputs. A half-flash conversion technique gives a fast
conversion rate of 2.5
s per channel, and the parts have a built-in
track-and-hold function capable of digitizing full-scale signals of
10 kHz (157 mV/
s slew rate) on all channels. The AD7824 and
AD7828 operate from a single 5 V supply and have an analog input
range of 0 V to 5 V, using an external 5 V reference.
Microprocessor interfacing of the parts is simple, using standard
Chip Select (
CS) and Read (RD) signals to initiate the conversion
and read the data from the three-state data outputs. The half-flash
conversion technique means that there is no need to generate a
clock signal for the ADC. The AD7824 and AD7828 can be
interfaced easily to most popular microprocessors.
The AD7824 and AD7828 are fabricated in an advanced, all
ion-implanted, linear compatible CMOS process (LC
2
MOS) and
have low power dissipation of 40 mW (typ). The AD7824 is
available in a 0.3" wide, 24-lead "skinny" DIP, while the AD7828
is available in a 0.6" wide, 28-lead DIP and in 28-terminal surface-
mount packages.
PRODUCT HIGHLIGHTS
1. 4- or 8-channel input multiplexer gives cost effective,
space-saving multichannel ADC system.
2. Fast conversion rate of 2.5
s/channel features a per-channel
sampling frequency of 100 kHz for the AD7824 or 50 kHz
for the AD7828.
3. Built-in track-and-hold function allows handling of four or
eight channels up to 10 kHz bandwidth (157 mV/
s slew rate).
4. Tight total unadjusted error spec and channel-to-channel
matching eliminate the need for user trims.
5. Single 5 V supply simplifies system power requirements.
6. Fast, easy-to-use digital interface allows connection to most
popular microprocessors with minimal external components.
No clock signal is required for the ADC.
REV. F
2
AD7824/AD7828SPECIFICATIONS
(V
DD
= 5 V, V
REF
(+) = 5 V, V
REF
() = GND = O V, unless otherwise
noted. All specifications T
MIN
to T
MAX
, unless otherwise noted. Specifications apply to Mode 0.)
Parameter
K Version
1
L Version
B, T Versions
C, U Versions Unit
Conditions/Comments
ACCURACY
Resolution
8
8
8
8
Bits
Total Unadjusted Error
2
1
1/2
1
1/2
LSB max
Minimum Resolution for which
No Missing Codes Are Guaranteed 8
8
8
8
Bits
Channel-to-Channel Mismatch
1/4
1/4
1/4
1/4
LSB max
REFERENCE INPUT
Input Resistance
1.0/4.0
1.0/4.0
1.0/4.0
1.0/4.0
k
min/k max
V
REF
(+) Input Voltage Range
V
REF
()/
V
REF
()/
V
REF
()/
V
REF
()/
V min/V max
V
DD
V
DD
V
DD
V
DD
V
REF
() Input Voltage Range
GND/
GND/
GND/
GND/
V min/V max
V
REF
(+)
V
REF
(+)
V
REF
(+)
V
REF
(+)
ANALOG INPUT
Input Voltage Range
V
REF
()/
V
REF
()/
V
REF
()/
V
REF
()/
V min/V max
V
REF
(+)
V
REF
(+)
V
REF
(+)
V
REF
(+)
Input Leakage Current
3
3
3
3
A max
Analog Input Any Channel
Input Capacitance
3
45
45
45
45
pF typ
0 V to 5 V
LOGIC INPUTS
RD, CS, A0, A1, and A2
V
INH
2.4
2.4
2.4
2.4
V min
V
INL
0.8
0.8
0.8
0.8
V max
I
INH
1
1
1
1
A max
I
INL
1
1
1
1
A max
Input Capacitance
3
8
8
8
8
pF max
Typically 5 pF
LOGIC OUTPUTS
DB0DB7 and
INT
V
OH
4.0
4.0
4.0
4.0
V min
I
SOURCE
= 360
A
V
OL
0.4
0.4
0.4
0.4
V max
I
SINK
= 1.6 mA
I
OUT
(DB0DB7)
3
3
3
3
A max
Floating State Leakage
Output Capacitance
3
8
8
8
8
pF max
Typically 5 pF
RDY
V
OL
4
0.4
0.4
0.4
0.4
V max
I
SINK
= 2.6 mA
I
OUT
3
3
3
3
A max
Floating State Leakage
Output Capacitance
8
8
8
8
pF max
Typically 5 pF
SLEW RATE, TRACKING
3
0.7
0.7
0.7
0.7
V/
s typ
0.157
0.157
0.157
0.157
V/
s max
POWER SUPPLY
V
DD
5
5
5
5
V
5% for Specified
Performance
I
DD
5
16
16
20
20
mA max
CS = RD = 2.4 V
Power Dissipation
50
50
50
50
mW typ
80
80
100
100
mW max
Power Supply Sensitivity
1/4
1/4
1/4
1/4
LSB max
1/16 LSB typ
V
DD
= 5 V
5%
NOTES
1
Temperature ranges are as follows:
K, L Versions: 0
C to 70C
B, C Versions: 40
C to +85C
T, U Versions: 55
C to +125C
2
Total Unadjusted Error includes offset, full-scale and linearity errors.
3
Sample tested at 25
C by Product Assurance to ensure compliance.
4
RDY is an open-drain output.
5
See Typical Performance Characteristics.
Specifications subject to change without notice.
AD7824/AD7828
REV. F
3
TIMING CHARACTERISTICS
1
(V
DD
= 5 V; V
REF
(+) = 5 V; V
REF
() = GND = 0 V, unless otherwise noted.)
Limit at 25 C
Limit at T
MIN
, T
MAX
Limit at T
MIN
, T
MAX
Parameter
(All Grades)
(K, L, B, C Grades)
(T, U Grades)
Unit
Conditions/Comments
t
CSS
0
0
0
ns min
CS to RD Setup Time
t
CSH
0
0
0
ns min
CS to RD Hold Time
t
AS
0
0
0
ns min
Multiplexer Address Setup Time
t
AH
30
35
40
ns min
Multiplexer Address Hold Time
t
RDY
2
40
60
60
ns max
CS to RDY Delay. Pull-Up
Resistor 5 k
.
t
CRD
2.0
2.4
2.8
s max
Conversion Time, Mode 0
t
ACC1
3
85
110
120
ns max
Data Access Time after
RD
t
ACC2
3
50
60
70
ns max
Data Access Time after
INT, Mode 0
t
lNTH
2
40
65
70
ns typ
RD to INT Delay
75
100
100
ns max
t
DH
4
60
70
70
ns max
Data Hold Time
t
P
500
500
600
ns min
Delay Time between Conversions
t
RD
60
80
80
ns min
Read Pulsewidth, Mode 1
600
500
400
ns max
NOTES
1
Sample tested at 25
C to ensure compliance. All input control signals are specified with t
RISE
= t
FALL
= 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
C
L
= 50 pF.
3
Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
DBN
3k
100pF
DGND
a. High-Z to V
OH
DBN
3k
100pF
DGND
5V
b. High-Z to V
OL
Figure 1. Load Circuits for Data Access Time Test
DBN
3k
10pF
DGND
a. V
OH
to High-Z
DBN
3k
10pF
DGND
5V
b. V
OL
to High-Z
Figure 2. Load Circuits for Data Hold Time Test
AD7824/AD7828
4
REV. F
Operating Temperature Range
Commercial (K, L Versions) . . . . . . . . . . . . . . 0
C to 70C
Industrial (B, C Versions) . . . . . . . . . . . . . 40
C to +85C
Extended (T, U Versions) . . . . . . . . . . . . 55
C to +125C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 300
C
Power Dissipation (Any Package) to 75
C . . . . . . . . . 450 mW
Derates above 75
C by . . . . . . . . . . . . . . . . . . . . . . 6 mW/C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
*
(T
A
= 25
C, unless otherwise noted.)
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V
Digital Input Voltage to GND
(
RD, CS, A0, A1, and A2) . . . . . . . . . 0.3 V, V
DD
+ 0.3 V
Digital Output Voltage to GND
(DB0, DB7, RDY, and
INT) . . . . . . . 0.3 V, V
DD
+ 0.3 V
V
REF
(+) to GND . . . . . . . . . . . . . . . . . V
REF
(), V
DD
+ 0.3 V
V
REF
() to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
REF
(+)
Analog Input (Any Channel) . . . . . . . . . . 0.3 V, V
DD
+ 0.3 V
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although AD7824/AD7828 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATIONS
DIP/SOIC/SSOP
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7824
NC = NO CONNECT
AIN4
V
DD
AIN3
NC
AIN2
A0
AIN1
A1
NC
DB7
DB0
DB6
DB1
DB5
DB2
DB4
DB3
CS
RD
RDY
INT
V
REF
(+)
GND
V
REF
()
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD7828
NC = NO CONNECT
AIN6
AIN7
AIN5
AIN8
AIN4
V
DD
AIN3
A0
AIN2
A1
AIN1
A2
NC
DB7
DB0
DB6
DB1
DB5
DB2
DB4
DB3
CS
RD
RDY
INT
V
REF
(+)
GND
V
REF
()
WARNING!
ESD SENSITIVE DEVICE
PLCC
25
24
23
22
21
20
19
5
6
7
8
9
10
11
4 3 2 1 28 27 26
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
12 13 14 15
16 17 18
A0
AIN2
V
DD
RD
NC = NO CONNECT
AD7828
A1
AIN1
A2
NC
DB7
DB0
DB6
DB1
DB5
DB2
DB4
DB3
AIN8
AIN7
AIN6
AIN5
AIN4
AIN3
INT
GND
V
REF
()
V
REF
(+)
RD
Y
CS
LCCC
TOP VIEW
(Not to Scale)
28 27
1
2
3
4
26
25
21
22
23
24
19
20
5
6
7
8
9
10
11
12 13 14 15 16 17 18
AD7828
AIN2
A0
V
DD
RD
AIN1
A1
NC
A2
DB0
DB7
DB1
DB6
DB2
DB5
DB3
DB4
AIN8
AIN7
AIN6
AIN5
AIN4
AIN3
INT
GND
V
REF
()
V
REF
(+)
RD
Y
CS
NC = NO CONNECT
ORDERING GUIDE
Total
Temperature
Unadjusted
Package
Model
Range
Error (LSBs) Option
AD7824KN
0
C to 70C
1
N-24
AD7824LN
0
C to 70C
1/2
N-24
AD7824KR
0
C to 70C
1
R-24
AD7824BQ
40
C to +85C
1
Q-24
AD7824CQ
40
C to +85C
1/2
Q-24
AD7824TQ
*
55
C to +125C
1
Q-24
AD7824UQ
*
55
C to +125C
1/2
Q-24
AD7828KN
0
C to 70C
1
N-28
AD7828LN
0
C to 70C
1/2
N-28
AD7828KP
0
C to 70C
1
P-28A
AD7828LP
0
C to 70C
1/2
P-28A
AD7828BQ
40
C to +85C
1
Q-28
AD7828CQ
40
C to +85C
1/2
Q-28
AD7828BR
40
C to +85C
+1
R-28
AD7828LRS
0
C to 70C
1/2
RS-28
AD7828TQ
*
55
C to +125C
1
Q-28
AD7828UQ
*
55
C to +125C
1/2
Q-28
AD7828TE
*
55
C to +125C
1
E-28A
AD7828UE
*
55
C to +125C
1/2
E-28A
*Available to /883B processing only. Contact our local sales office for military
data sheet. For U.S. Standard Military Drawing (SMD) see DESC Drawing
#5692-88764.
Typical Performance CharacteristicsAD7824/AD7828
REV. F
5
T
A
AMBIENT TEMPERATURE C
3
2
1
100
150
50
t
CRD
CONVERSION
TIME
s
0
50
100
V
DD
= 5V
TPC 1. Conversion Time vs. Temperature
V
REF
V
2.0
1.0
0
0
5
1
LINEARITY ERR
OR LSB
*
2
3
4
1.5
0.5
V
DD
= 5V
T
A
= 25 C
*1LSB =
V
REF
256
TPC 2. Accuracy vs. V
REF
[V
REF
= V
REF
(+) V
REF
()]
INPUT FREQUENCY kHz
36
44
52
5
1
SNR dB
2
3
4
40
48
38
46
42
50
20
30 40 50 70
100
7
10
ENCODE RATE = 400kHz
INPUT SIGNAL = 5V p-p
MEASUREMENT BANDWIDTH = 80kHz
TPC 3. Signal Noise Ratio vs. Input Frequency
T
A
AMBIENT TEMPERATURE C
14
12
10
100
150
50
I
DD
SUPPL
Y CURRENT mA
0
50
100
13
11
9
8
V
DD
= 5.25V
V
DD
= 4.75V
V
DD
= 5V
TPC 4. Power Supply Current vs. Temperature
(Not Including Reference Ladder)
t
P
ns
2.0
1.0
0
300
LINEARITY ERR
OR LSB
1.5
0.5
V
DD
= 5V
V
REF
= 5V
T
A
= 25 C
400
500
600
700
800
900
TPC 5. Accuracy vs. t
P
T
A
AMBIENT TEMPERATURE C
8
4
100
150
50
OUTPUT CURRENT mA
0
50
100
10
6
2
0
I
SOURCE
, V
OUT
= 2.4V
V
DD
= 5V
I
SINK
, V
OUT
= 0.4V
TPC 6. Output Current vs. Temperature
AD7824/AD7828
6
REV. F
OPERATIONAL DIAGRAM
The AD7824 is a 4-channel 8-bit ADC and the AD7828 is an
8-channel 8-bit ADC. Operational diagrams for both of these
devices are shown in Figures 3 and 4. The addition of just a 5 V
reference allows the devices to perform the analog-to-digital function.
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7824
NC = NO CONNECT
AIN4
V
DD
AIN3
NC
AIN2
A0
AIN1
A1
NC
DB7
DB0
DB6
DB1
DB5
DB2
DB4
DB3
CS
RD
RDY
INT
V
REF
(+)
GND
V
REF
()
ANALOG INPUTS
0V TO 5V
P 4LSB
DATA BUS
P CONTROL INPUT
STATUS OUTPUT
P ADDRESS
BUS
P 4MSB
DATA BUS
P CONTROL INPUT
STATUS OUTPUT
5V
5V
Figure 3. AD7824 Operational Diagram
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD7828
NC = NO CONNECT
AIN6
AIN7
AIN5
AIN8
AIN4
V
DD
AIN3
A0
AIN2
A1
AIN1
A2
NC
DB7
DB0
DB6
DB1
DB5
DB2
DB4
DB3
CS
RD
RDY
INT
V
REF
(+)
GND
V
REF
()
ANALOG INPUTS
0V TO 5V
P 4LSB
DATA BUS
P CONTROL INPUT
STATUS OUTPUT
ANALOG INPUTS
0V TO 5V
P ADDRESS
BUS
P 4MSB
DATA BUS
P CONTROL INPUT
STATUS OUTPUT
5V
5V
Figure 4. AD7828 Operational Diagram
CIRCUIT INFORMATION
BASIC DESCRIPTION
The AD7824/AD7828 uses a half-flash conversion technique
whereby two 4-bit flash ADCs are used to achieve an 8-bit result.
Each 4-bit flash ADC contains 15 comparators that compare
the unknown input to a reference ladder to get a 4-bit result.
For a full 8-bit reading to be realized, the upper 4-bit flash, the
most significant (MS) flash, performs a conversion to provide
the four most significant data bits. An internal DAC, driven by
the four MSBs, then recreates an analog approximation of the
input voltage. This analog result is subtracted from the input,
and the difference is converted by the lower flash ADC, the least
significant (LS) flash, to provide the four least significant bits of
the output data. The most significant flash ADC also has one
additional comparator to detect overrange on the analog input.
APPLYING THE AD7824/AD7828
REFERENCE AND INPUT
The two reference inputs on the AD7824/AD7828 are fully differ-
ential and define the zero to full-scale input range of the ADC.
As a result, the span of the analog input voltage for all channels
can easily be varied. By reducing the reference span, V
REF
(+) to
V
REF
(), to less than 5 V, the sensitivity of the converter can be
increased (e.g., if V
REF
= 2 V then 1 LSB = 7.8 mV). The input/
reference arrangement also facilitates ratiometric operation.
This reference flexibility also allows the input channel voltage
span to be offset from zero. The voltage at V
REF
() sets the
input level for all channels, which produces a digital output of
all zeroes. Therefore, although the analog inputs are not them-
selves differential, they have nearly differential input capability
in most measurement applications because of the reference
design. Figures 5 to 7 show some of the configurations that are
possible.
AD7824*
AD7828*
AIN1
GND
V
DD
V
REF
(+)
V
REF
()
47 F
0.1 F
V
IN
()
V
IN
(+)
5V
ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
*
Figure 5. Power Supply as Reference
AD7824*
AD7828*
AIN1
GND
V
DD
V
REF
(+)
V
REF
()
47 F
0.1 F
V
IN
()
V
IN
(+)
5V
ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
*
AD580
0.1 F
10 F
Figure 6. External Reference Using the AD580, Full-Scale
Input is 2.5 V
AD7824*
AD7828*
AIN1
GND
V
DD
V
REF
(+)
V
REF
()
47 F
0.1 F
V
IN
(+)
5V
ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
*
DB7
DB0
DATA
V1
V2
DATA = 256 (FOR ALL CHANNELS)
V
IN
(+)
V1 V2
Figure 7. Input Not Referenced to GND
AD7824/AD7828
REV. F
7
INPUT CURRENT
Due to the novel conversion techniques employed by the AD7824/
AD7828, the analog input behaves somewhat differently than in
conventional devices. The ADC's sampled-data comparators
take varying amounts of input current depending on which cycle
the conversion is in.
The equivalent input circuit of the AD7824/AD7828 is shown
in Figure 8. When a conversion starts (
CS and RD going low),
all input switches close, and the selected input channel is con-
nected to the most significant and least significant comparators.
Therefore, the analog input is simultaneously connected to
31 input capacitors of 1 pF each.
1pF
1pF
15LSB
COMPARATORS
1pF
1pF
16MSB
COMPARATORS
TO LS
LADDER
R
ON
R
ON
R MUX
C
S
12pF
C
S
2pF
R
S
AIN1
TO MS
LADDER
V
IN
AD7824/
AD7828
Figure 8. AD7824/AD7828 Equivalent Input Circuit
The input capacitors must charge to the input voltage through
the on resistance of the analog switches (about 3 k
to 6 k). In
addition, about 14 pF of input stray capacitance must be charged.
The analog input for any channel can be modelled as an RC
network, as shown in Figure 9. As R
S
increases, it takes longer
for the input capacitance to charge.
R
ON
350
R MUX
800
C
S1
12pF
R
S
V
IN
C
S2
2pF
31pF
AIN1
Figure 9. RC Network Model
The time for which the input comparators track the analog input
is approximately 1
s at the start of conversion. Because of input
transients on the analog inputs, it is recommended that a source
impedance no greater than 100
be connected to the analog
inputs. The output impedance of an op amp is equal to the open
loop output impedance divided by the loop gain at the frequency of
interest. It is important that the amplifier driving the AD7824/
AD7828 analog inputs have sufficient loop gain at the input signal
frequency as to make the output impedance low.
Suitable op amps for driving the AD7824/AD7828 are the AD544
or AD644.
INHERENT SAMPLE-HOLD
A major benefit of the AD7824's and AD7828's analog input
structure is its ability to measure a variety of high speed signals
without the help of an external sample-and-hold. In a conven-
tional SAR type converter, regardless of its speed, the input
must remain stable to at least 1/2 LSB throughout the conversion
process if rated accuracy is to be maintained. Consequently, for
many high speed signals, this signal must be externally sampled
and held stationary during the conversion. The AD7824/AD7828
input comparators, by nature of their input switching, inherently
accomplish this sample-and-hold function. Although the conver-
sion time for AD7824/AD7828 is 2
s, the time for which any
selected analog input must be 1/2 LSB stable is much smaller.
The AD7824/AD7828 tracks the selected input channel for
approximately 1
s after conversion start. The value of the analog
input at that instant (1
s from conversion start) is the measured
value. This value is then used in the least significant flash to
generate the lower four bits of data.
SINUSOIDAL INPUTS
The AD7824/AD7828 can measure input signals with slew rates
as high as 157 mV/
s to the rated specifications. This means that
the analog input frequency can be up to 10 kHz without the aid
of an external sample-and-hold. Furthermore, the AD7828 can
measure eight 10 kHz signals without a sample-and-hold. The
Nyquist criterion requires that the sampling rate be twice the
input frequency (i.e., 2
10 kHz). This requires an ideal anti-
aliasing filter with an infinite roll-off. To ease the problem of
antialiasing filter design, the sampling rate is usually much greater
than the Nyquist criterion. The maximum sampling rate (F
MAX
)
for the AD7824/AD7828 can be calculated as follows:
F
t
t
MAX
CRD
P
=
+
1
F
E
E
kHz
MAX
=
+
=
1
2
6
0 5
6
400
.
t
CRD
= AD7824/AD7828 Conversion Time
t
P
= Minimum Delay Between Conversion
This permits a maximum sampling rate of 50 kHz for each of
the eight channels when using the AD7828 and 100 kHz for
each of the four channels when using the AD7824.
AD7824/AD7828
8
REV. F
UNIPOLAR OPERATION
The analog input range for any channel of the AD7824/AD7828 is
0 V to 5 V as shown in the unipolar operational diagram of
Figure 10. Figure 11 shows the designed code transitions that
occur midway between successive integer LSB values (i.e., 1/2 LSB,
3/2 LSB, 5/2 LSB, FS 3/2 LSBs). The output code is natural
binary with 1 LSB = FS/256 = (5/256) V = 19.5 mV.
AD7824*
AD7828*
AIN1
GND
V
DD
V
REF
(+)
V
REF
()
47 F
0.1 F
V
IN
0V TO 5V
5V
ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
*
DB7
DB0
V
REF
5V
Figure 10. AD7824/AD7828 Unipolar 0 V to 5 V Operation
11111111
11111110
11111101
00000011
00000010
00000001
00000000
FULL-SCALE
TRANSITION
OUTPUT CODE
1LSB 2LSB 3LSB
FS 1LSB
FS
0
AIN, INPUT VOLTAGE LSB
1LSB =
FS
256
Figure 11. Ideal Input/Output Transfer Characteristic for
Unipolar 0 V to 5 V Operation
BIPOLAR OPERATION
The circuit of Figure 12 is designed for bipolar operation. An
AD544 op amp conditions the signal input (V
IN
) so that only
positive voltages appear at AIN1. The closed loop transfer func-
tion of the op amp for the resistor values shown is given below:
AIN
V
Volts
IN
1
=
-
(
)
2 5
0 625
.
.
The analog input range is
4 V and the LSB size is 31.25 mV.
The output code is complementary offset binary. The ideal
input/output characteristic is shown in Figure 13.
AD7824*
AD7828*
AIN1
GND
V
DD
V
REF
(+)
V
REF
()
47 F
0.1 F
V
IN
5V
ADDITIONAL PINS OMITTED FOR CLARITY.
ONLY CHANNEL 1 SHOWN.
*
DB7
DB0
5V
AD544
5V
40k
27k
25k
12k
Figure 12. AD7824/AD7828 Bipolar
4 V Operation
AIN, INPUT VOLTAGE LSB
11111111
11111110
00000000
0V
OUTPUT CODE
01111111
01111110
00000010
00000001
10000001
10000000
10000010
11111101
+FS
2
FS
2
+ 1LSB
FS = 8V
1LSB = FS/256
Figure 13. Ideal Input/Output Transfer Characteristic for
4 V Operation
TIMING AND CONTROL
The AD7824/AD7828 has two digital inputs for timing and
control. These are Chip Select (
CS) and Read (RD). A READ
operation brings
CS and RD low, which starts a conversion on
the channel selected by the multiplexer address inputs (see
Table I). There are two modes of operation as outlined by the
timing diagrams of Figures 14 and 15. Mode 0 is designed for
microprocessors that can be driven into a WAIT state. A
READ operation (i.e.,
CS and RD are taken low) starts a con-
version and data is read when conversion is complete. Mode l
does not require microprocessor WAIT states. A READ operation
initiates a conversion and reads the previous conversion results.
Table I. Truth Table for Input Channel Selection
AD7824
AD7828
A1
A0
A2
A1
A0
Channel
0
0
0
0
0
AIN1
0
1
0
0
1
AIN2
1
0
0
1
0
AIN3
1
1
0
1
1
AIN4
1
0
0
AIN5
1
0
1
AIN6
1
1
0
AIN7
1
1
1
AIN8
AD7824/AD7828
REV. F
9
MODE 0
Figure 14 shows the timing diagram for Mode 0 operation. This
mode can only be used for microprocessors that have a WAIT
state facility, whereby a READ instruction cycle can be extended
to accommodate slow memory devices. A READ operation brings
CS and RD low, which starts a conversion. The analog multiplexer
address inputs must remain valid while
CS and RD are low. The
data bus (DB7DB0) remains in the three-state condition until
conversion is complete. There are two converter status outputs on
the AD7824/AD7828, interrupt (
INT) and ready (RDY), which
can be used to drive the microprocessor READY/WAIT input.
The RDY is an open-drain output (no internal pull-up device) that
goes low on the falling edge of
CS and goes high impedance at the
end of conversion when the 8-bit conversion result appears on the
data outputs. If the RDY status is not required, the external
pull-up resistor can be omitted and the RDY output tied to GND.
The
INT goes low when conversion is complete and returns high
on the rising edge of
CS or RD.
MODE 1
Mode 1 operation is designed for applications where the micropro-
cessor is not forced into a WAIT state. A READ operation takes
CS and RD low, which triggers a conversion (see Figure 15). The
multiplexer address inputs are latched on the rising edge of
RD.
Data from the previous conversion is read from the three-state
data outputs (DB7DB0). This data may be disregarded if not
required. Note that the RDY output (open drain output) does
not provide any status information in this mode and must be
connected to GND. At the end of conversion,
INT goes low. A
second READ operation is required to access the new conversion
result. This READ operation latches a new address into the multi-
plexer inputs and starts another conversion.
INT returns high at the
end of the second READ operation, when
CS or RD returns high.
A delay of 2.5
s must be allowed between READ operations.
CS
RD
ANALOG
CHANNEL
ADDRESS
RDY
INT
DATA
t
CSS
t
AS
t
RDY
t
CRD
t
ACC2
t
DH
t
INTH
t
AH
t
AS
t
P
t
CSS
t
CSH
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
HIGH IMPEDANCE
Figure 14. Mode 0 Timing Diagram
CS
RD
ANALOG
CHANNEL
ADDRESS
INT
DATA
t
CSS
t
AS
ADDRESS
VALID
OLD
VALID
ADDRESS
VALID
NEW
VALID
t
CSH
t
AH
t
RD
t
CRD
t
INTH
t
ACC1
t
DH
t
ACC1
t
DH
t
INTH
t
AH
t
AS
t
P
t
CSS
t
RD
t
CSH
Figure 15. Mode 1 Timing Diagram
AD7824/AD7828
10
REV. F
MICROPROCESSOR INTERFACING
The AD7824/AD7828 is designed to interface to microprocessors
as Read Only Memory (ROM). Analog channel selection, con-
version start, and data read operations are controlled by
CS, RD,
and the channel address inputs. These signals are common to
all memory peripheral devices.
Z80 MICROPROCESSOR
Figure 16 shows a typical AD7824/AD7828Z80 interface. The
AD7824/AD7828 is operating in Mode 0. Assume the ADC is
assigned a memory block starting at address C000. The follow-
ing LOAD instruction to any of the addresses listed in Table II
will start a conversion of the selected channel and read the
conversion result.
LD B, (C000)
At the beginning of the instruction cycle when the ADC
address is selected, RDY asserts the WAIT input so that the
Z80 is forced into a WAIT state. At the end of conversion,
RDY returns high and the conversion result is placed in the B
register of the microprocessor.
DATA BUS
ADDRESS BUS
ADDRESS
DECODE
EN
5V
5k
A0
A1
A2
Z80
AD7824*
AD7828*
A15
A0
MREQ
WAIT
RD
D7
D0
CS
RDY
RD
DB7
DB0
A0
A1
A2**
LINEAR CIRCUITRY OMITTED FOR CLARITY.
FOR THE AD7828 ONLY
**
*
Figure 16. AD7824/AD7828Z80 lnterface
Table II. Address Channel Selection
AD7824
AD7828
Address
Channel
Channel
C000
1
1
C001
2
2
C002
3
3
C003
4
4
C004
5
C005
6
C006
7
C007
8
MC68000 MICROPROCESSOR
Figure 17 shows an MC68000 interface. The AD7824/AD7828
is operating in Mode 0. Assume the ADC is again assigned a
memory block starting at address C000. A MOVE instruction
to any of the addresses in Table II starts a conversion and reads
the conversion result.
MOVE
B $C000, D0
Once conversion has begun, the MC68000 inserts WAIT states
until INT goes low, asserting DTACK at the end of conversion.
The microprocessor then places the conversion results into the
D0 register.
DATA BUS
ADDRESS BUS
ADDRESS
DECODE
EN
5V
5k
A0
A1
A2
AD7824*
AD7828*
A23
A1
D7
D0
CS
RDY
RD
DB7
DB0
A0
A1
A2**
CLR
D
CK
Q
7474
DTACK
R/
W
AS
MC68000
LINEAR CIRCUITRY OMITTED FOR CLARITY.
FOR THE AD7828 ONLY
**
*
Figure 17. AD7824/AD7828MC68000 Interface
TMS32010 MICROCOMPUTER
A TMS32010 interface is shown in Figure 18. The AD7824/
AD7828 is operating in Mode 1 (i.e., no
P WAIT states). The
ADC is mapped at a port address. The following I/O instruction
starts a conversion and reads the previous conversion result into
the accumulator.
IN, A PA (PA = PORT ADDRESS)
The port address (000 to 111) selects the analog channel to be
converted. When conversion is complete, a second I/O instruc-
tion (IN, A PA) reads the up-to-date data into the accumulator
and starts another conversion. A delay of 2.5
s must be allowed
between conversions.
DATA BUS
A2**
AD7824*
AD7828*
A1
A0
CS
RD
DB7
DB0
PA2
PA1
PA0
MEN
DEN
D7
D0
TMS32010
LINEAR CIRCUITRY OMITTED FOR CLARITY.
FOR THE AD7828 ONLY
**
*
Figure 18. AD7824/AD7828TMS32010 Interface
AD7824/AD7828
REV. F
11
OUTLINE DIMENSIONS
24-Lead Plastic Dual-in-Line Package [PDIP]
(N-24)
Dimensions shown in inches and (millimeters)
24
1
12
13
1.185 (30.01)
1.165 (29.59)
1.145 (29.08)
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
SEATING
PLANE
0.015 (0.38) MIN
0.180
(4.57)
MAX
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.100
(2.54)
BSC
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AG
BAND-PASS
FILTER 1
BAND-PASS
FILTER 2
BAND-PASS
FILTER 7
BAND-PASS
FILTER 8
AMP
SPEECH
INPUT
AIN1
AIN2
AIN7
AIN8
V
DD
V
REF
()
V
REF
(+)
5V
GND
5V
CS
RD
DB7
DB0
A2
A1
A0
DATA
AD7828
Figure 19. Speech Analysis Using Real-Time Filtering
V
DD
GND
5V
CS
RD
AIN1
AIN2
AIN3
AIN4
V
REF
(+)
V
REF
()
AD7824
INT
DB7
DB0
A1
A0
WR
DB7
DB0
A1
A0
V
OUT
A
AGND
DGND
V
OUT
B
V
OUT
C
V
OUT
D
AD7226
V
SS
V
DD
15V
V
O
1
V
O
2
V
O
3
V
O
4
SAMPLE
PULSE
V
REF
10V
Figure 20. 4-Channel Fast Infinite Sample-and-Hold
28-Lead Plastic Dual-in-Line Package [PDIP]
(N-28)
Dimensions shown in inches and (millimeters)
0.195 (4.95)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.625 (15.87)
0.600 (15.24)
28
1
14
15
0.580 (14.73)
0.485 (12.32)
1.565 (39.7)
1.380 (35.1)
SEATING
PLANE
0.250 (6.35)
MAX
0.022 (0.558)
0.014 (0.356)
0.200 (5.05)
0.115 (2.93)
0.015 (0.39)
MIN
0.100 (2.54)
BSC
0.70 (1.77)
0.30 (0.77)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-011AB
AD7824/AD7828
12
REV. F
OUTLINE DIMENSIONS
24-Lead Standard Small Outline Package [SOIC]
Wide Body
(R-24)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AD
0.32 (0.0126)
0.23 (0.0091)
8
0
0.75 (0.0295)
0.25 (0.0098)
45
1.27 (0.0500)
0.40 (0.0157)
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.020)
0.33 (0.013)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
24
13
12
1
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
15.60 (0.6142)
15.20 (0.5984)
COPLANARITY
0.10
28-Lead Standard Small Outline Package [SOIC]
Wide Body
(R-28)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AE
0.32 (0.0126)
0.23 (0.0091)
8
0
0.75 (0.0295)
0.25 (0.0098)
45
1.27 (0.0500)
0.40 (0.0157)
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.33 (0.0130)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
28
15
14
1
18.10 (0.7126)
17.70 (0.6969)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
COPLANARITY
0.10
AD7824/AD7828
REV. F
13
OUTLINE DIMENSIONS
28-Lead Ceramic DIP - Glass Hermetic Seal [CERDIP]
(Q-28)
Dimensions shown in inches and (millimeters)
28
1
14
15
0.610 (15.49)
0.500 (12.70)
PIN 1
0.005 (0.13)
MIN
0.100 (2.54)
MAX
15
0
0.620 (15.75)
0.590 (14.99)
0.018 (0.46)
0.008 (0.20)
SEATING
PLANE
0.225(5.72)
MAX
1.490 (37.85) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
MIN
0.026 (0.66)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
24-Lead Ceramic DIP - Glass Hermetic Seal [CERDIP]
(Q-24)
Dimensions shown in inches and (millimeters)
24
1
12
13
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13)
MIN
0.098 (2.49)
MAX
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
1.280 (32.51) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Terminal Ceramic Leaded Chip Carrier [LCC]
(E-28A)
Dimensions shown in inches and (millimeters)
1
28
5
11
18
BOTTOM
VIEW
19
25
26
4
12
0.15 (3.81)
REF
0.075
(1.91)
REF
0.028 (0.71)
0.022 (0.56)
0.300 (7.62)
REF
0.055 (1.40)
0.045 (1.14)
0.075 (1.91)
REF
0.020 (0.51)
MIN
0.05 (1.27)
BSC
0.095 (2.41)
0.075 (1.90)
0.458 (11.63)
0.442 (11.23)
SQ
0.458
(11.63)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
AD7824/AD7828
14
REV. F
OUTLINE DIMENSIONS
28-Lead Plastic Leaded Chip Carrier [PLCC]
(P-28A)
Dimensions shown in inches and (millimeters)
4
5
26
25
11
12
19
18
TOP VIEW
(PINS DOWN)
SQ
0.456 (11.582)
0.450 (11.430)
0.050
(1.27)
BSC
0.048 (1.22)
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.495 (12.57)
0.485 (12.32)
SQ
0.021 (0.53)
0.013 (0.33)
0.430 (10.9)
0.390 (9.9)
0.032 (0.81)
0.026 (0.66)
0.120 (3.05)
0.090 (2.29)
0.056 (1.42)
0.042 (1.07)
0.020 (0.51)
MIN
0.180 (4.57)
0.165 (4.19)
BOTTOM
VIEW
(PINS UP)
0.040 (1.02)
0.025 (0.64)
COMPLIANT TO JEDEC STANDARDS MO-047AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
0.25
0.09
0.95
0.75
0.55
8
4
0
0.05
MIN
1.85
1.75
1.65
2.00 MAX
0.38
0.22
SEATING
PLANE
0.65
BSC
0.10
COPLANARITY
28
15
14
1
10.50
10.20
9.90
5.60
5.30
5.00
8.20
7.80
7.40
COMPLIANT TO JEDEC STANDARDS MO-150AH
AD7824/AD7828
REV. F
15
Revision History
Location
Page
1/0
3--Data Sheet changed from REV. E to REV. F.
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to DIP/SOIC/SSOP, LCCC, AND PLCC Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edit to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to Circuit Information Basic Description section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to Input Current section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edit to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edit to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4/02--Data Sheet changed from REV. D to REV. E.
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
C0132301/03 (F)
PRINTED IN U.S.A.
16
PDF 
ZIP