REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

MOS

Complete 12-Bit Multiplying DAC

AD7845

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Voltage Output Multiplying DAC

The AD7845 is the first DAC which has a full 4-quadrant
multiplying capability and an output amplifier on chip. All
specifications include amplifier performance.

2. Matched Application Resistors

Three application resistors provide an easy facility for gain
ranging, voltage offsetting, etc.

3. Space Saving

The AD7845 saves space in two ways. The integration of the
output amplifier on chip means that chip count is reduced.
The part is housed in skinny 24-lead 0.3" DIP, 28-terminal
LCC and PLCC and 24-terminal SOIC packages.

GENERAL DESCRIPTION

The AD7845 is the industry's first 4-quadrant multiplying D/A
converter with an on-chip amplifier. It is fabricated on the
LC

MOS process, which allows precision linear components

and digital circuitry to be implemented on the same chip.

The 12 data inputs drive latches which are controlled by stan-
dard

CS and WR signals, making microprocessor interfacing

simple. For stand-alone operation, the

CS and WR inputs can

be tied to ground, making all latches transparent. All digital
inputs are TTL and 5 V CMOS compatible.

The output amplifier can supply

10 V into a 2 k

load. It is

internally compensated, and its input offset voltage is low due to
laser trimming at wafer level. For normal operation, R

is tied

to V

OUT

, but the user may alternatively choose R

, R

or R

scale the output voltage range.

FEATURES
12-Bit CMOS MDAC with Output Amplifier
4-Quadrant Multiplication
Guaranteed Monotonic (T

MIN

to T

MAX

)

Space-Saving 0.3" DIPs and 24- or 28-Terminal Surface

Mount Packages

Application Resistors On Chip for Gain Ranging, etc.
Low Power LC

MOS

APPLICATIONS
Automatic Test Equipment
Digital Attenuators
Programmable Power Supplies
Programmable Gain Amplifiers
Digital-to-420 mA Converters

= +15 V, 5%, V

= 15 V, 5%, V

REF

= +10 V, AGND = DGND = O V,

OUT

connected to R

. V

OUT

load = 2 k , 100 pF. All specifications T

MIN

to T

MAX

unless otherwise noted.)

REV. B

AD7845SPECIFICATIONS

Parameter

J Version

K Version

A Version

B Version

S Version

T Version

Units

Test Conditions/Comments

ACCURACY

Resolution

Bits

1 LSB =

REF

= 2.4 mV

Relative Accuracy

at +25

1/2

LSB max

All Grades Are Guaranteed

MIN

to T

MAX

3/4

LSB max

Monotonic over Temperature

Differential Nonlinearity

LSB max

DAC Register Loaded with

Zero Code Offset Error

All 0s.

at +25

mV max

MIN

to T

MAX

mV max

Offset Temperature Coefficient;

(

Offset/

Temperature)

C typ

Gain Error

LSB max

, V

OUT

Connected

LSB max

, V

OUT

Connected, V

REF

= +5 V

LSB max

, V

OUT

Connected, V

REF

= +5 V

LSB max

, V

OUT

Connected, V

REF

= +2.5 V

Gain Temperature Coefficient;

(

Gain/

Temperature)

ppm of FSR/

C R

, V

OUT

Connected

typ

REFERENCE INPUT

Input Resistance, Pin 17

min

Typical Input Resistance = 12 k

max

APPLICATION RESISTOR

RATIO MATCHING

0.5

0 5

% max

Matching Between R

, R

DIGITAL INPUTS

(Input High Voltage)

2.4

V min

(Input Low Voltage)

0.8

V max

(Input Current)

A max

Digital Inputs at 0 V and V

(Input Capacitance)

pF max

POWER SUPPLY

Range

14.25/15.75

V min/V max

Range

14.25/15.75 14.25/15.75 14.25/15.75 14.25/15.75

14.25/15.75 14.25/15.75

V min/V max

Power Supply Rejection

Gain/

0.01

% per % max

= +15 V

5%, V

REF

= 10 V

Gain/

0.01

% per % max

= 15 V

5%.

mA max

OUT

Unloaded

mA max

OUT

Unloaded

AC PERFORMANCE CHARACTERISTICS

These characteristics are included for Design Guidance and are not subject to test.

DYNAMIC PERFORMANCE

Output Voltage Settling Time

s max

To 0.01% of Full-Scale Range
V

OUT

Load = 2 k

, 100 pF.

DAC Register Alternately Loaded
with All 0s and All 1s. Typically
2.5

s at 25

Slew Rate

s typ

OUT

Load = 2 k

, 100 pF.

Digital-to-Analog

nVs typ

Measured with V

REF

= 0 V.

Glitch Impulse

DAC Register Alternately Loaded
with All 0s and All 1s.

Multiplying Feedthrough

mV p-p typ

REF

10 V, 10 kHz Sine Wave

Error

DAC Register Loaded with All 0s.

Unity Gain Small Signal

Bandwidth

600

kHz typ

OUT

, R

Connected. DAC Loaded

with All 1s V

REF

= 100 mV p-p

Sine Wave.

Full Power Bandwidth

175

kHz typ

OUT

, R

Connected. DAC Loaded

with All 1s. V

REF

= 20 V p-p

Sine Wave. R

= 2 k

Total Harmonic Distortion

dB typ

REF

= 6 V rms, 1 kHz Sine Wave.

OUTPUT CHARACTERISTICS

Open Loop Gain

dB min

OUT

, R

Not Connected

OUT

10 V, R

= 2 k

Output Voltage Swing

V min

= 2 k

, C

= 100 pF

Output Resistance

0.2

typ

, V

OUT

Connected,

Short Circuit Current @ +25

mA typ

OUT

Shorted to AGND

Output Noise Voltage

Includes Noise Due to Output

(0.1 Hz to 10 Hz) @ +25

V rms typ

Amplifier and Johnson Noise

f = 10 Hz

250

nV/

Hz typ

of R

f = 100 Hz

100

nV/

Hz typ

f = 1 kHz

nV/

Hz typ

f = 10 kHz

nV/

Hz typ

f = 100 kHz

nV/

Hz typ

NOTES

Temperature ranges are as follows: J, K Versions: 0

C to +70

C; A, B Versions: 40

C to +85

C; S, T Versions: 55

C to +125

Guaranteed by design and characterization, not production tested.

The metal lid on the ceramic D-24A package is connected to Pin 12 (DGND).

The device is functional with a power supply of

12 V.

Minimum specified load resistance is 2 k

Specifications subject to change without notice.

AD7845

REV. B

Limit at T

MIN

to T

MAX

Parameter

(All Versions)

Units

Test Conditions/Comments

ns min

Chip Select to Write Setup Time

ns min

Chip Select to Write Hold Time

ns min

Write Pulsewidth

ns min

Data Setup Time

ns min

Data Hold Time

NOTES

Guaranteed by design and characterization, not production tested.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

= +15 V, 5%. V

= 15 V, 5%. V

REF

= +10 V. AGND = DGND = O V.)

ORDERING GUIDE

Relative

Temperature

Accuracy

Package

Model

Range

@ +25 C

Option

AD7845JN

C to +70

1 LSB

N-24

AD7845KN

C to +70

1/2 LSB

N-24

AD7845JP

C to +70

1 LSB

P-28A

AD7845KP

C to +70

1/2 LSB

P-28A

AD7845JR

C to +70

1 LSB

R-24

AD7845KR

C to +70

1/2 LSB

R-24

AD7845AQ

C to +85

1 LSB

Q-24

AD7845BQ

C to +85

1/2 LSB

Q-24

AD7845AR

C to +85

1 LSB

R-24

AD7845BR

C to +85

1/2 LSB

R-24

AD7845SQ/883B

C to +125

1 LSB

Q-24

AD7845TQ/883B

C to +125

1/2 LSB

Q-24

AD7845SE/883B

C to +125

1 LSB

E-28A

NOTES

Analog Devices reserves the right to ship either ceramic (D-24A) or cerdip

(Q-24) hermetic packages.

To order MIL-STD-883, Class B processed parts, add /883B to part number.

E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip

Carrier; Q = Cerdip; R = SOIC.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7845 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

Operating Temperature Range

Commercial (J, K Versions) . . . . . . . . . . . . . 0

C to +70

Industrial (A, B Versions) . . . . . . . . . . . . 40

C to +85

Extended (S, T Versions) . . . . . . . . . . . . 55

C to +125

Storage Temperature Range . . . . . . . . . . . 65

C to +150

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect device
reliability. Only one Absolute Maximum Rating may be applied at any one time.

OUT

may be shorted to AGND provided that the power dissipation of the

package is not exceeded.

DATA

NOTES
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM
10% TO 90% OF +5V. t

= t

= 20ns.

2. TIMING MEASUREMENT REFERENCE LEVEL IS

+ V

Figure 1. AD7845 Timing Diagram

ABSOLUTE MAXIMUM RATINGS

= +25

C unless otherwise stated)

to DGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +17 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 17 V

REF

to AGND . . . . . . . . . . . . . . . . V

+ 0.3 V, V

0.3 V

RFB

to AGND . . . . . . . . . . . . . . . . V

+ 0.3 V, V

0.3 V

to AGND . . . . . . . . . . . . . . . . . V

+ 0.3 V, V

0.3 V

to AGND . . . . . . . . . . . . . . . . . V

+ 0.3 V, V

0.3 V

to AGND . . . . . . . . . . . . . . . . . V

+ 0.3 V, V

0.3 V

OUT

to AGND

. . . . . . . . . . . . . . . V

+ 0.3 V, V

0.3 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, V

Digital Input Voltage to DGND . . . . . 0.3 V to V

+ 0.3 V

Power Dissipation (Any Package)

To +75

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 mW

Derates above +75

C . . . . . . . . . . . . . . . . . . . . . 10 mW/

WARNING!

ESD SENSITIVE DEVICE

AD7845

REV. B

PIN CONFIGURATIONS

LCC

PLCC

DIP, SOIC

DIGITAL-TO-ANALOG GLITCH IMPULSE

This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is nor-
mally specified as the area of the glitch in either pA-secs or
nV-secs depending upon whether the glitch is measured as a
current or voltage. The measurement takes place with V

REF

AGND.

DIGITAL FEEDTHROUGH

When the DAC is not selected (i.e.,

CS is high) high frequency

logic activity on the device digital inputs is capacitively coupled
through the device to show up as noise on the V

OUT

pin. This

noise is digital feedthrough.

MULTIPLYING FEEDTHROUGH ERROR

This is ac error due to capacitive feedthrough from the V

REF

terminal to V

OUT

when the DAC is loaded with all 0s.

OPEN-LOOP GAIN

Open-loop gain is defined as the ratio of a change of output
voltage to the voltage applied at the V

REF

pin with all 1s loaded

in the DAC. It is specified at dc.

UNITY GAIN SMALL SIGNAL BANDWIDTH

This is the frequency at which the magnitude of the small signal
voltage gain of the output amplifier is 3 dB below unity. The
device is operated as a closed-loop unity gain inverter (i.e.,
DAC is loaded with all 1s).

OUTPUT RESISTANCE

This is the effective output source resistance.

FULL POWER BANDWIDTH

Full power bandwidth is specified as the maximum frequency, at
unity closed-loop gain, for which a sinusoidal input signal will
produce full output at rated load without exceeding a distortion
level of 3%.

TERMINOLOGY

LEAST SIGNIFICANT BIT

This is the analog weighting of 1 bit of the digital word in a

DAC. For the AD7845, 1 LSB =

REF

RELATIVE ACCURACY

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for both endpoints (i.e., offset and gain error are ad-
justed out) and is normally expressed in least significant bits or
as a percentage of full-scale range.

DIFFERENTIAL NONLINEARITY

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of +1 LSB max over
the operating temperature range ensures monotonicity.

GAIN ERROR

Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer. See Figure 13.

ZERO CODE OFFSET ERROR

This is the error present at the device output with all 0s loaded
in the DAC. It is due to the op amp input offset voltage and
bias current and the DAC leakage current.

TOTAL HARMONIC DISTORTION

This is the ratio of the root-mean-square (rms) sum of the har-
monics to the fundamental, expressed in dBs.

OUTPUT NOISE

This is the noise due to the white noise of the DAC and the
input noise of the amplifier.

AD7845

REV. B

PIN FUNCTION DESCRIPTION (DIP)

Pin

Mnemonic

Description

OUT

Voltage Output Terminal

2-11

DB11DB2

Data Bit 11 (MSB) to Data Bit 2

DGND

Digital Ground. The metal lid on the ceramic package is connected to this pin

13-14

DB1DB0

Data Bit 1 to Data Bit 0 (LSB)

Write Input. Active low

Chip Select Input. Active low

REF

Reference Input Voltage which can be an ac or dc signal

AGND

Analog Ground. This is the reference point for external analog circuitry

Negative power supply for the output amplifier (nominal 12 V to +15 V)

Positive power supply (nominal +12 V to +15 V)

Application resistor. R

= 4 R

Application resistor. R

= 2 R

Application resistor. R

= 2 R

Feedback resistor in the DAC. For normal operation this is connected to V

OUT

CIRCUIT INFORMATION
Digital Section

Figure 11 is a simplified circuit diagram of the AD7845 input
control logic. When

CS and WR are both low, the DAC latch is

loaded with the data on the data inputs. All the digital inputs
are TTL, HCMOS and +5 V CMOS compatible, facilitating
easy microprocessor interfacing. All digital inputs incorporate
standard protection circuitry.

Figure 11. AD7845 Input Control Logic

D/A Section

Figure 12 shows a simplified circuit diagram for the AD7845
D/A section and output amplifier.

A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A-C. The
remaining 10 bits drive the switches (S0S9) in a standard R-2R
ladder configuration.

REF

SHOWN FOR ALL 1s ON DAC

OUT

AGND

Figure 12. Simplified Circuit Diagram for the AD7845 D/A
Section

Each of the switches AC steers 1/4 of the total reference cur-
rent with the remaining 1/4 passing through the R-2R section.

An output amplifier and feedback resistor perform the current-
to-voltage conversion giving

OUT

= D

REF

where D is the fractional representation of the digital word. (D
can be set from 0 to 4095/4096.)

The amplifier can maintain

10 V across a 2 k

load. It is inter-

nally compensated and settles to 0.01% FSR (1/2 LSB) in less
than 5

s. The input offset voltage is laser trimmed at wafer

level. The amplifier slew rate is typically 11 V/

s, and the unity

gain small signal bandwidth is 600 kHz. There are three extra
on-chip resistors (R

, R

) connected to the amplifier invert-

ing terminal. These are useful in a number of applications in-
cluding offset adjustment and gain ranging.

AD7845

REV. B

UNIPOLAR BINARY OPERATION

Figure 13 shows the AD7845 connected for unipolar binary
operation. When V

is an ac signal, the circuit performs

2-quadrant multiplication. The code table for Figure 13 is given
in Table I.

Figure 13. Unipolar Binary Operation

Table I. Unipolar Binary Code Table for AD7845

Binary Number In
DAC Register

Analog Output, V

OUT

MSB

LSB

1111

4095

4096

1000

0000

2048

4096

= 1/2 V

0000

0001

4096

0000

0 V

OFFSET AND GAIN ADJUSTMENT FOR FIGURE 13

Zero Offset Adjustment

1. Load DAC with all 0s.
2. Trim R3 until V

OUT

= 0 V.

Gain Adjustment

1. Load DAC with all 1s.

2. Trim R1 so that V

OUT

= V

4095

4096

In fixed reference applications, full scale can also be adjusted by
omitting R1 and R2 and trimming the reference voltage magni-
tude. For high temperature applications, resistors and potenti-
ometers should have a low temperature coefficient.

BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)

The recommended circuit for bipolar operation is shown in
Figure 14. Offset binary coding is used.

The offset specification of this circuit is determined by the
matching of internal resistors R

and R

and by the zero code

offset error of the device. Gain error may be adjusted by varying
the ratio of R1 and R2.

To use this circuit without trimming and keep within the gain
error specifications, resistors R1 and R2 should be ratio
matched to 0.01%.

The code table for Figure 14 is given in Table II.

Figure 14. Bipolar Offset Binary Operation

Table II. Bipolar Code Table for Offset Binary Circuit of
Figure 14

Binary Number In
DAC Register

Analog Output, V

OUT

MSB

LSB

1111

2047

2048

1000

0000

0001

2048

1000

0000

0 V

0111

1111

2048

0000

2048

= V

AD7845

REV. B

APPLI

CATION

S CIRCUITS

PROGRAMMABLE GAIN AMPLIFIER (PGA)

The AD7845 performs a PGA function when connected as in
Figure 15. In this configuration, the R-2R ladder is connected
in the amplifier feedback loop. R

is the amplifier input resis-

tor. As the code decreases, the R-2R ladder resistance increases
and so the gain increases.

OUT

= V

DAC

0 to

4095

4096

= V

DAC

, since R

= R

DAC

Figure 15. AD7845 Connected as PGA

As the programmed gain increases, the error and noise also
increase. For this reason, the maximum gain should be limited
to 256. Table III shows gain versus code.

Note that instead of using R

as the input resistor, it is also

possible to use combinations of the other application resistors,
R

, R

and R

. For instance, if R

is used instead of R

, the

gain range for the same codes of Table II now goes from l/2
to 128.

Table III. Gain and Error vs. Input Code for Figure 15

Digital Inputs

Gain

Error (%)

1111

4096/4095

0.04

1000

0000

0.07

0100

0000

0.13

0010

0000

0.26

0001

0000

0.51

0000

1000

0000

1.02

0000

0100

0000

2.0

0000

0010

0000

128

4.0

0000

0001

0000

256

8.0

PROGRAMMABLE CURRENT SOURCES

The AD7845 is ideal for designing programmable current
sources using a minimum of external components. Figures 16
and 17 are examples. The circuit of Figure 16 drives a program-
mable current I

into a load referenced to a negative supply.

Figure 17 shows the circuit for sinking a programmable current,
I

. The same set of circuit equations apply for both diagrams.

= I

+ I

DAC

0 to

4095

4096

DAC

, since R

= R

DAC

Note that by making R1 much smaller than R

DAC

, the circuit

becomes insensitive to both the absolute value of R

DAC

and its

temperature variations. Now, the only resistor determining load
current I

is the sense resistor R1.

If R1 = 100

, then the programming range is 0 mA to 100 mA,

and the resolution is 0.024 mA.

Figure 16. Programmable Current Source

AD7845

REV. B

Figure 17. Programmable Current Sink

420 mA CURRENT LOOP

The AD7845 provides an excellent way of making a 4-20 mA
current loop circuit. This is basically a variation of the circuits
in Figures 16 and 17 and is shown in Figure 18. The application
resistor R

(Value 4R) produces the effective 4 mA offset.

= I

+ I

Since I

> I

156

2.5

DAC

156

and since R

DAC

2.5

1000

156

= [4 + (16

D)]mA, where D goes from 0 to 1 with

Digital Code

When D = 0 (Code of all 0s):

= 4 mA

When D = 1 (Code of all 1s):

= 20 mA

The above circuit succeeds in significantly reducing the circuit
component count. Both the on-chip output amplifier and the
application resistor R

contribute to this.

Figure 18. 420 mA Current Loop

APPLICATION HINTS

General Ground Management: AC or transient voltages
between AGND and DGND can cause noise injection into the
analog output. The simplest method of ensuring that voltages at
AGND and DGND are equal is to tie AGND and DGND
together at the AD7845. In more complex systems where the
AGND and DGND intertie is on the backplane, it is recom-
mended that two diodes be connected in inverse parallel be-
tween the AD7845 AGND and DGND pins (IN914 or
equivalent).

Digital Glitches: When a new digital word is written into the
DAC, it results in a change of voltage applied to some of the
DAC switch gates. This voltage change is coupled across the
switch stray capacitance and appears as an impulse on the cur-
rent output bus of the DAC. In the AD7845, impulses on this
bus are converted to a voltage by R

and the output amplifier.

The output voltage glitch energy is specified as the area of the
resulting spike in nV-seconds. It is measured with V

REF

con-

nected to analog ground and for a zero to full-scale input code
transition. Since microprocessor based systems generally have
noisy grounds which couple into the power supplies, the
AD7845 V

and V

terminals should be decoupled to signal

ground.

Temperature Coefficients: The gain temperature coefficient
of the AD7845 has a maximum value of 5 ppm/

C. This corre-

sponds to worst case gain shift of 2 LSBs over a 100

C tem-

perature range. When trim resistors R1 and R2 in Figure 13
are used to adjust full-scale range, the temperature coefficient
of R1 and R2 must be taken into account. The offset tempera-
ture coefficient is 5 ppm of FSR/

C maximum. This corre-

sponds to a worst case offset shift of 2 LSBs over a 100

temperature range.

The reader is referred to Analog Devices Application Note
"Gain Error and Gain Temperature Coefficient of CMOS Mul-
tiplying DACs," Publication Number E630C-5-3/86.

AD7845

REV. B

8-BIT MICROPROCESSOR SYSTEMS

Figure 22 shows an interface circuit for the AD7845 to the
8085A 8-bit microprocessor. The software routine to load data
to the device is given in Table IV. Note that the transfer of the
12 bits of data requires two write operations. The first of these
loads the 4 MSBs into the 7475 latch. The second write opera-
tion loads the 8 LSBs plus the 4 MSBs (which are held by the
latch) into the DAC.

Figure 22. 8085A Interface

Table IV. Subroutine Listing for Figure 22

2000 LOAD DAC: LXI

H,#3000

The H,L register pair
are loaded with latch
address 3000.

MVI

A,#"MS"

Load the 4 MSBs of
data into accumulator.

MOV

M,A

Transfer data from
accumulator to latch.

INR

Increment H,L pair to
AD7845 address.

MVI

A,#"LS"

Load the 8 LSBs of
data into accumulator.

MOV

M,A

Transfer data from
accumulator to DAC.

RET

End of routine.

MICROPROCESSOR INTERFACING
16-BIT MICROPROCESSOR SYSTEMS

Figures 19, 20 and 21 show how the AD7845 interfaces to
three popular 16-bit microprocessor systems. These are the
MC68000, 8086 and the TM32010. The AD7845 is treated as
a memory-mapped peripheral to the processors. In each case, a
write instruction loads the AD7845 with the appropriate data.
The particular instructions used are as follows:

MC68000:

MOVE

8086:

MOV

TMS32010: OUT

Figure 19. AD7845 to MC68000 Interface

Figure 20. AD7845 to 8086 Interface

Figure 21. TMS32010

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