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Электронный компонент: AD8008ARM-REEL7

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REV. C
a
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
AD8007/AD8008
Ultralow Distortion
High Speed Amplifiers
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
CONNECTION DIAGRAMS
GENERAL DESCRIPTION
The AD8007 (single) and AD8008 (dual) are high perfor-
mance current feedback amplifiers with ultralow distortion
and noise. Unlike other high performance amplifiers, the low
price and low quiescent current allow these amplifiers to be
used in a wide range of applications. ADI's proprietary second
generation eXtra-Fast Complementary Bipolar (XFCB)
process enables such high performance amplifiers with low
power consumption.
The AD8007/AD8008 have 650 MHz bandwidth, 2.7 nV/
Hz
voltage noise, 83 dB SFDR @ 20 MHz (AD8007), and 77 dBc
SFDR @ 20 MHz (AD8008).
With the wide supply voltage range (5 V to 12 V) and wide band-
width, the AD8007/AD8008 are designed to work in a variety of
applications. The AD8007/AD8008 amplifiers have a low power
supply current of 9 mA/amplifier.
The AD8007 is available in a tiny SC70 package as well as a
standard 8-lead SOIC. The dual AD8008 is available in both
FEATURES
Extremely Low Distortion
Second Harmonic
88 dBc @ 5 MHz
83 dBc @ 20 MHz (AD8007)
77 dBc @ 20 MHz (AD8008)
Third Harmonic
101 dBc @ 5 MHz
92 dBc @ 20 MHz (AD8007)
98 dBc @ 20 MHz (AD8008)
High Speed
650 MHz, 3 dB Bandwidth (G = +1)
1000 V/ s Slew Rate
Low Noise
2.7 nV/
Hz Input Voltage Noise
22.5 pA/
Hz Input Inverting Current Noise
Low Power
9 mA/Amplifier Typ Supply Current
Wide Supply Voltage Range
5 V to 12 V
0.5 mV Typical Input Offset Voltage
Small Packaging
SOIC-8, MSOP, and SC70 Packages Available
APPLICATIONS
Instrumentation
IF and Baseband Amplifiers
Filters
A/D Drivers
DAC Buffers
8-lead SOIC and 8-lead MSOP packages. These amplifiers are
rated to work over the industrial temperature range of 40
C
to +85
C.
FREQUENCY MHz
30
40
110
1
100
10
DIST
OR
TION dBc
70
80
90
100
50
60
2ND
3RD
G = +2
R
L
= 150
V
S
= 5V
V
OUT
= 2V p-p
Figure 1. AD8007 Second and Third Harmonic
Distortion vs. Frequency
SOIC (RN-8)
SC70 (KS-5)
8
7
6
5
1
2
3
4
NC = NO CONNECT
NC
IN
+IN
NC
+V
S
V
OUT
NC
V
S
AD8007
(Top View)
5
1
2
3
IN
+IN
+V
S
V
OUT
V
S
4
AD8007
(Top View)
SOIC (RN)
and MSOP (RM)
1
V
OUT1
IN1
+IN1
V
S
+V
S
V
OUT2
IN2
+IN2
8
2
7
3
6
4
5
AD8008
(Top View)
REV. C
2
AD8007/AD8008SPECIFICATIONS
V
S
= 5 V
(@ T
A
= 25 C, R
S
= 200 , R
L
= 150 , R
F
= 499 , Gain = +2, unless otherwise noted.)
AD8007/AD8008
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Bandwidth
G = +1, V
O
= 0.2 V p-p, R
L
= 1 k
540
650
MHz
G = +1, V
O
= 0.2 V p-p, R
L
= 150
250
500
MHz
G = +2, V
O
= 0.2 V p-p, R
L
= 150
180
230
MHz
G = +1, V
O
= 2 V p-p, R
L
= 1 k
200
235
MHz
Bandwidth for 0.1 dB Flatness
V
O
= 0.2 V p-p, G = +2, R
L
= 150
50
90
MHz
Overdrive Recovery Time
2.5 V Input Step, G = +2, R
L
= 1 k
30
ns
Slew Rate
G = +1, V
O
= 2 V Step
900
1000
V/
s
Settling Time to 0.1%
G = +2, V
O
= 2 V Step
18
ns
Settling Time to 0.01%
G = +2, V
O
= 2 V Step
35
ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic
f
C
= 5 MHz, V
O
= 2 V p-p
88
dBc
f
C
= 20 MHz, V
O
= 2 V p-p
83/77
dBc
Third Harmonic
f
C
= 5 MHz, V
O
= 2 V p-p
101
dBc
f
C
= 20 MHz, V
O
= 2 V p-p
92/98
dBc
IMD
f
C
= 19.5 MHz to 20.5 MHz, R
L
= 1 k
,
V
O
= 2 V p-p
77
dBc
Third Order Intercept
f
C
= 5 MHz, R
L
= 1 k
43.0/42.5
dBm
f
C
= 20 MHz, R
L
= 1 k
42.5
dBm
Crosstalk (AD8008)
f = 5 MHz, G = +2
68
dB
Input Voltage Noise
f = 100 kHz
2.7
nV/
Hz
Input Current Noise
Input, f = 100 kHz
22.5
pA/
Hz
+Input, f = 100 kHz
2
pA/
Hz
Differential Gain Error
NTSC, G = +2, R
L
= 150
0.015
%
Differential Phase Error
NTSC, G = +2, R
L
= 150
0.010
Degree
DC PERFORMANCE
Input Offset Voltage
0.5
4
mV
Input Offset Voltage Drift
3
V/C
Input Bias Current
+Input
4
8
A
Input
0.4
6
A
Input Bias Current Drift
+Input
16
nA/
C
Input
9
nA/
C
Transimpedance
V
O
=
2.5 V, R
L
= 1 k
1.0
1.5
M
R
L
= 150
0.4
0.8
M
INPUT CHARACTERISTICS
Input Resistance
+Input
4
M
Input Capacitance
+Input
1
pF
Input Common-Mode Voltage Range
3.9 to +3.9
V
Common-Mode Rejection Ratio
V
CM
=
2.5 V
56
59
dB
OUTPUT CHARACTERISTICS
Output Saturation Voltage
V
CC
V
OH
, V
OL
V
EE
,
R
L
= 1 k
1.1
1.2
V
Short Circuit Current, Source
130
mA
Short Circuit Current, Sink
90
mA
Capacitive Load Drive
30% Overshoot
8
pF
POWER SUPPLY
Operating Range
5
12
V
Quiescent Current per Amplifier
9
10.2
mA
Power Supply Rejection Ratio
+PSRR
59
64
dB
PSRR
59
65
dB
REV. C
AD8007/AD8008
3
V
S
= +5 V
(@ T
A
= 25 C, R
S
= 200 , R
L
= 150 , R
F
= 499 , Gain = +2, unless otherwise noted.)
AD8007/AD8008
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Bandwidth
G = +1, V
O
= 0.2 V p-p, R
L
= 1 k
520
580
MHz
G = +1, V
O
= 0.2 V p-p, R
L
= 150
350
490
MHz
G = +2, V
O
= 0.2 V p-p, R
L
= 150
190
260
MHz
G = +1, V
O
= 1 V p-p, R
L
= 1 k
270
320
MHz
Bandwidth for 0.1 dB Flatness
Vo = 0.2 V p-p, G = +2, R
L
= 150
72
120
MHz
Overdrive Recovery Time
2.5 V Input Step, G = +2, R
L
= 1 k
30
ns
Slew Rate
G = +1, V
O
= 2 V Step
665
740
V/
s
Settling Time to 0.1%
G = +2, V
O
= 2 V Step
18
ns
Settling Time to 0.01%
G = +2, V
O
= 2 V Step
35
ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic
f
C
= 5 MHz, V
O
= 1 V p-p
96/95
dBc
f
C
= 20 MHz, V
O
= 1 V p-p
83/80
dBc
Third Harmonic
f
C
= 5 MHz, V
O
= 1 V p-p
100
dBc
f
C
= 20 MHz, V
O
= 1 V p-p
85/88
dBc
IMD
f
C
= 19.5 MHz to 20.5 MHz, R
L
= 1 k
,
89/87
dBc
V
O
= 1 V p-p
Third Order Intercept
f
C
= 5 MHz, R
L
= 1 k
43.0
dBm
f
C
= 20 MHz, R
L
= 1 k
42.5/41.5
dBm
Crosstalk (AD8008)
Output to Output f = 5 MHz, G = +2
68
dB
Input Voltage Noise
f = 100 kHz
2.7
nV/
Hz
Input Current Noise
Input, f = 100 kHz
22.5
pA/
Hz
+Input, f = 100 kHz
2
pA/
Hz
DC PERFORMANCE
Input Offset Voltage
0.5
4
mV
Input Offset Voltage Drift
3
V/C
Input Bias Current
+Input
4
8
A
Input
0.7
6
A
Input Bias Current Drift
+Input
15
nA/
C
Input
8
nA/
C
Transimpedance
V
O
= 1.5 V to 3.5 V, R
L
= 1 k
0.5
1.3
M
R
L
= 150
0.4
0.6
M
INPUT CHARACTERISTICS
Input Resistance
+Input
4
M
Input Capacitance
+Input
1
pF
Input Common-Mode Voltage Range
1.1 to 3.9
V
Common-Mode Rejection Ratio
V
CM
= 1.75 V to 3.25 V
54
56
dB
OUTPUT CHARACTERISTICS
Output Saturation Voltage
V
CC
V
OH
, V
OL
V
EE
,
R
L
= 1 k
1.05
1.15
V
Short Circuit Current, Source
70
mA
Short Circuit Current, Sink
50
mA
Capacitive Load Drive
30% Overshoot
8
pF
POWER SUPPLY
Operating Range
5
12
V
Quiescent Current per Amplifier
8.1
9
mA
Power Supply Rejection Ratio
+PSRR
59
62
dB
PSRR
59
63
dB
REV. C
4
AD8007/AD8008
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD80 07/
AD8008 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . See Figure 2
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . .
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . .
1.0 V
Output Short Circuit Duration . . . . . . . . . . . . . . See Figure 2
Storage Temperature . . . . . . . . . . . . . . . . . . 65
C to +125C
Operating Temperature Range . . . . . . . . . . . 40
C to +85C
Lead Temperature Range (soldering 10 sec) . . . . . . . . . 300
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8007/AD8008
packages is limited by the associated rise in junction temperature
(T
J
) on the die. The plastic encapsulating the die will locally reach
the junction temperature. At approximately 150
C, which is the
glass transition temperature, the plastic will change its proper-
ties. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, perma-
nently shifting the parametric performance of the AD8007/
AD8008. Exceeding a junction temperature of 175
C for an
extended period of time can result in changes in the silicon
devices, potentially causing failure.
The still-air thermal properties of the package and PCB (
JA
),
ambient temperature (T
A
), and the total power dissipated in the
package (P
D
) determine the junction temperature of the die.
The junction temperature can be calculated as follows:
T
T
P
A
D
A
J
J
=
+
(
)
The power dissipated in the package (P
D
) is the sum of the quies-
cent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (V
S
) times the quiescent current
(I
S
). Assuming the load (R
L
) is referenced to midsupply, the
total drive power is V
S
/2
I
OUT
, some of which is dissipated in the
package and some in the load (V
OUT
I
OUT
). The difference
between the total drive power and the load power is the drive
power dissipated in the package.
P
D
= quiescent power + (total drive power load power):
P
V
I
V
V
R
V
R
D
S
S
S
OUT
L
OUT
L
=
(
)
+




-
2
2
RMS output voltages should be considered. If R
L
is referenced
to V
S
, as in single-supply operation, then the total drive power
is V
S
I
OUT
.
If the rms signal levels are indeterminate, then consider the
worst case, when V
OUT
= V
S
/4 for R
L
to midsupply:
P
V
I
V
R
D
S
S
S
L
=
(
)
+




4
2
In single-supply operation, with R
L
referenced to V
S,
worst case is:
V
V
OUT
S
=
2
Airflow will increase heat dissipation, effectively reducing
JA
.
Also, more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes will
reduce the
JA
. Care must be taken to minimize parasitic capaci-
tances at the input leads of high speed op amps as discussed in
the board layout section.
Figure 2 shows the maximum safe power dissipation in the pack-
age versus the ambient temperature for the SOIC-8 (125
C/
W), MSOP (150
C/W), and SC70 (210C/W) packages on a
JEDEC standard 4-layer board.
JA
values are approximations.
AMBIENT TEMPERATURE C
2.0
1.5
0
60
100
40
MAXIMUM PO
WER DISSIP
A
TION
W
20
0
20
40
60
80
1.0
0.5
SOIC-8
SC70-5
MSOP-8
Figure 2. Maximum Power Dissipation vs.
Temperature for a 4-Layer Board
OUTPUT SHORT CIRCUIT
Shorting the output to ground or drawing excessive current for
the AD8007/AD8008 will likely cause catastrophic failure.
REV. C
AD8007/AD8008
5
ORDERING GUIDE
Model
Temperature Range
Package
Description
Package Outline
Branding
Information
AD8007AR
+85C
8-Lead SOIC
RN-8
AD8007AR-REEL
+85C
8-Lead SOIC
RN-8
AD8007AR-REEL7
+85C
8-Lead SOIC
RN-8
AD8007AKS-REEL
+85C
5-Lead SC70
KS-5
HTA
AD8007AKS-REEL7
40C to +85C
5-Lead SC70
KS-5
HTA
AD8008AR 40C
to
+85C
8-Lead
SOIC
RN-8
AD8008AR-REEL7
40C to +85C
8-Lead SOIC
RN-8
AD8008AR-REEL
40C to +85C
8-Lead SOIC
RN-8
AD8008ARM-REEL
+85C
8-Lead MSOP
RM-8
H2B
AD8008ARM-REEL7
+85C
8-Lead MSOP
RM-8
H2B
40C to
40C to
40C to
40C to
40C to
40C to
REV. C
6
AD8007/AD8008Typical Performance Characteristics
FREQUENCY MHz
3
2
5
1
100
10
NORMALIZED GAIN dB
1
2
3
4
1
0
6
7
1000
G = +1
G = +2
G = +10
G = 1
TPC 1. Small Signal Frequency Response for Various Gains
FREQUENCY MHz
3
2
5
100
10
GAIN dB
1
2
3
4
1
0
6
7
1000
R
L
= 150 , V
S
= +5V
R
L
= 150 , V
S
= 5V
R
L
= 1k , V
S
= 5V
G = +1
TPC 2. Small Signal Frequency Response for V
S
and R
LOAD
FREQUENCY MHz
3
2
5
100
10
GAIN dB
1
2
3
4
1
0
6
7
1000
R
S
= 249
R
S
= 301
R
S
= 200
G = +1
R
L
= 1k
TPC 3. Small Signal Frequency Response for
Various R
S
Values
FREQUENCY MHz
6.4
6.3
5.6
100
10
GAIN dB
6.0
5.9
5.8
5.7
6.2
6.1
5.5
5.4
1000
G = +2
V
S
= +5V
V
S
= 5V
TPC 4. 0.1 dB Gain Flatness; V
S
= +5,
5 V
FREQUENCY MHz
9
8
1
100
10
GAIN dB
5
4
3
2
7
6
0
1
1000
G = +2
R
L
= 150
V
S
= +5V
R
L
= 150 , V
S
= 5V
R
L
= 1k , V
S
= 5V
R
L
= 1k , V
S
= +5V
TPC 5. Small Signal Frequency Response for V
S
and R
LOAD
FREQUENCY MHz
9
8
1
100
10
GAIN dB
5
4
3
2
7
6
0
1
1000
G = +2
R
F
= R
G
= 249
R
F
= R
G
= 324
R
F
= R
G
= 649
R
F
= R
G
= 499
TPC 6. Small Signal Frequency Response for Various
Feedback Resistors, R
F
= R
G
(V
S
= 5 V, R
L
= 150 , R
S
= 200
, R
F
= 499
, unless otherwise noted.)
REV. C
AD8007/AD8008
7
FREQUENCY MHz
10
9
2
1
100
10
GAIN dB
6
5
4
3
8
7
1
0
1000
G = +2
20pF
0pF
20pF AND
10 SNUB
20pF AND
20 SNUB
499
499
200
49.9
R
SNUB
C
LOAD
TPC 7. Small Signal Frequency Response for Capacitive
Load and Snub Resistor
FREQUENCY MHz
3
2
5
100
10
GAIN dB
1
2
3
4
1
0
6
7
1000
V
S
= +5V, +85 C
V
S
= 5V, 40 C
V
S
= +5V, 40 C
V
S
= 5V, +85 C
G = +1
TPC 8. Small Signal Frequency Response over
Temperature, V
S
= +5 V,
5 V
FREQUENCY MHz
3
2
5
1
100
10
NORMALIZED GAIN dB
1
2
3
4
1
0
6
7
1000
V
OUT
= 2V p-p
G = +1 G = +2
G = +10
G = 1
TPC 9. Large Signal Frequency Response for Various Gains
FREQUENCY Hz
10M
1M
10k
1M
100k
TRANSIMPED
ANCE
1k
100
10
1
100k
10k
10M
100M
1G
0
30
90
150
210
270
330
PHASE Degrees
2G
TRANSIMPEDANCE
PHASE
30
90
180
TPC 10. Transimpedance and Phase vs. Frequency
FREQUENCY MHz
9
8
1
100
10
GAIN dB
5
4
3
2
7
6
0
1
1000
G = +2
V
S
= +5V, +85 C
V
S
= 5V, 40 C
V
S
= +5V, 40 C
V
S
= 5V, +85 C
TPC 11. Small Signal Frequency Response over
Temperature, V
S
= +5 V,
5 V
FREQUENCY MHz
9
8
1
100
10
GAIN dB
5
4
3
2
7
6
0
1
1000
R
L
= 150 , V
S
= 5V, V
O
= 2V p-p
R
L
= 1k , V
S
= 5V, V
O
= 2V p-p
R
L
= 150 , V
S
= +5V, V
O
= 1V p-p
R
L
= 1k , V
S
= +5V, V
O
= 1V p-p
G = +2
TPC 12. Large Signal Frequency Response for V
S
and R
LOAD
REV. C
8
AD8007/AD8008
FREQUENCY MHz
90
10
1
DIST
OR
TION dBc
50
60
70
80
40
100
110
100
G = 1
V
S
= 5V
V
O
= 1V p-p
HD2, R
L
= 150
HD3, R
L
= 150
HD2, R
L
= 1k
HD3, R
L
= 1k
TPC 13. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R
L
FREQUENCY MHz
90
10
1
DIST
OR
TION dBc
50
60
70
80
40
100
110
100
G = 1
V
S
= 5V
V
O
= 2V p-p
HD2, R
L
= 150
HD3, R
L
= 150
HD2, R
L
= 1k
HD3, R
L
= 1k
TPC 14. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R
L
FREQUENCY MHz
90
10
1
DIST
OR
TION dBc
50
60
70
80
40
100
110
100
V
S
= 5V
V
O
= 2V p-p
R
L
= 150
HD2, G = 1
HD3, G = 1
HD2, G = 10
HD3, G = 10
30
TPC 15. AD8007 Second and Third Harmonic Distortion
vs. Frequency and Gain
FREQUENCY MHz
90
10
1
DIST
OR
TION dBc
50
60
70
80
40
100
110
100
G = 2
V
S
= 5V
V
O
= 1V p-p
HD2, R
L
= 150
HD3, R
L
= 150
HD2, R
L
= 1k
HD3, R
L
= 1k
TPC 16. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R
L
FREQUENCY MHz
90
10
1
DIST
OR
TION dBc
50
60
70
80
40
100
110
100
G = 2
V
S
= 5V
V
O
= 2V p-p
HD2, R
L
= 150
HD3, R
L
= 150
HD2, R
L
= 1k
HD3, R
L
= 1k
TPC 17. AD8007 Second and Third Harmonic Distortion
vs. Frequency and R
L
FREQUENCY MHz
90
10
1
DIST
OR
TION dBc
50
60
70
80
40
100
110
100
G = +2
V
S
= 5V
R
L
= 150
30
HD2, V
O
= 2V p-p
HD3, V
O
= 2V p-p
HD2, V
O
= 4V p-p
HD3, V
O
= 4V p-p
TPC 18. AD8007 Second and Third Harmonic Distortion
vs. Frequency and V
OUT
(V
S
= 5 V, R
L
= 150 , R
S
= 200
, R
F
= 499
, unless otherwise noted.)
REV. C
AD8007/AD8008
9
FREQUENCY MHz
100
10
HD2, R
L
= 1k
HD2, R
L
= 150
HD3, R
L
= 1k
HD3, R
L
= 150
G = 1
V
S
= 5V
V
O
= 1V p-p
40
1
DIST
OR
TION dBc
110
100
90
80
70
60
50
TPC 19. AD8008 Second and Third Harmonic
Distortion vs. Frequency and R
L
FREQUENCY MHz
40
1
100
10
DIST
OR
TION dBc
HD2, R
L
= 1k
HD2, R
L
= 150
HD3, R
L
= 1k
HD3, R
L
= 150
G = 1
V
S
= 5V
V
O
= 1V p-p
110
100
90
80
70
60
50
TPC 20. AD8008 Second and Third Harmonic
Distortion vs. Frequency and R
L
FREQUENCY MHz
100
10
HD2, G = 10
V
S
= 5V
V
O
= 2V p-p
R
L
= 150
HD2, G = 1
HD3, G = 1
HD3, G = 10
40
1
DIST
OR
TION dBc
110
100
90
80
70
60
50
30
TPC 21. AD8008 Second and Third Harmonic
Distortion vs. Frequency and Gain
FREQUENCY MHz
100
10
HD2, R
L
= 1k
HD2, R
L
= 150
HD3, R
L
= 1k
HD3, R
L
= 150
G = 2
V
S
= 5V
V
O
= 1V p-p
40
1
DIST
OR
TION dBc
110
100
90
80
70
60
50
TPC 22. AD8008 Second and Third Harmonic
Distortion vs. Frequency and R
L
FREQUENCY MHz
100
10
HD2, R
L
= 150
HD3, R
L
= 1k
HD3, R
L
= 150
G = 2
V
S
= 5V
V
O
= 2V p-p
40
1
DIST
OR
TION dBc
110
100
90
80
70
60
50
HD2, R
L
= 1k
TPC 23. AD8008 Second and Third Harmonic
Distortion vs. Frequency and R
L
FREQUENCY MHz
100
10
HD2, V
O
= 2V p-p
G = 2
R
L
= 150
V
S
= 5
40
110
100
90
80
70
60
50
30
1
DIST
OR
TION dBc
HD2, V
O
= 4V p-p
HD3, V
O
= 2V p-p
HD3, V
O
= 4V p-p
TPC 24. AD8008 Second and Third Harmonic
Distortion vs. Frequency and V
OUT
(V
S
= 5 V, R
S
= 200
, R
F
= 499 , R
L
= 150
, @25 C, unless otherwise noted.)
REV. C
10
AD8007/AD8008
V
OUT
V p-p
90
1.5
1
DIST
OR
TION dBc
70
75
80
85
65
2
G = 2
V
S
= 5V
F
O
= 20MHz
2.5
HD2, R
L
= 150
HD3, R
L
= 150
HD2, R
L
= 1k
HD3, R
L
= 1k
60
TPC 25. AD8007 Second and Third Harmonic
Distortion vs. V
OUT
and R
L
FREQUENCY MHz
38
5
THIRD ORDER INTERCEPT dBm
42
41
40
39
43
G = +2
V
S
= 5V
V
O
= 2V p-p
R
L
= 1k
37
36
35
10
15
20
25
30
35
40
45
50
55
60
65
70
44
TPC 26. AD8007 Third Order Intercept vs. Frequency
V
OUT
V p-p
90
1.5
1
70
75
80
85
65
2
G = 2
V
S
= 5V
F
O
= 20MHz
2.5
HD2, R
L
= 150
HD3, R
L
= 150
HD2, R
L
= 1k
HD3, R
L
= 1k
TPC 27. AD8008 Second and Third Harmonic
Distortion vs. V
OUT
and R
L
V
OUT
V p-p
90
2
1
DIST
OR
TION dBc
70
75
80
85
65
3
4
G = 2
V
S
= 5V
F
O
= 20MHz
95
100
105
110
5
6
HD2, R
L
= 150
HD3, R
L
= 150
HD2, R
L
= 1k
HD3, R
L
= 1k
TPC 28. AD8007 Second and Third Harmonic
Distortion vs. V
OUT
and R
L
FREQUENCY MHz
38
42
41
40
39
43
70
44
G = 2
V
S
= 5V
V
O
= 2V p-p
R
L
= 1k
37
36
35
65
60
55
50
45
40
35
30
25
20
15
10
5
THIRD ORDER INTERCEPT dBm
TPC 29. AD8008 Third Order Intercept vs. Frequency
V
OUT
V p-p
90
1
70
75
80
85
65
2
6
G = 2
V
S
= 5V
F
O
= 20MHz
HD2, R
L
= 1k
HD2, R
L
= 150
HD3, R
L
= 150
HD3, R
L
= 1k
95
100
105
110
3
4
5
TPC 30. AD8008 Second and Third Harmonic
Distortion vs. V
OUT
and R
L
(V
S
= 5 V, R
S
= 200
, R
F
= 499 , R
L
= 150
, @25 C unless otherwise noted.)
REV. C
AD8007/AD8008
11
FREQUENCY Hz
10
1k
100
VO
LTA
G
E

NOISE nV/
Hz
100
10
1
10k
100k
1M
2.7nV/ Hz
TPC 31. Input Voltage Noise vs. Frequency
FREQUENCY Hz
100k
10M
1M
OUTPUT IMPED
ANCE
100
10
1
100M
1G
1000
0.1
0.01
G = 2
TPC 32. Output Impedance vs. Frequency
FREQUENCY Hz
100M
1G
CMRR dB
10
20
30
100k
1M
0
10M
40
50
60
70
V
S
= 5V, 5V
TPC 33. CMRR vs. Frequency
FREQUENCY Hz
10
10k
100
CURRENT NOISE pA/
Hz
100
10
1
100k
1M
1000
10M
1k
NONINVERTING CURRENT NOISE 2.0pA/ Hz
INVERTING CURRENT NOISE 22.5pA/ Hz
TPC 34. Input Current Noise vs. Frequency
FREQUENCY Hz
100k
1G
CR
OSST
ALK dB
100
1M
10M
100M
90
80
70
60
50
40
20
30
G = 2
R = 150
V
S
= 5V
V
M
= 1V p-p
SIDE B DRIVEN
SIDE A DRIVEN
TPC 35. AD8008 Crosstalk vs. Frequency (Output to Output)
FREQUENCY Hz
20
10
10k
1M
100k
PSRR dB
20
30
40
50
0
10
10M
100M
1G
60
70
80
+PSRR
PSRR
TPC 36. PSRR vs. Frequency
(V
S
=
5 V, R
L
= 150
, R
S
= 200
, R
F
= 499 , unless otherwise noted.)
REV. C
12
AD8007/AD8008
50mV/DIV
G = 1
R
L
= 150 , V
S
= 5V AND 5V
R
L
= 1k , V
S
= 5V AND 5V
0
10
20
30
40
50
TIME ns
TPC 37. Small Signal Transient Response for
R
L
= 150
, 1 k and V
S
= +5 V,
5 V
1V/DIV
G = +1
R
L
= 150
R
L
= 1k
0
10
20
30
40
50
TIME ns
TPC 38. Large Signal Transient Response for
R
L
= 150
, 1 k
G = 2
1V/DIV
0
10
20
30
40
50
TIME ns
C
LOAD
= 0pF
C
LOAD
= 10pF
C
LOAD
= 20pF
TPC 39. Large Signal Transient Response
for Capacitive Load = 0 pF, 10 pF, and 20 pF
G = +2
50mV/DIV
0
10
20
30
40
50
TIME ns
R
L
= 150 , V
S
= +5V AND 5V
R
L
= 1k , V
S
= +5V AND 5V
TPC 40. Small Signal Transient Response for
R
L
= 150
, 1 k and V
S
= +5 V,
5 V
G = 1
1V/DIV
0
10
20
30
40
50
TIME ns
INPUT
OUTPUT
TPC 41. Large Signal Transient Response, G
= 1,
R
L
= 150
50mV/DIV
C
L
= 0pF
C
L
= 20pF
C
L
= 20pF
R
SNUB
= 10
499
499
200
49.9
R
SNUB
C
LOAD
+
G = 2
0
10
20
30
40
50
TIME ns
TPC 42. Small Signal Transient Response: Effect of
Series Snub Resistor when Driving Capacitive Load
REV. C
AD8007/AD8008
13
TPC 43. Output Overdrive Recovery, R
L
= 1 k
,
150
, V
IN
=
2.5 V
0
TIME ns
5
10
15
20
25
30
35
40
45
G = +2
0.1
0
SETTLING
TIME %
0.2
0.3
0.4
0.5
0.1
0.2
0.3
0.4
0.5
18ns
TPC 44. 0.1% Settling Time, 2 V Step
R
L
1
200
0
V
OUT
V
3
2
1
0
4
400
600
2
3
4
800
1000
G = +10
V
S
= 5V
V
IN
= 0.75V
TPC 45. V
OUT
Swing vs. R
LOAD
, V
S
=
5 V, G = +10,
V
IN
=
0.75 V
0
100
200
TIME ns
INPUT (1V/DIV)
R
L
= 150
R
L
= 1k
OUTPUT (2V/DIV)
V
S
V
S
300
400
500
G = 2
REV. C
14
AD8007/AD8008
THEORY OF OPERATION
The AD8007 (single) and AD8008 (dual) are current feedback
amplifiers optimized for low distortion performance. A simplified
conceptual diagram of the AD8007 is shown in Figure 3. It closely
resembles a classic current feedback amplifier comprised of a
complementary emitter-follower input stage, a pair of signal mir-
rors, and a diamond output stage. However, in the case of the
AD8007/AD8008, several modifications have been made to greatly
improve the distortion performance over that of a classic current
feedback topology.
I
DI
+V
S
V
S
C
J
1
C
J
2
Q1
Q2
IN
D1
D2
I
1
I
2
IN+
I
3
I
4
I
DO
Q3
Q4
Q5
Q6
+V
S
V
S
R
F
OUT
R
G
M2
M1
HiZ
Figure 3. Simplified Schematic of AD8007
The signal mirrors have been replaced with low distortion, high
precision mirrors. They are shown as "M1" and "M2" in Figure 3.
Their primary function from a distortion standpoint is to greatly
reduce the effect of highly nonlinear distortion caused by capaci-
tances C
J
1 and C
J
2. These capacitors represent the collector-to-base
capacitances of the mirrors' output devices.
A voltage imbalance arises across the output stage, as measured
from the high impedance node "HiZ" to the output node "Out."
This imbalance is a result of delivering high output currents and
is the primary cause of output distortion. Circuitry is included
to sense this output voltage imbalance and generate a compensating
current "I
DO
." When injected into the circuit, I
DO
reduces the
distortion that would be generated at the output stage. Similarly,
the nonlinear voltage imbalance across the input stage (measured
from the noninverting to the inverting input) is sensed, and a cur-
rent "I
DI
" is injected to compensate for input-generated distortion.
The design and layout are strictly top-to-bottom symmetric in
order to minimize the presence of even-order harmonics.
USING THE AD8007/AD8008
Supply Decoupling for Low Distortion
Decoupling for low distortion performance requires careful
consideration. The commonly adopted practice of returning the
high frequency supply decoupling capacitors to physically sepa-
rate (and possibly distant) grounds can lead to degraded
even-order harmonic performance. This situation is shown in
Figure 4 using the AD8007 as an example. Note that for a sinu-
soidal input, each decoupling capacitor returns to its ground a
quasi-rectified current carrying high even-order harmonics.
+V
S
V
S
R
G
499
R
S
200
IN
R
F
499
GND 1
GND 2
OUT
AD8007
+
+
10 F
10 F
0.1 F
0.1 F
Figure 4. High Frequency Capacitors Returned
to Physically Separate Grounds (Not Recommended)
The decoupling scheme shown in Figure 5 is preferable. Here,
the two high frequency decoupling capacitors are first tied
together at a common node, and are then returned to the
ground plane through a single connection. By first adding the
two currents flowing through each high frequency decoupling
capacitor, one is ensuring that the current returned into the
ground plane is only at the fundamental frequency.
+V
S
V
S
R
G
499
R
S
200
IN
R
F
499
OUT
AD8007
+
+
10 F
0.1 F
10 F
0.1 F
Figure 5. High Frequency Capacitors Returned
to Ground at a Single Point (Recommended)
Whenever physical layout considerations prevent the decoupling
scheme shown in Figure 5, the user can connect one of the high
frequency decoupling capacitors directly across the supplies and
connect the other high frequency decoupling capacitor to ground.
This is shown in Figure 6.
REV. C
AD8007/AD8008
15
+V
S
V
S
R
G
499
R
S
200
IN
R
F
499
OUT
AD8007
+
+
10 F
10 F
C1
0.1 F
C2
0.1 F
Figure 6. High Frequency Capacitors Connected
across the Supplies (Recommended)
Layout Considerations
The standard noninverting configuration with recommended power
supply bypassing is shown in Figure 6. This is also the bypassing
scheme used on the evaluation board shown in Figure 7. The
0.1
F high frequency decoupling capacitors should be X7R or
NPO chip components. Connect C2 from the +V
S
pin to the V
S
pin. Connect C1 from the +V
S
pin to signal ground.
The length of the high frequency bypass capacitor leads is critical.
Parasitic inductance due to long leads will work against the low
impedance created by the bypass capacitor. The ground for the
load impedance should be at the same physical location as the
bypass capacitor grounds. For the larger value capacitors, which
are intended to be effective at lower frequencies, the current
return path distance is less critical.
LAYOUT AND GROUNDING CONSIDERATIONS
Grounding
A ground plane layer is important in densely packed PC boards
to minimize parasitic inductances. However, an understanding of
where the current flows in a circuit is critical to implementing
effective high speed circuit design. The length of the current path
is directly proportional to the magnitude of parasitic induc-
tances and thus the high frequency impedance of the path. High
speed currents in an inductive ground return will create an
unwanted voltage noise. Broad ground plane areas will reduce
the parasitic inductance.
Input Capacitance
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
Even 1 pF or 2 pF of capacitance will reduce the input imped-
ance at high frequencies, in turn increasing the amplifier's gain,
causing peaking of the frequency response or even oscillations
if severe enough. It is recommended that the external passive com-
ponents that are connected to the input pins be placed as close as
possible to the inputs to avoid parasitic capacitance. The ground
and power planes must be kept at a distance of at least 0.05 mm
from the input pins on all layers of the board.
Output Capacitance
To a lesser extent, parasitic capacitances on the output can cause
peaking of the frequency response. There are two methods to
effectively minimize its effect:
1. Put a small value resistor in series with the output to isolate
the load capacitance from the amplifier's output stage.
(See TPC 7.)
2. Increase the phase margin by (a) increasing the amplifier's
gain or (b) adding a pole by placing a capacitor in parallel
with the feedback resistor.
Input-to-Output Coupling
To minimize capacitive coupling, the input and output signal
traces should not be parallel. This helps reduce unwanted posi-
tive feedback.
External Components and Stability
The AD8007 and AD8008 are current feedback amplifiers and,
to a first order, the feedback resistor determines the bandwidth
and stability. The gain, load impedance, supply voltage, and
input impedances also have an effect.
TPC 6 shows the effect of changing R
F
on bandwidth and peaking
for a gain of +2. Increasing R
F
will reduce peaking but also
reduce the bandwidth. TPC 1 shows that for a given R
F
, increasing
the gain will also reduce peaking and bandwidth. Table I shows
the recommended R
F
and R
G
values that optimize bandwidth with
minimal peaking.
Table I. Recommended Component Values
Gain
R
F
(
)
R
G
(
)
R
S
1
499
499
200
+1
499
NA
200
+2
499
499
200
+5
499
124
200
+10
499
54.9
200
The load resistor will also affect bandwidth as shown in TPCs 2
and 5. A comparison between TPCs 2 and 5 also demonstrates
the effect of gain and supply voltage.
When driving loads with a capacitive component, stability is
improved by using a series snub resistor "R
SNUB
" at the output.
The frequency and pulse responses for various capacitive loads
are illustrated in TPCs 7 and 42, respectively.
For noninverting configurations, a resistor in series with the input,
R
S
, is needed to optimize stability for Gain = +1, as illustrated
in TPC 3. For larger noninverting gains, the effect of a series
resistor is reduced.
REV. C
16
AD8007/AD8008
AD8007
C2
0.1 F
C1
0.1 F
C4
10 F
+
+V
S
5
1
2
4
3
R
GP
R
GN
R
S
AGND
R
F
AGND
C3
10 F
+
V
S
OUTPUT
SMA
AGND
R
T
INPUT
SMA
RBT
Figure 7. Schematic of AD8007 Evaluation Board
for the SC70 Package
EVALUATION BOARD
The SC70 board schematic is shown in Figure 7. To use the
SC70 board in an inverting configuration, R
GN
is used and R
GP
is
left open. The position of R
S
can be shifted so that it connects
Pin 3 to ground. When used as a noninverter, R
GP
is populated
and R
GN
is left open. In both configurations, R
T
allows for a 50
termination resistor. Universal (inverting or noninverting) AD8007
SOIC, AD8008 SOIC, and AD8008 MSOP boards are also avail-
able. The SC70 and MSOP evaluation boards are shown in
Figures 815.
REV. C
AD8007/AD8008
17
Figure 8. SC70 Evaluation Board Silkscreen (Top)
Figure 9. SC70 Evaluation Board Silkscreen (Bottom)
Figure 10. SC70 Evaluation Board, Amplifier Side (Top)
Figure 11. SC70 Evaluation Board, Component
Side (Bottom)
REV. C
18
AD8007/AD8008
Figure 12. MSOP Evaluation Board Silkscreen (Top)
Figure 13. MSOP Evaluation Board Silkscreen (Bottom)
Figure 14. MSOP Evaluation Board, Amplifier Side (Top)
Figure 15. MSOP Evaluation Board, Amplifier
Side (Bottom)
REV. C
AD8007/AD8008
19
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches)
0.25 (0.0098)
0.19 (0.0075)
1.27 (0.0500)
0.41 (0.0160)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
8
5
4
1
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.33 (0.0130)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
5-Lead Pastic Surface Mount Package [SC70]
(KS-5)
Dimensions shown in millimeters
0.30
0.15
0.10
0.00
1.00
0.90
0.70
SEATING
PLANE
1.10 MAX
0.22
0.08
0.46
0.36
0.26
3
5
4
1
2
2.00 BSC
PIN 1
2.10 BSC
0.65 BSC
1.25 BSC
COMPLIANT TO JEDEC STANDARDS MO-203AA
Dimensions shown in millimeters
0.23
0.08
0.80
0.40
8
0
8
5
4
1
4.90
BSC
PIN 1
0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COMPLIANT TO JEDEC STANDARDS MO-187AA
COPLANARITY
0.10
8-Lead MSOP Package [MSOP]
(RM-8)
C02866010/02(C)
PRINTED IN U.S.A.
20
AD8007/AD8008
REV. C
Revision History
Location
Page
10/02--Data Sheet changed from REV. B to REV. C
CONNECTION DIAGRAMS captions updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ORDERING GUIDE updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 5 edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9/02--Data Sheet changed from REV. A to REV. B.
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8/02--Data Sheet changed from REV. 0 to REV. A.
Added AD8008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Added SOIC-8 (RN) and MSOP-8 (RM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to MAXIMUM POWER DISSIPATION SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
New Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
New TPCs 1924 and TPCs 27, 29, 30, and 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to EVALUATION BOARD section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MSOP-8 (RM) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19