www.docs.chipfind.ru
REV. A
a
AD8016
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Low Power, High Output Current
xDSL Line Driver
PIN CONFIGURATION
FEATURES
xDSL Line Driver that Features Full ADSL CO (Central
Office) Performance on 12 V Supplies
Low Power Operation
5 V to 12 V Voltage Supply
12.5 mA/Amp (Typ) Total Supply Current
Power-Reduced Keep-Alive Current of 4.5 mA/Amp
High Output Voltage and Current Drive
I
OUT
= 600 mA
40 V p-p Differential Output Voltage R
L
= 50 ,
V
S
= 12 V
Low Single Tone Distortion
75 dBc @ 1 MHz SFDR, R
L
= 100 , V
O
= 2 V p-p
MTPR = 75 dBc, 26 kHz to 1.1 MHz, Z
LINE
= 100 ,
P
LINE
= 20.4 dBm
High Speed
78 MHz Bandwidth (3 dB), G = +5
40 MHz Gain Flatness
1000 V/ s Slew Rates
PRODUCT DESCRIPTION
The AD8016 high output current dual amplifier is designed
for the line drive interface in Digital Subscriber Line systems
such as ADSL, HDSL2, and proprietary xDSL systems. The
drivers are capable, in full-bias operation, of providing 24.4 dBm
output power into low resistance loads, enough to power a
20.4 dBm line, including hybrid insertion loss.
FREQUENCY kHz
549.3
10dB/DIV
550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3
75dBc
Figure 1. Multitone Power Ratio; V
S
=
12 V, 20.4 dBm
Output Power into 100
, Downstream
24-Lead Batwing
(RB-24)
20-Lead PSOP3
(RP-20)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD8016
NC = NO CONNECT
V
OUT
1
+V1
+V2
V
INN
1
V
INP
1
NC
NC
NC
PWDN0
DGND
V1
V
OUT
2
V
INN
2
V
INP
2
NC
NC
NC
PWDN1
BIAS
V2
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD8016
NC = NO CONNECT
+V1
+V2
V
OUT
1
V
INN
1
V
INP
1
AGND
AGND
AGND
AGND
PWDN0
DGND
V1
NC
V
OUT
2
V
INN
2
V
INP
2
AGND
AGND
AGND
PWDN1
BIAS
V2
NC
AGND
28-Lead HTSSOP
(RE-28)
NC
NC
NC
BIAS
V2
+V1
+V2
V
OUT
1
V
IN
1
PWDN1
DGND
V1
V
OUT
2
+V
IN
2
PWDN0
NC = NO CONNECT
NC
NC
NC
V
IN
2
+V
IN
1
NC
NC
NC
NC
NC
NC
NC
NC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD8016ARE
The AD8016 is available in a low cost 24-lead SOIC, a ther-
mally enhanced 20-lead PSOP, and a 28-lead HTSSOP with
an exposed leadframe (ePAD). Operating from
12 V supplies,
the AD8016 requires only 1.5 W of total power dissipation
(refer to the Power Dissipation section for details) while driving
20.4 dBm of power downstream using the xDSL hybrid in Figure
33a and Figure 33b. Two digital bits (PWDN0, PWDN1) allow
the driver to be capable of full performance, an output "keep-alive
state," or two intermediate bias states. The "keep-alive" state
biases the output transistors enough to provide a low imped-
ance at the amplifier outputs for back termination.
The low power dissipation, high output current, high output voltage
swing, flexible power-down, and robust thermal packaging enable
the AD8016 to be used as the Central Office (CO) terminal driver
in ADSL, HDSL2, VDSL, and proprietary xDSL systems.
REV. A
2
AD8016SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Bandwidth
G = +1, R
F
= 1.5 k
, V
OUT
= 0.2 V p-p
380
MHz
G = +5, R
F
= 499
, V
OUT
< 0.5 V p-p
69
78
MHz
Bandwidth for 0.1 dB Flatness
G = +5, R
F
= 499
, V
OUT
= 0.2 V p-p
16
38
MHz
Large Signal Bandwidth
V
OUT
= 4 V p-p
90
MHz
Peaking
V
OUT
= 0.2 V p-p < 50 MHz
0.1
dB
Slew Rate
V
OUT
= 4 V p-p, G = +2
1000
V/
s
Rise and Fall Time
V
OUT
= 2 V p-p
2
ns
Settling Time
0.1%, V
OUT
= 2 V p-p
23
ns
Input Overdrive Recovery Time
V
OUT
= 12.5 V p-p
350
ns
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended
V
OUT
= 2 V p-p, G = +5, R
F
= 499
2nd Harmonic
f
C
= 1 MHz, R
L
= 100
/25
75/62
77/64
dBc
3rd Harmonic
f
C
= 1 MHz, R
L
= 100
/25
88/74
93/76
dBc
Multitone Power Ratio
1
26 kHz to 1.1 MHz, Z
LINE
= 100
,
P
LINE
= 20.4 dBm
75
dBc
IMD
500 kHz,
f = 10 kHz, R
L
= 100
/25
84/80
88/85
dBc
IP3
500 kHz, R
L
= 100
/25
42/40
43/41
dBm
Voltage Noise (RTI)
f = 10 kHz
2.6
4.5
nV/
Hz
Input Current Noise
f = 10 kHz
18
21
pA
Hz
INPUT CHARACTERISTICS
RTI Offset Voltage
3.0
1.0
+3.0
mV
+Input Bias Current
45
+45
A
Input Bias Current
75
4
+75
A
Input Resistance
400
k
Input Capacitance
2
pF
Input Common-Mode Voltage Range
10
+10
V
Common-Mode Rejection Ratio
58
64
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Single-Ended, R
L
= 100
11
+11
V
Linear Output Current
G = 5, R
L
= 10
, f
1
= 100 kHz,
60 dBc SFDR
400
600
mA
Short Circuit Current
2000
mA
Capacitive Load Drive
80
pF
POWER SUPPLY
Operating Range
3
13
V
Quiescent Current
PWDN1, PWDN0 = (1, 1)
12.5
13.2
mA/Amp
PWDN1, PWDN0 =
(1, 0)
8
10
mA/Amp
PWDN1, PWDN0 =
(0, 1)
5
8
mA/Amp
PWDN1, PWDN0 =
(0, 0)
4
6
mA/Amp
Recovery Time
To 95% of I
Q
25
s
Shutdown Current
250
A Out of Bias Pin
1.5
4.0
mA/Amp
Power Supply Rejection Ratio
V
S
=
1 V
63
75
dB
OPERATING TEMPERATURE RANGE
40
+85
C
NOTES
1
See Figure 43, R20, R21 = 0
, R1 = open.
Specifications subject to change without notice.
(@ 25 C, V
S
= 12 V, R
L
= 100
, PWDN0, PWDN1 = (1, 1), T
MIN
= 40 C,
T
MAX
= +85 C, unless otherwise noted)
REV. A
3
AD8016
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Bandwidth
G = +1, R
F
= 1.5 k
, V
OUT
= 0.2 V p-p
320
MHz
G = +5, R
F
= 499
, V
OUT
< 0.5 V p-p
70
71
MHz
Bandwidth for 0.1 dB Flatness
G = +5, R
F
= 499
, V
OUT
= 0.2 V p-p
10
15
MHz
Large Signal Bandwidth
V
OUT
= 1 V rms
80
MHz
Peaking
V
OUT
= 0.2 V p-p < 50 MHz
0.7
1.0
dB
Slew Rate
V
OUT
= 4 V p-p, G = +2
300
V/
s
Rise and Fall Time
V
OUT
= 2 V p-p
2
ns
Settling Time
0.1%, V
OUT
= 2 V p-p
39
ns
Input Overdrive Recovery Time
V
OUT
= 6.5 V p-p
350
ns
NOISE/DISTORTION PERFORMANCE
Distortion, Single-Ended
G = +5, V
OUT
= 2 V p-p, R
F
= 499
2nd Harmonic
f
C
= 1 MHz, R
L
= 100
/25
73/61
75/63
dBc
3rd Harmonic
f
C
= 1 MHz, R
L
= 100
/25
80/68
82/70
dBc
Multitone Power Ratio
1
26 kHz to 138 kHz, Z
LINE
= 100
,
P
LINE
= 13 dBm
68
dBc
IMD
500 kHz,
f = 110 kHz, R
L
= 100
/25
87/82
88/83
dBc
IP3
500 kHz
42/39
42/39
dBm
Voltage Noise (RTI)
f = 10 kHz
4
5
nV/
Hz
Input Current Noise
f = 10 kHz
17
20
pA
Hz
INPUT CHARACTERISTICS
RTI Offset Voltage
3.0
0.2
+3.0
mV
+Input Bias Current
25
10
+25
A
Input Bias Current
30
10
+30
A
Input Resistance
400
k
Input Capacitance
2
pF
Input Common-Mode Voltage Range
4
+4
V
Common-Mode Rejection Ratio
60
66
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
Single-Ended, R
L
= 100
5
+5
V
Linear Output Current
G = 5, R
L
= 5
, f = 100 kHz,
60 dBc SFDR
300
420
mA
Short Circuit Current
830
mA
Capacitive Load Drive
R
S
= 10
50
pF
POWER SUPPLY
Quiescent Current
PWDN1, PWDN0 = (1, 1)
8
9.7
mA/Amp
PWDN1, PWDN0 =
(1, 0)
6
6.9
mA/Amp
PWDN1, PWDN0 =
(0, 1)
4
5.0
mA/Amp
PWDN1, PWDN0 =
(0, 0)
3
4.1
mA/Amp
Recovery Time
To 95% of I
Q
23
s
Shutdown Current
250
A Out of Bias Pin
1.0
2.0
mA/Amp
Power Supply Rejection Ratio
V
S
=
1 V
63
80
dB
OPERATING TEMPERATURE RANGE
40
+85
C
NOTES
1
See Figure 43, R20, R21 = 0
, R1 = open.
Specifications subject to change without notice.
(@ 25 C, V
S
= 6 V, R
L
= 100
, PWDN0, PWDN1 = (1, 1), T
MIN
= 40 C,
T
MAX
= +85 C, unless otherwise noted)
SPECIFICATIONS
LOGIC INPUTS (CMOS-Compatible Logic)
Parameter
Min
Typ
Max
Unit
Logic "1" Voltage
2.2
+V
CC
V
Logic "0" Voltage
0
0.8
V
(PWDN0, PWDN1, V
CC
= 12 V or 6 V; Full Temperature Range)
REV. A
AD8016
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8016 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26.4 V
Internal Power Dissipation
PSOP3 Package
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 W
Batwing Package
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W
EPAD Package
4
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 W
Input Voltage (Common-Mode) . . . . . . . . . . . . . . . . . . . .
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . . 65
C to +125C
Operating Temperature Range . . . . . . . . . . . . 40
C to +85C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device on a four-layer board with 10 inches
2
of 1 oz. copper at
85
C 20-lead PSOP3 package:
JA
= 18
C/W.
3
Specification is for device on a four-layer board with 10 inches
2
of 1 oz. copper at
85
C 24-lead Batwing package:
JA
= 28
C/W.
4
Specification is for device on a four-layer board with 9 inches
2
of 1 oz. copper at
85
C 28-lead (EPAD) package:
JA
= 29
C/W.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8016
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
device is determined by the glass transition temperature of the
plastic, approximately 150
C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package.
The output stage of the AD8016 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8016 to source or sink 2000 mA. To ensure
proper operation, it is necessary to observe the maximum power
derating curves. Direct connection of the output to either power
supply rail can destroy the device.
AMBIENT TEMPERATURE C
7
0
MAXIMUM POWER DISSIPATION
Watts
6
5
4
3
2
1
0
10
20
30
40
50
60
70
80
90
PSOP3
BATWING
8
EPAD
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature for AD8016 for T
J
= 125
C
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD8016ARP
40
C to +85C
20-Lead PSOP3
RP-20
AD8016ARP-Reel
40
C to +85C
20-Lead PSOP3
ARP-Reel
AD8016ARP-EVAL
40
C to +85C
Evaluation Board
ARP-EVAL
AD8016ARB
40
C to +85C
24-Lead Batwing
RB-24
AD8016ARB-Reel
40
C to +85C
24-Lead Batwing
ARB-Reel
AD8016ARB-EVAL
40
C to +85C
Evaluation Board
ARB-EVAL
AD8016ARE
40
C to +85C
28-Lead HTSSOP
RE-28
AD8016ARE-Reel
40
C to +85C
28-Lead HTSSOP
ARE-Reel
AD8016ARE-EVAL
40
C to +85C
Evaluation Board
ARE-EVAL
REV. A
AD8016
5
Typical Performance Characteristics
0.1 F
0.1 F
10 F
10 F
49.9
124
499
R
L
V
OUT
+V
S
V
S
+
+
V
IN
Figure 3. Single-Ended Test Circuit; G = +5
V
OUT
= 100mV
V
IN
= 20mV
VOLTS
TIME 100ns/DIV
Figure 4. 100 mV Step Response; G = +5, V
S
=
6 V,
R
L
= 25
, Single-Ended
V
OUT
= 5V
V
IN
= 800mV
TIME 100ns/DIV
VOLTS
Figure 5. 4 V Step Response; G = +5, V
S
=
6 V,
R
L
= 25
, Single-Ended
499
49.9
+V
IN
R
L
499
111
49.9
V
IN
+V
O
V
O
+V
S
V
S
0.1 F
10 F
+
0.1 F
10 F
+
Figure 6. Differential Test Circuit; G = +10
V
OUT
= 100mV
V
IN
= 20mV
VOLTS
TIME 100ns/DIV
Figure 7. 100 mV Step Response; G = +5, V
S
=
12 V,
R
L
= 25
, Single-Ended
V
OUT
= 4V
V
IN
= 800mV
VOLTS
TIME 100ns/DIV
Figure 8. 4 V Step Response; G = +5, V
S
=
12 V,
R
L
= 25
, Single-Ended
REV. A
AD8016
6
(0,1)
(1,0)
FREQUENCY MHz
30
0.01
10
DISTORTION
dBc
1
0.1
110
100
90
80
70
60
50
40
20
R
F
= 499
G = +10
V
O
= 4V p-p
PWDN 1,0 = (1,1)
(0,0)
Figure 10. Distortion vs. Frequency; Second Harmonic,
V
S
=
6 V, R
L
= 50
, Different
(0,1)
PEAK OUTPUT CURRENT mA
30
0
100
DISTORTION
dBc
200
80
75
70
65
60
55
50
40
R
F
= 499
G = +5
PWDN 1,0 = (1,1)
(0,0)
35
45
300
400
500
600
700
800
(1,0)
Figure 11. Distortion vs. Peak Output Current; Second
Harmonic, V
S
=
12 V, R
L
= 10
, f = 100 kHz, Single-Ended
(1,0)
(0,1)
FREQUENCY MHz
30
0.01
10
DISTORTION
dBc
1
0.1
110
100
90
80
70
60
50
40
20
R
F
= 499
G = +10
V
O
= 4V p-p
PWDN 1,0 = (1,1)
(0,0)
Figure 9. Distortion vs. Frequency; Second Harmonic,
V
S
=
12 V, R
L
= 50
, Differential
(0,1)
FREQUENCY MHz
30
0.01
10
DISTORTION
dBc
1
0.1
110
100
90
80
70
60
50
40
20
R
F
= 499
G = +10
V
O
= 4V p-p
PWDN 1,0 = (1,1)
(0,0)
(1,0)
Figure 12. Distortion vs. Frequency; Third Harmonic,
V
S
=
12 V, R
L
= 50
, Differential
(1,0)
(0,1)
FREQUENCY MHz
30
0.01
10
DISTORTION
dBc
1
0.1
110
100
90
80
70
60
50
40
20
R
F
= 499
G = +10
V
O
= 4V p-p
PWDN 1,0 = (1,1)
(0,0)
Figure 13. Distortion vs. Frequency; Third Harmonic,
V
S
=
6 V, R
L
= 50
, Differential
(1,0)
(0,1)
PEAK OUTPUT CURRENT mA
30
0
100
DISTORTION
dBc
200
90
80
70
50
R
F
= 499
G = +5
PWDN
1,0 = (1,1)
(0,0)
40
60
300
400
500
600
700
Figure 14. Distortion vs. Peak Output Current, Third
Harmonic; V
S
=
12 V, R
L
= 10
, G = +5, f = 100 kHz,
Single-Ended
REV. A
AD8016
7
(1,0)
(0,1)
PEAK OUTPUT CURRENT mA
30
0
100
DISTORTION
dBc
200
80
75
70
65
60
55
50
40
R
F
= 499
G = +5
PWDN 1,0 = (1,1)
(0,0)
35
45
300
400
500
600
Figure 15. Distortion vs. Peak Output Current; Second
Harmonic, V
S
=
6 V, R
L
= 5
, f = 100 kHz, Single-Ended
(0,1)
DIFFERENTIAL OUTPUT V p-p
30
0
5
DISTORTION
dBc
10
100
90
80
70
50
PWDN 1,0 = (1,1)
(0,0)
40
60
15
20
25
30
35
40
(1,0)
Figure 16. Distortion vs. Output Voltage; Second
Harmonic, V
S
=
12 V, G = +10, f = 1 MHz, R
L
= 50
,
Differential
(1,0)
(0,1)
DIFFERENTIAL OUTPUT V p-p
30
0
5
DISTORTION
dBc
10
90
80
70
50
PWDN 1,0 = (1,1)
(0,0)
40
60
15
20
Figure 17. Distortion vs. Output Voltage; Second
Harmonic, V
S
=
6 V, G = +10, f = 1 MHz, R
L
= 50
,
Differential
(1,0)
(0,1)
PEAK OUTPUT CURRENT mA
30
0
100
DISTORTION
dBc
200
80
75
70
65
60
55
50
40
PWDN 1,0 = (1,1)
(0,0)
35
45
300
400
500
600
Figure 18. Distortion vs. Peak Output Current; Third
Harmonic, V
S
=
6 V, G = +5, R
L
= 5
, f = 100 kHz,
Single-Ended
(1,0)
(0,1)
DIFFERENTIAL OUTPUT V p-p
30
0
5
DISTORTION
dBc
10
100
90
80
70
50
PWDN 1,0 = (1,1)
(0,0)
40
60
15
20
25
30
35
40
Figure 19. Distortion vs. Output Voltage; Third
Harmonic, V
S
=
12 V, G = +10, f = 1 MHz, R
L
= 50
,
Differential
(1,0)
(0,1)
DIFFERENTIAL OUTPUT V p-p
30
0
5
DISTORTION
dBc
10
90
80
70
50
PWDN 1,0 = (1,1)
(0,0)
40
60
15
20
Figure 20. Distortion vs. Output Voltage, Third Harmonic,
V
S
=
6 V, G = +10, f = 1 MHz, R
L
= 50
, Differential
REV. A
AD8016
8
FREQUENCY MHz
1
10
100
500
3
0
3
6
9
12
15
18
21
24
27
NORMALIZED FREQUENCY RESPONSE
dB
V
IN
= 40mV p-p
G = +5
R
L
= 100
1,1
1,0
0,1
0,0
Figure 21. Frequency Response; V
S
=
12 V,
@ PWDN1, PWDN0 Codes
FREQUENCY MHz
1
OUTPUT VOLTAGE
dBV
16
19
10
100
500
G = +5
R
L
= 100
R
F
= 499
13
10
7
4
1
2
5
8
11
Figure 22. Output Voltage vs. Frequency; V
S
=
12 V
FREQUENCY MHz
20
0.03
CMRR
dB
0.1
1
10
100
500
10
0
10
20
30
40
50
60
70
80
V
IN
= 2V rms
R
F
= 602
1,1
1,0
0,1
0,0
Figure 23. CMRR vs. Frequency; V
S
=
12 V
@ PWDN1, PWDN0 Codes
FREQUENCY MHz
1
10
100
500
3
0
3
6
9
12
15
18
21
24
6
NORMALIZED FREQUENCY RESPONSE
dB
V
IN
= 40mV p-p
G = +5
R
L
= 100
1,1
0,1
1,0
0,0
Figure 24. Frequency Response; V
S
=
6 V,
@ PWDN1, PWDN0 Codes
FREQUENCY MHz
1
PSRR
dB
16
19
10
100
500
13
10
7
4
1
2
5
8
11
G = +5
R
L
= 100
R
F
= 499
Figure 25. PSRR vs. Frequency; V
S
=
6 V
FREQUENCY MHz
10
0.01
PSRR
dB
20
30
40
50
60
70
80
90
0.1
1
10
100
500
+PSRR
PSRR
R
F
= 499
Figure 26. PSRR vs. Frequency; V
S
=
12 V
REV. A
AD8016
9
0
FREQUENCY MHz
10
INPUT VOLTAGE NOISE
nV/ Hz
100
80
60
40
20
100
1k
10k
10M
10
20
30
40
50
60
70
80
90
+ INPUT CURRENT NOISE
pA/ Hz
0
120
140
160
180
100k
1M
+I
NOISE
V
IN NOISE
Figure 27. Noise vs. Frequency
+2mV
(0.1%)
2mV
(0.1%)
0
0
5
10
15
20
25
30
35
40
45
5
G = +2
R
F
= 1k
V
OUT
= 2V
STEP
R
L
= 100
OUTPUT VOLTAGE ERROR
2mV/DIV (0.1%/DIV)
V
IN
V
OUT
TIME ns
V
OUT
V
IN
Figure 28. Settling Time 0.1%; V
S
=
12 V
FREQUENCY MHz
30
0.03
CROSSTALK
dB
0.1
1
10
100
500
40
50
60
70
80
90
V
OUT
= 2V p-p
R
F
= 499
G = +5
R
L
= 100
20
Figure 29. Output Crosstalk vs. Frequency
FREQUENCY MHz
1000000
0.0001
TRANSIMPEDANCE
k
100000
10000
1000
100
10
1
0.1
0.01
0
0.001
0.01
0.1
1
10
100
1000
10000
0
40
80
120
160
200
240
280
320
360
PHASE
Degrees
TRANSIMPEDANCE
PHASE
Figure 30. Open-Loop Transimpedance and Phase
vs. Frequency
0
5
10
15
20
25
30
35
40
45
5
G = +2
R
F
= 1k
V
OUT
= 2V
STEP
R
L
= 100
OUTPUT VOLTAGE ERROR
2mV/DIV (0.1%/DIV)
TIME ns
+2mV
(0.1%)
2mV
(0.1%)
0
V
OUT
V
IN
V
OUT
V
IN
Figure 31. Settling Time 0.1%; V
S
=
6 V
FREQUENCY MHz
1000
0.03
OUTPUT IMPEDANCE
0.1
1
10
100
500
100
10
1
0.1
0.01
0,0
0,1
1,1
1,0
Figure 32. Output Impedance vs. Frequency
@ PWDN1, PWDN0 Codes
REV. A
AD8016
10
V
IN
= 2V/DIV
V
OUT
= 5V/DIV
V
IN
V
OUT
100
0
100
200
300
400
500
600
700
800
900
TIME ns
0V
0V
a. Overload Recovery; V
S
=
12 V, G = +5, R
L
= 100
100
0
100
200
300
400
500
600
700
800
900
TIME ns
V
IN
V
OUT
0V
0V
V
IN
= 2V/DIV
V
OUT
= 5V/DIV
b. Overload Recovery; V
S
=
12 V, G = +5, R
L
= 100
Figure 33.
I
BIAS
A
25
0
I
Q
mA
20
15
10
5
0
50
100
150
200
[0,1]
[0,0]
[1,0]
PWDN 1,0 = [1,1]
Figure 34. I
Q
vs. I
BIAS
Pin Current; V
S
=
12 V
I
BIAS
A
18
0
I
Q
mA
16
14
12
10
8
50
100
150
200
6
4
2
0
PWDN 1,0 = [1.1]
[1,0]
[0,1]
[0,0]
Figure 35. I
Q
vs. I
BIAS
Pin Current; V
S
=
6 V
R
LOAD
OUTPUT SWING
Volts
12
8
10
100
1k
10k
4
0
4
8
12
+V
OUT
, V
S
= 12V
+V
OUT
, V
S
= 6V
V
OUT
, V
S
= 6V
V
OUT
, V
S
= 12V
Figure 36. Output Voltage vs. R
LOAD
REV. A
AD8016
11
FEEDBACK RESISTOR SELECTION
In current feedback amplifiers, selection of feedback and gain
resistors will have an impact on the MTPR performance, band-
width and gain flatness. Care should be exercised in the selec-
tion of these resistors so that optimum performance is achieved.
The table below shows the recommended resistor values for use
in a variety of gain settings. These values are suggested as a
good starting point when designing for any application.
Table I. Resistor Selection Guide
Gain
R
F
( )
R
G
( )
+1
1 k
1
500
500
+2
650
650
+5
750
187
+10
1 k
111
BIAS PIN AND PWDN FEATURES
The AD8016 is designed to cover both CO (Central Office) and
CPE (Customer Premise Equipment) ends of an xDSL applica-
tion. It offers full versatility in setting quiescent bias levels for
the particular application from full ON to reduced bias (in three
steps) to full OFF (via BIAS pin). This versatility gives the
modem designer the flexibility to maximize efficiency while
maintaining reasonable levels of Multitone Power Ratio (MTPR)
performance. Optimizing driver efficiency while delivering the
required DMT power is accomplished with the AD8016 through
the use of on-chip power management features. Two digitally
programmable logic pins, PWDN1 and PWDN0, may be used
to select four different bias levels; 100%, 60%, 40%, and 25%
of full quiescent power (see Table II).
Table II. PWDN Code Selection Guide
PWDN1
PWDN0
Code
Code
Quiescent Bias Level
1
1
100% (Full ON)
1
0
60%
0
1
40%
0
0
25% (Low Z
OUT
but Not OFF)
X
X
Full OFF (High Z
OUT
via 250
A
Pulled Out of BIAS Pin)
The bias level can be controlled with TTL logic levels (HI = 1)
applied to PWDN1 and PWDN0 pins alone or in combination
with BIAS control pin. The DGND or digital ground pin is the
logic ground reference for PWDN1 and PWDN0 pins. In typical
ADSL applications where
12 V or 6 V supplies (also single
supplies) are used, the DGND pin is connected to analog ground.
The BIAS control pin by itself is a means to continuously adjust
the AD8016 internal biasing and thus quiescent current I
Q
. By
pulling out a current of 0
A (or open) to approximately 200 A,
the quiescent current can be adjusted from 100% (full ON) to a
full OFF condition. The full OFF condition yields a high output
impedance. Because of on-chip resistor variation of up to
20%
the actual amount of current required to fully shut down the
AD8016 can vary. To institute a full chip shutdown, a pull-
down current of 250
A is recommended. See Figure 38 for
logic drive circuit for complete amplifier shutdown. Figures 34
and 35 show the relationship between current pulled out of
THEORY OF OPERATION
The AD8016 is a current feedback amplifier with high (500 mA)
output current capability. With a current feedback amplifier the
current into the inverting input is the feedback signal and the
open-loop behavior is that of a transimpedance, dVo/dIin or T
Z
.
The open-loop transimpedance is analogous to the open-loop
voltage gain of a voltage feedback amplifier. Figure 37 shows a
simplified model of a current feedback amplifier. Since R
IN
is
proportional to 1/g
m
, the equivalent voltage gain is just T
Z
g
m
,
where g
m
is the transconductance of the input stage. Basic
analysis of the follower with gain circuit yields:
V
V
G
T
S
T
S
G
R
R
O
IN
Z
Z
IN
F
=
+
+
( )
( )
where:
G
R
R
R
g
F
G
IN
m
= +
=
1
1
25
Recognizing that G
R
IN
<< R
F
for low gains, the familiar
result of constant bandwidth with gain for current feedback
amplifiers is evident, the 3 dB point being set when |T
Z
| = R
F
.
Of course, for a real amplifier there are additional poles that
contribute excess phase and there will be a value for R
F
below
which the amplifier is unstable. Tolerance for peaking and desired
flatness will determine the optimum R
F
in each application.
T
Z
R
IN
I
IN
+
+
R
F
V
OUT
R
N
R
G
V
IN
Figure 37. Simplified Block Diagram
The AD8016 is the first current feedback amplifier capable of
delivering 400 mA of output current while swinging to within
2 V of either power supply rail. This enables full CO ADSL
performance on only 12 V rails, an immediate 20% power saving.
The AD8016 is also unique in that it has a power management
system included on-chip. It features four user programmable
power levels (all of which provide a low output impedance of the
driver), as well as the provision for complete shutdown (high
impedance state). Also featured is a thermal shutdown with
alarm signal.
POWER SUPPLY AND DECOUPLING
The AD8016 should be powered with a good quality (i.e., low
noise) dual supply of
12 V for the best distortion and Multi-
tone Power Ratio (MTPR) performance. Careful attention must
be paid to decoupling the power supply pins. A 10
F capacitor
located in near proximity to the AD8016 is required to provide
good decoupling for lower frequency signals. In addition, 0.1
F
decoupling capacitors should be located as close to each of the
four power supply pins as is physically possible. All ground pins
should be connected to a common low impedance ground
plane.
REV. A
AD8016
12
BIAS pin (I
BIAS
) and the supply current (I
Q
). A typical shut-
down I
Q
is less than 1 mA total. Alternatively, an external pull-
down resistor to ground or a current sink attached to the BIAS
pin can be used to set I
Q
to lower levels (see Figure 39). The
BIAS pin may be used in combination with the PWDN1 and
PWDN0 pins; however, diminished MTPR performance may
result when I
Q
is lowered too much. Current pulled away from
the BIAS pin will shunt away a portion of the internal bias cur-
rent. Setting PWDN1 or PWDN0 to Logic 0 also shunts away a
portion of the internal bias current. The reduction of quiescent
bias levels due to the use of PWDN1 and PWDN0 is consistent
with the percentages established in Table II. When PWDN0 alone
is set to Logic 0, and no other means of reducing the internal
bias currents is used, full-rate ADSL signals may be driven while
maintaining reasonable levels of MTPR.
R2
50k
BIAS
R1
*
3.3V LOGIC
2N3904
*R1 = 47k FOR 12V
S
OR +12V
S
,
R1 = 22k FOR 6V
S
.
Figure 38. Logic Drive of BIAS Pin for Complete Amplifier
Shutdown
THERMAL SHUTDOWN
The AD8016ARB and ARP have been designed to incorporate
shutdown protection against accidental thermal overload. In the
event of thermal overload, the AD8016 was designed to shut
down at a junction temperature of 165
C and return to normal
operation at a junction temperature 140
C The AD8016 will
continue to operate, cycling on and off, as long as the thermal
overload condition remains. The frequency of the protection
cycle depends on the ambient environment, severity of the ther-
mal overload condition, the power being dissipated and the ther-
mal mass of the PCB beneath the AD8016. When the AD8016
begins to cycle due to thermal stress, the internal shutdown
circuitry draws current out of the node connected in common
with the BIAS pin, while the voltage at the BIAS pin goes to the
negative rail. When the junction temperature returns to 140
C,
current is no longer drawn from this node and the BIAS pin
voltage returns to the positive rail. Under these circumstances,
the BIAS pin can be used to trip an alarm indicating the pres-
ence of a thermal overload condition.
Figure 39 also shows three circuits for converting this signal to a
standard logic level.
V
CC
+5V
BIAS
10k
ALARM
1/4 HCF 40109B
SGS - THOMSON
10k
+5V
100k
1M
BIAS
ALARM
MIN 350
OR
V
EE
10k
200 A
V
CC
BIAS
PWDN1
BIAS
OR
0200 A
V = V
CC
0.2V
SHUT-
DOWN
AD8016
PWDN0
Figure 39. Shutdown and Alarm Circuit
APPLICATIONS
The AD8016ARP and AD8016ARB dual xDSL line driver
amplifiers are the most efficient xDSL line drivers available to
the market today. The AD8016 may be applied in driving modu-
lated signals including Discrete Multitone (DMT) in either
direction; upstream from Customer Premise Equipment (CPE)
to the Central Office (CO) and downstream from CO to CPE.
The most significant thermal management challenge lies in
driving downstream information from CO sites to the CPE.
Driving xDSL information downstream suggests the need to
locate many xDSL modems in a single CO site. The implication
is that several modems will be placed onto a single printed cir-
cuit board residing in a card cage located in a variety of ambient
conditions. Environmental conditioners such as fans or air con-
ditioning may or may not be available, depending on the density
of modems and the facilities contained at the CO site. To achieve
long-term reliability and consistent modem performance, designers
of CO solutions must consider the wide array of ambient condi-
tions that exist within various CO sites.
MULTITONE POWER RATIO OR MTPR
ADSL systems rely on Discrete Multitone (or DMT) modulation
to carry digital data over phone lines. DMT modulation appears
in the frequency domain as power contained in several individual
frequency subbands, sometimes referred to as tones or bins, each
of which is uniformly separated in frequency. (See Figure 1 for
example of downstream DMT signals used in evaluating MTPR
performance.) A uniquely encoded, Quadrature Amplitude Modu-
lation (QAM) signal occurs at the center frequency of each
subband or tone. Difficulties will exist when decoding these
subbands if a QAM signal from one subband is corrupted by the
QAM signal(s) from other subbands, regardless of whether the
corruption comes from an adjacent subband or harmonics of
other subbands. Conventional methods of expressing the output
signal integrity of line drivers, such as spurious free dynamic range
(SFDR), single-tone harmonic distortion or THD, two-tone
Intermodulation Distortion (IMD) and 3rd order intercept (IP3)
become significantly less meaningful when amplifiers are required
to drive DMT and other heavily modulated waveforms. A typical
xDSL downstream DMT signal may contain as many as 256
carriers (subbands or tones) of QAM signals. Multitone Power
Ratio (MTPR) is the relative difference between the measured
power in a typical subband (at one tone or carrier) versus the
power at another subband specifically selected to contain no QAM
data. In other words, a selected subband (or tone) remains open
or void of intentional power (without a QAM signal) yielding an
empty frequency bin. MTPR, sometimes referred to as the "empty
bin test," is typically expressed in dBc, similar to expressing the
relative difference between single-tone fundamentals and 2nd or
3rd harmonic distortion components.
See Figure 1 for a sample of the ADSL downstream spectrum
showing MTPR results while driving 20.4 dBm of power onto a
100
line. Measurements of MTPR are typically made at the
output (line side) of ADSL hybrid circuits. (See Figure 46a for
an example of Analog Devices' hybrid schematic.) MTPR can
be affected by the components contained in the hybrid circuit,
including the quality of the capacitor dielectrics, voltage ratings
and the turns ratio of the selected transformers. Other compo-
nents aside, an ADSL driver hybrid containing the AD8016 can be
optimized for the best MTPR performance by selecting the turns
ratio of the transformers. The voltage and current demands from
the differential driver changes, depending on the transformer
REV. A
AD8016
13
turns ratio. The point on the curve indicating maximum dynamic
headroom is achieved when the differential driver delivers both
the maximum voltage and current while maintaining the lowest
possible distortion. Below this point the driver has reserve cur-
rent-driving capability and experiences voltage clipping while
above this point the amplifier runs out of current drive capabil-
ity before the maximum voltage drive capability is reached.
Since a transformer reflects the secondary load impedance back
to the primary side by the square of the turns ratio, varying the
turns ratio changes the load across the differential driver. In the
transformer configuration of Figure 46a and 46b, the turns ratio
of the selected transformer is effectively doubled due to the
parallel wiring of the transformer primaries within this ADSL
driver hybrid. The following equation may be used to calculate
the load impedance across the output of the differential driver,
reflected by the transformers, from the line side of the xDSL
driver hybrid. Z' is the primary side impedance as seen by the
differential driver; Z
2
is the line impedance and N is the trans-
former turns ratio.
Z
Z
N
'
(
)
2
2
2
Figure 40 shows the dynamic headroom in each subband of a
downstream DMT waveform versus turns ratio running at 100%
and 60% of the quiescent power while maintaining 65 dBc of
MTPR at V
S
=
12 V.
4
1
3
2
1.2
1.4
2
1
0
1
1.6
1.8
2
1.1
1.3
1.5
1.7
1.9
DOWNSTREAM TURNS RATIO
DYNAMIC HEADROOM
dB
V
S
= 12V
PWDN1,0 = (1,1)
V
S
= 11.4V
PWDN1,0 = (1,1)
V
S
= 11.4V
PWDN1,0 = (1,0)
V
S
= 12V
PWDN1,0 = (1,0)
Figure 40. Dynamic Headroom vs. XFMR Turns Ratio,
V
S
=
12 V
Once an optimum turns ratio is determined, the amplifier will
have an MTPR performance for each setting of the power-down
pins. The table below demonstrates the effects of reducing the
total power dissipated by using the PWDN pins on MTPR
performance when driving 20.4 dBm downstream onto the line
with a transformer turns ratio of 1:1.4.
Table III. Dynamic Power Dissipation for Downstream
Transmission
PWDN1
PWDN0
PD (W)
MTPR
1
1
1.454
78 dBc
1
0
1.262
75.3 dBc
0
1
1.142
57.2 dBc
0
*
0
0.120
N/A
*This mode is quiescent power dissipation.
GENERATING DMT
At this time, DMT-modulated waveforms are not typically menu-
selectable items contained within arbitrary waveform generators.
Even using (AWG) software to generate DMT signals, AWGs
that are available today may not deliver DMT signals sufficient
in performance with regard to MTPR due to limitations in the
D/A converters and output drivers used by AWG manufactur-
ers. Similar to evaluating single-tone distortion performance of
an amplifier, MTPR evaluation requires a DMT signal generator
capable of delivering MTPR performance better than that of the
driver under evaluation. Generating DMT signals can be accom-
plished using a Tektronics AWG 2021 equipped with opt 4,
(12/24-Bit, TTL Digital Data Out), digitally coupled to Analog
Devices AD9754, a 14-bit TxDAC, buffered by an AD8002
amplifier configured as a differential driver. See Figure 45 for
schematics of a circuit used to generate DMT signals that can
achieve down to 80 dBc of MTPR performance, sufficient for
use in evaluating xDSL drivers. Note that the DMT waveforms
available with the AD8016ARP-EVAL and AD8016ARB-EVAL
boards or similar WFM files are needed to produce the neces-
sary digital data required to drive the TxDAC from the optional
TTL Digital Data output of the TEK AWG2021. Copies of
these WFM files can be obtained through the Analog Devices
website. http://www.analog.com/.
EVALUATION BOARDS
The AD8016ARP-EVAL, AD8016ARB-EVAL, AD8016ARE-EVAL
boards available through Analog Device provide a platform for
evaluating the AD8016 in an ADSL differential line driver
circuit. The board is laid out to accommodate Analog Devices
two transformer line driver hybrid circuit (see Figures 46a and
46b) including line matching network, an RJ11 jack for interfac-
ing to line simulators, transformer coupled input for single-to-
differential input conversion and accommodations for the receiver
function. Schematics and layout information are available for both
versions of the EVAL board. Also included in the package are
WFM files for use in generating 14-bit DMT waveforms.
Upstream data is contained in the ...24.wfm files and down-
stream data in the ...128.wfm files.
These DMT modulated signals are used to evaluate xDSL
products for Multitone Power Ratio or MTPR performance.
The data files are used in pairs (adslu24.wfm and adsll24.wfm
go together, etc.) and are loaded into Tektronics AWG2021
arbitrary waveform generator. The adslu24.wfm is loaded via
the TEK AWG2021 floppy drive into Channel 1, while the
adsll24.wfm is simultaneously loaded into Channel 2. The num-
ber in the file name, prefixed with "u," goes into CH1 or upper
channel and the "l" goes into CH2 or the lower channel. 12 bits
from CH1 are combined with 2 bits from CH2 to achieve 14-
bit digital data at the digital outputs of the TEK 2021. The
resulting waveforms produced at the AD9754-EB outputs are
then buffered and amplified by the AD8002 differential driver to
achieve 14-bit performance from this DMT signal source.
POWER DISSIPATION
In order to properly size the heat sinking area for your applica-
tion, it is important to consider the total power dissipation of
the AD8016. The dc power dissipation for V
IN
= 0 is I
Q
(VCC
VEE), or 2
I
Q
V
S
.
For the AD8016 powered on +12 V and 12 V supplies (
V
S
),
the number is 0.6 W. In a differential driver circuit (Figure 6),
REV. A
AD8016
14
we can use symmetry to simplify the computation for a dc input
signal.
P
I
V
V
V
V
R
D
Q
S
S
O
O
L
=
+
2
4
(
)
where
V
O
is the peak output voltage of an amplifier.
This formula is slightly pessimistic due to the fact that some of
the quiescent supply current is commutated during sourcing or
sinking current into the load. For a sine wave source, integration
over a half cycle yields:
P
I
V
V V
R
V
R
D
Q
S
O
S
L
O
L
=
+
-
2
2
4
2
The situation is more complicated with a complex modulated
signal. In the case of a DMT signal, taking the equivalent sine
wave power overestimates the power dissipation by ~23%. For
example:
P
OUT
= 23.4 dBm = 220 mW
V
OUT
@ 50
= 3.31 V rms
V
O
= 2.354 V
at each amplifier output, which yields a P
D
of 1.81 W.
Through measurement, a DMT signal of 23.4 dBm requires
1.47 W of power to be dissipated by the AD8016. Figure 41
shows the results of calculation and actual measurements
detailing the relationship between the power dissipated by the
AD8016 versus the total output power delivered to the back
termination resistors and the load combined. A 1:2 transformer
turns ratio was used in the calculations and measurements.
OUTPUT POWER mW
2.5
0
POWER DISSIPATION
2.0
1.5
100
200
300
1.0
0.5
0
MEASURED
SINE
MEASURED
DMT
CALCULATED
Figure 41. Power Dissipation vs. Output Power (Including
Back Terminations). See Figure 7 for Test Circuit
THERMAL ENHANCEMENTS AND PCB LAYOUT
There are several ways to enhance the thermal capacity of the
CO solution. Additional thermal capacity can be created using
enhanced PCB layout techniques such as interlacing (sometimes
referred to as stitching or interconnection) of the layers immedi-
ately beneath the line driver. This technique serves to increase
the thermal mass or capacity of the PCB immediately beneath
the driver. (See AD8016-EVAL boards for an example of this
method of thermal enhancement.) A cooling fan that draws
moving air over the PCB and xDSL drivers, while not always
required, may be useful in reducing the operating temperature
of the die, allowing more drivers/square-inch within the CO
design. The AD8016, whether in a PSOP3 (ARP) or batwing
(ARB) package, can be designed to operate in the CO solution
using prudent measures to manage the power dissipation through
careful PCB design. The PSOP3 package is available for use in
designing the highest density CO solutions. Maximum heat trans-
fer to the PCB can be accomplished using the PSOP3 package
when the thermal slug is soldered to an exposed copper pad
directly beneath the AD8016. Optimum thermal performance
can be achieved in the ARE package only when the back of the
package is soldered to a PCB designed for maximum thermal
capacity (see Figure 44). Thermal experiments with the PS0P3
package were conducted without soldering the heat slug to the
PCB. Heat transfer was through physical contact only. The
following offers some insight into the AD8016 power dissipation
and relative junction temperature, the effects of PCB size and
composition on the junction-to-air thermal resistance or
JA
.
THERMAL TESTING
A wind tunnel study was conducted to determine the relationship
between thermal capacity (i.e., printed circuit board copper area),
air flow and junction temperature. Junction-to-ambient ther-
mal resistance,
JA
, was also calculated for the AD8016ARP,
AD8016ARE, and AD8016ARB packages. The AD8016 was
operated in a noninverting differential driver configuration, typical
of an xDSL application yet isolated from any other modem
components. Testing was conducted using a 1 ounce copper
board in an ambient temperature of ~24
C over air flows of
200, 150, 100, and 50 (0.200 and 400 for AD8016ARE) linear
feet per minute (LFM) and for ARP and ARB packages as well
as in still air. The four-layer PCB was designed to maximize the
area of copper on the outer two layers of the board while the
inner layers were used to configure the AD8016 in a differential
driver circuit. The PCB measured 3
4 inches in the beginning
of the study and was progressively reduced in size to approxi-
mately 2
2 inches. The testing was performed in a wind tunnel to
control air flow in units of LFM. The tunnel is approximately
11 inches in diameter.
AIR FLOW TEST CONDITIONS
DUT Power: Typical DSL DMT signal produces about 1.5 W
of power dissipation in the AD8016 package. The fully biased
(PWDN0 and PWDN1 = Logic 1) quiescent current of the
AD8016 is ~25 mA. A 1 MHz differential sine wave at an ampli-
tude of 8 V p-p/amplifier into an R
LOAD
of 100
differential
(50
per side) will produce the 1.5 W of power typical in the
AD8016 device. (See the Power Dissipation section for details.)
Thermal Resistance: The junction-to-case thermal resistance
(
JC
) of the AD8016ARB or batwing package is 8.6
C/W,
AD8016ARE is 5.6
C/W, and the AD8016ARP or PSOP3
package is 0.86
C/W. These package specifications were used in
this study to determine junction temperature based on the mea-
sured case temperature.
PCB Dimensions of a Differential Driver Circuit: Several
components are required to support the AD8016 in a differential
driver circuit. The PCB area necessary for these components (i.e.,
feedback and gain resistors, ac coupling and decoupling capaci-
tors, termination and load resistors) dictated the area of the
smallest PCB in this study, 4.7 square inches. Further reduction
in PCB area, although possible, will have consequences in terms
of the maximum operating junction temperature.
REV. A
AD8016
15
EXPERIMENTAL RESULTS
The experimental data suggests that for both packages, and a
PCB as small as 4.7 square inches, reasonable junction tempera-
tures can be maintained even in the absence of air flow. The graph
in Figure 42 shows junction temperature versus air flow for various
dimensions of 1 ounce copper PCBs at an ambient temperature
of 24
C in both the ARB and ARP packages. For the worst case
package, the AD8016ARB and the worst case PCB at 4.7 square
inches, the extrapolated junction temperature for an ambient
environment of 85
C would be approximately 132C with 0 LFM
of air flow. If the target maximum junction temperature of the
AD8016ARB is 125
C, a 4-layer PCB with 1 oz. copper covering
the outer layers and measuring 9 square inches is required
with 0 LFM of air flow.
Note that the AD8016ARE is targeted at xDSL applications
other than full-rate CO ADSL. The AD8016ARE is targeted at
g.lite and other xDSL applications where reduced power dissi-
pation can be achieved through a reduction in output power.
Extreme temperatures associated with full-rate ADSL using the
AD8016ARE should be avoided whenever possible.
AIR FLOW LFM
75
0
JUNCTION TEMPERATURE
C
70
65
60
55
50
45
40
50
100
150
200
ARP 6 SQ-IN
ARP 4.7 SQ-IN
ARP 12 SQ-IN
ARB 4.7 SQ-IN
ARB 7.125 SQ-IN
ARB 9 SQ-IN
ARB 6 SQ-IN
ARP 9 SQ-IN
+24 C AMBIENT
Figure 42. Junction Temperature vs. Air Flow
PCB AREA SQ-IN
35
4
JA
C/W
30
25
20
15
10
7
10
ARB 0 LFM
ARB 50 LFM
ARB 100 LFM
ARB 200 LFM
ARB 150 LFM
ARP 0 LFM
ARP 100 LFM
ARP 200 LFM
ARP 150 LFM
ARP 50 LFM
Figure 43. Junction-to-Ambient Thermal Resistance vs.
PCB Area
40
0
35
30
2
4
10
25
20
15
6
8
10
1
3
5
7
9
50
45
PCB AREA SQ-IN
JA
C/W
ARE 0 LFM
ARE 200 LFM
ARE 400 LFM
Figure 44. Junction-to-Ambient Thermal Resistance vs.
PCB Area
REV. A
AD8016
16
Figure 45. DMT Signal Generator Schematic
1
0
98
76
54
32
1
R4
10
9
8
7
6
5
4
3
2
1
R7
DVDD
10
9
8
7
6
5
4
3
2
1
R3
1
0
98
76
54
32
1
DVDD
R6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
P1
10
9
8
7
6
5
4
3
2
1
R5
DVDD
10
9
8
7
6
5
4
3
2
1
R1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C19
C1
C2
C25
C26
C27
C28
C29
16 PINDIP
RES PK
16
15
14
13
12
11
10
1
2
3
4
5
6
7
C30
C31
C32
C33
C34
C35
C36
16 PINDIP
RES PK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
I
OUTA
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
U1
AD9754
I
OUTB
AVDD
CT1
A
1
A
R15
49.9
CLK
JP1
AB
3
2
1
J1
TP1
EXTCLK
C7
1
F
C8
0.1
F
AVDD
A
C9
0.1
F
TP8
2
AVDD
TP11
C11
0.1
F
TP10
TP9
R16
2k
TP14
JP4
C10
0.1
F
OUT1
OUT2
TP13
R17
49.9
PDIN
J2
A
A
A
AVDD
3
JP2
TP12
TP7
A
C6
10
F
AVCC
B6
TP6
A
C5
10
F
AVEE
B5
TP19
A
AGND
B4
TP18
TP5
C4
10
F
TP4
AVDD
B3
TP2
DGND
B2
C3
10
F
TP3
DVDD
B1
J3
C12
22pF
A
J4
C13
22pF
98
76
54
32
1
R2
10
1
0
98
76
54
32
1
DVDD
R8
OUT2
OUT1
A
R
20k
49.9
A
49.9
A
10k
A
10k
A
1
F
1
F
AD8002
A
AVCC
249
A
0.1
F
AD8002
A
AVEE
A
0.1
F
226
750
750
249
DIFFERENTIAL
DMT OUTPUTS
TO TEK
AWG
2021
REV. A
AD8016
17
P4 3
AD8016
14
22
21
U1
+V
+VT
VT
AD8016
1
4
3
11
2
NC = 5, 6
AGND3,4,5
S5
TP10
TP5
C8
R11
R13
A
B
JP6
1
2
3
R24
R25
R23
1
2
3
6
4
T3
NC = 5
1:1
JP5
R15
R16
TP11
AGND3,4,5
S6
S3
S4
TP17
TP18
AD8022
AD8022
5
6
7
+VR;8
VR;4
+VR;8
VR;4
2
3
1
R1
5 WATT
1
2
R17
TP6
TP7
C11
R20
PR1
PR2
1
2
3
4
T2
10
8
9
7
TP13
TP14
TP1
C4
C5
R2
C6
C7
TP15
TP16
R4
C9
P1
1
2
3
4
5
6
7 8
TP2
R5
TP8
P4 1
P4 2
NC = 5, 6
1
2
3
4
T1
10
8
9
7
R3
TP9
C12
R21
R18
R19
+V
V
U1
+VT
VT
24
23
V
R9
R6
U2
R7
U2
R14
TP4
C10
P3 1
P3 3
P3 2
Figure 46a. Schematic AD8016ARB-EVAL
S2
R10
P2
P2
P2
1
2
3
TP3
+VL
R22
R12
JP1
JP2
R9
CW
15
10
9
16
5
6
7
8
17
18
U1
AD8016
BIAS
DGND
PDN0
PDN1
AGND
19
20
AGND
AGND
AGND
AGND
AGND
AGND
AGND
13
12
NC
+
+
TP19
TB1
3
TB1
2
TB1
1
L5
BEAD
L1
BEAD
C14
10 F
25V
C1
10 F
25V
C17
0.1 F
C15
0.1 F
C26
0.1 F
C19
0.1 F
C16
0.1 F
C25
0.1 F
TP20
+VT
VT
+
+
TB2
2
TB2
3
TB2
1
L4
BEAD
L3
BEAD
C13
10 F
25V
C3
10 F
25V
C21
0.1 F
C23
0.1 F
C24
0.1 F
C22
0.1 F
TP21
TP22
+VR
VR
+
TB3
1
TB3
2
L2
BEAD
C2
10 F
25V
C20
0.1 F
C18
0.1 F
TP12
+VL
+VT
+VR
JP3
VT
VR
JP4
TP24
TP23
TP25
TP26
TP27
TP28
TP29
TP30
NC
Figure 46b. Schematic AD8016ARB-EVAL
REV. A
AD8016
18
LAYOUT AD8016ARB-EVAL
Figure 47. Assembly
Figure 48. Layer 1
Figure 49. Power/Ground Plane
Figure 50. Layer 1
Figure 51. Silkscreen Bottom
REV. A
AD8016
19
ALP EVALUATION BOARD BILL OF MATERIALS
Qty.
Description
Vendor
Ref Desc.
5
10
F 25 V Size Tantalum Chip Capacitor
ADS# 4-7-2
C13, 13, 14
10
0.1
F 50 V 1206 Size Ceramic Chip Capacitor
ADS# 4-5-18
C1521, 2426
2
49.9
1% 1/8 W 1206 Size Chip Resistor
ADS# 3-14-26
R11, 15
2
100
1% 1/8 W 1206 Size Chip Resistor
ADS# 3-18-40
R8, 14
1
100
5% 3.0 W Metal Film Power Resistor
ADS# 3-24-1
R1
3
1.00 k
1% 1/6 W 1206 Size Chip Resistor
ADS# 3-18-11
R17R19
2
10.0 k
1% 1/6 W 1206 Size Chip Resistor
ADS# 3-18-119
R13 and 16
1
Test Point (Black) [GND]
ADS# 12-18-44
GND
2
Test Point (Brown)
ADS# 12-18-59
TP10, 11
4
Test Point (Red)
ADS# 12-18-43
TP1719, 21
2
Test Point (Orange)
ADS# 12-18-60
TP3, 15, 16
1
Test Point (Yellow)
ADS# 12-18-32
TP12
2
Test Point (Green)
ADS# 12-18-61
TP7, 9
2
Test Point (Blue)
ADS# 12-18-62
TP20, 22
2
Test Point (Violet)
ADS# 12-18-63
TP4, 5
4
Test Point (Grey)
ADS# 12-18-64
TP1, 2, 13, 14
2
Test Point (White)
ADS# 12-18-42
TP6, 8
2
3 Green Terminal Block. ONSHORE# EDZ250/3
ADS# 12-19-14
TB1, TB2
1
2 Green Terminal Block. ONSHORE# EDZ250/2
ADS# 12-19-13
TB3
5
1 Inch Center Shunt Berg# 65474-001
ADS# 11-2-38
J1J5
5
Male Header. 1 Inch Center. Berg #69157-102
ADS# 11-2-37
J1J5
5
Conn. BNC Vert. MT Telegartner # J01001A1944
ADS# 12-6-22
S2S6
1
AMP# 555154-1 MOD. JACK (SHIELDED) 6 6
DK# A 9024
P1
1
3-Pin Gold Male Header Waldom #WM 2723-ND
DK# WM 2723-ND
JP6
3
3-Pin Gold Male Locking Header Waldom #WM 2701-ND
DK# WM 2701-ND
P24
1
AD8016 ARB
ADS# AD 8016 XRP
D.U.T.
1
AD8016 SOIC Rev. A Evaluation PC Board
SIERRA/PROTO EXPRESS
Eval. PC Board
4
# 4 40
1/4" Panhead SS Machine Screw
ADS# 30-1-1
4
# 4 40
1/2" Threaded Alum. Standoffs
ADS# 30-16-2
OPTION
2
1:1.4 Turns Ratio RF Transformer from CoEv
C1374 Rev. 2
T1, T2
REV. A
AD8016
20
C01019a18/00 (rev. A)
PRINTED IN U.S.A.
20-Lead PSOP3
(RP-20A)
BOTTOM VIEW
0.2441 (6.20)
0.2283 (5.80)
0.5118 (13.00)
0.3543 (9.00)
8
0
0.1142 (2.90) MAX
2 PLACES
END VIEW
DETAIL A
0.0433 (1.10)
0.0315 (0.80)
SEATING
PLANE
0.0500
(1.27)
BSC
0.0209 (0.53)
0.0157 (0.40)
0.5709 (14.50)
0.5591 (14.20)
0.5472 (13.90)
0.4370 (11.10)
0.4331 (11.00)
0.4252 (10.80)
1
10
20
11
0.1417 (3.60)
0.1319 (3.35)
0.1220 (3.10)
0.6299 (16.00)
0.6260 (15.90)
0.6220 (15.80)
TOP VIEW
0.0433 (1.10) MAX 45
0.0433
(1.10) MAX
2 PLACES
PIN 1
SIDE VIEW
0.0394 (1.00)
0.0354 (0.90)
0.0315 (0.80)
0.1299 (3.30)
0.1240 (3.15)
0.1181 (3.00)
0.1118 (0.30)
0.0079 (0.20)
0.0039 (0.10)
0.0039 (0.10)
0.0020 (0.05)
0.0000 (0.00)
0.0126 (0.32)
0.0090 (0.23)
DETAIL A
24-Lead Batwing
(RB-24)
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
45
24
13
12
1
0.6141 (15.60)
0.5985 (15.20)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4193 (10.65)
0.3937 (10.00)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0201 (0.51)
0.0130 (0.33)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
28-Lead HTSSOP
(RE-28)
0.041 (1.05)
0.039 (1.00)
0.031 (0.80)
SEATING
PLANE
0.047
(1.20)
MAX
0.006 (0.15)
0.000 (0.00)
0.0118 (0.30)
0.0075 (0.19)
0.177 (4.50)
0.173 (4.40)
0.169 (4.30)
28
15
14
1
0.386 (9.80)
0.382 (9.70)
0.378 (9.60)
PIN 1
0.059
(1.50)
MIN
0.130 (3.30)
MIN
0.252
(6.40)
BSC
EXPOSED PAD
ON BOTTOM
0.0256 (0.65)
BSC
0.0079 (0.20)
0.0035 (0.09)
8
0
0.030 (0.75)
0.024 (0.60)
0.177 (0.45)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
PDF 
ZIP