REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8057/AD8058
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
Low Cost, High Performance
Voltage Feedback, 325 MHz Amplifiers
CONNECTION DIAGRAMS (TOP VIEWS)
FEATURES
Low Cost Single (AD8057) and Dual (AD8058)
High Speed
325 MHz, 3 dB Bandwidth (G = +1)
1000 V/ s Slew Rate
Gain Flatness 0.1 dB to 28 MHz
Low Noise
7 nV/
Hz
Low Power
5.4 mA/Amplifier Typical Supply Current @ +5 V
Low Distortion
85 dBc @ 5 MHz, R
L
= 1 k
Wide Supply Range from 3 V to 12 V
Small Packaging
AD8057 Available in SOIC-8 and SOT-23-5
AD8058 Available in SOIC-8 and SOIC
APPLICATIONS
Imaging
DVD/CD
Photodiode Preamp
A-to-D Driver
Professional Cameras
Filters
PRODUCT DESCRIPTION
The AD8057 (single) and AD8058 (dual) are very high perfor-
mance amplifiers with a very low cost. The balance between
cost and performance make them ideal for many applications.
The AD8057 and AD8058 will reduce the need to qualify a
variety of specialty amplifiers.
The AD8057 and AD8058 are voltage feedback amplifiers with
the bandwidth and slew rate normally found in current feedback
amplifiers. The AD8057 and AD8058 are low power amplifiers
having low quiescent current and a wide supply range from 3 V
to 12 V. They have noise and distortion performance required
for high-end video systems as well as dc performance param-
eters rarely found in high speed amplifiers.
The AD8057 and AD8058 are available in standard SOIC
packaging as well as tiny SOT-23-5 (AD8057) and
SOIC
(AD8058). These amplifiers are available in the industrial tem-
perature range of 40
C to +85
C.
FREQUENCY MHz
1
1000
10
GAIN dB
100
5
4
5
3
2
1
0
1
2
3
4
G = +2
G = +10
G = +5
G = +1
Figure 1. Small Signal Frequency Response
SOT-23-5 (RT-5)
+IN
+V
S
V
S
AD8057
1
2
3
5
4
IN
V
OUT
(Not to Scale)
SO-8 (SOIC)
8
7
6
5
1
2
3
4
NC
IN
+IN
NC
+V
S
V
OUT
NC
V
S
AD8057
(Not to Scale)
NC = NO CONNECT
RM-8 ( SOIC)
SO-8 (SOIC)
OUT1
IN1
+IN1
V
S
+V
S
OUT2
IN2
+IN2
1
2
3
4
8
7
6
5
(Not to Scale)
AD8058
2
REV. A
AD8057/AD8058SPECIFICATIONS
AD8057/AD8058
Parameter
Conditions
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
3 dB Bandwidth
G = +1, V
O
= 0.2 V p-p
325
MHz
G = 1, V
O
= 0.2 V p-p
95
MHz
G = +1, V
O
= 2 V p-p
175
MHz
Bandwidth for 0.1 dB Flatness
G = +1, V
O
= 0.2 V p-p
30
MHz
Slew Rate
G = +1, V
O
= 2 V Step, R
L
= 2 k
850
V/
s
G = +1, V
O
= 4 V Step, R
L
= 2 k
1150
V/
s
Settling Time to 0.1%
G = +2, V
O
= 2 V Step
30
ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
f
C
= 5 MHz, V
O
= 2 V p-p, R
L
= 1 k
85
dBc
f
C
= 20 MHz, V
O
= 2 V p-p, R
L
= 1 k
62
dBc
SFDR
f = 5 MHz, V
O
= 2 V p-p, R
L
= 150
68
dB
Third Order Intercept
f = 5 MHz, V
O
=
2.0 V p-p
35
dBm
Crosstalk, Output to Output
f = 5 MHz, G = +2
60
dB
Input Voltage Noise
f = 100 kHz
7
nV/
Hz
Input Current Noise
f = 100 kHz
0.7
pA/
Hz
Differential Gain Error
NTSC, G = +2, R
L
= 150
0.01
%
NTSC, G = +2, R
L
= 1 k
0.02
%
Differential Phase Error
NTSC, G = +2, R
L
= 150
0.15
Degree
NTSC, G = +2, R
L
= 1 k
0.01
Degree
Overload Recovery
V
IN
= 200 mV p-p, G = +1
30
ns
DC PERFORMANCE
Input Offset Voltage
1
5
mV
T
MIN
T
MAX
2.5
mV
Input Offset Voltage Drift
3
V/
C
Input Bias Current
0.5
2.5
A
T
MIN
T
MAX
3.0
A
Input Offset Current
0.75
A
Open-Loop Gain
V
O
=
2.5 V, R
L
= 2 k
50
55
dB
V
O
=
2.5 V, R
L
= 150
50
52
dB
INPUT CHARACTERISTICS
Input Resistance
10
M
Input Capacitance
+Input
2
pF
Input Common-Mode Voltage Range
R
L
= 1 k
4.0
+4.0
V
Common-Mode Rejection Ratio
V
CM
=
2.5 V
48
60
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
= 2 k
4.0
+4.0
V
R
L
= 150
3.9
V
Capacitive Load Drive
30% Overshoot
30
pF
POWER SUPPLY
Operating Range
1.5
6.0
2.5
V
Quiescent Current for AD8057
6.0
7.5
mA
Quiescent Current for AD8058
14.0
15
mA
Power Supply Rejection Ratio
V
S
=
5 V to
1.5 V
54
59
dB
Specifications subject to change without notice.
(@ T
A
= +25 C, V
S
= 5 V, R
L
= 100
, R
F
= 0
, Gain = +1,
unless otherwise noted)
3
REV. A
AD8057/AD8058
AD8057/AD8058
Parameter
Conditions
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
3 dB Bandwidth
G = +1, V
O
= 0.2 V p-p
300
MHz
G = +1, V
O
= 2 V p-p
155
MHz
Bandwidth for 0.1 dB Flatness
V
O
= 0.2 V p-p
28
MHz
Slew Rate
G = +1, V
O
= 2 V Step, R
L
= 2 k
700
V/
s
Settling Time to 0.1%
G = +2, V
O
= 2 V Step
35
ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion
f
C
= 5 MHz, V
O
= 2 V p-p, R
L
= 1 k
75
dBc
f
C
= 20 MHz, V
O
= 2 V p-p, R
L
= 1 k
54
dBc
Crosstalk, Output to Output
f = 5 MHz, G = +2
60
dB
Input Voltage Noise
f = 100 kHz
7
nV/
Hz
Input Current Noise
f = 100 kHz
0.7
pA/
Hz
Differential Gain Error
NTSC, G = +2, R
L
= 150
0.05
%
NTSC, G = +2, R
L
= 1 k
0.05
%
Differential Phase Error
NTSC, G = +2, R
L
= 150
0.10
Degree
NTSC, G = +2, R
L
= 1 k
0.02
Degree
DC PERFORMANCE
Input Offset Voltage
1
5
mV
T
MIN
T
MAX
2.5
mV
Input Offset Voltage Drift
3
V/
C
Input Bias Current
0.5
2.5
A
T
MIN
T
MAX
3.0
A
Input Offset Current
0.75
A
Open-Loop Gain
V
O
=
1.25 V, R
L
= 2 k
50
55
dB
V
O
=
1.25 V, R
L
= 150
45
52
dB
INPUT CHARACTERISTICS
Input Resistance
10
M
Input Capacitance
+Input
2
pF
Input Common-Mode Voltage Range
R
L
= 1 k
0.9 to 3.4
V
Common-Mode Rejection Ratio
V
CM
=
2.5 V
48
60
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
= 2 k
0.9 to 4.1
V
R
L
= 150
1.2 to 3.8
V
Capacitive Load Drive
30% Overshoot
30
pF
POWER SUPPLY
Operating Range
3.0
6.0
10.0
V
Quiescent Current for AD8057
5.4
7.0
mA
Quiescent Current for AD8058
13.5
14
mA
Power Supply Rejection Ratio
V
S
=
2.5 V to
1.5 V
54
58
dB
Specifications subject to change without notice.
(@ T
A
= +25 C, V
S
=
+5 V, R
L
= 100
, R
F
= 0
, Gain = +1, unless otherwise noted)
SPECIFICATIONS
AD8057/AD8058
4
REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8057/AD8058 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Internal Power Dissipation
2
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 0.8 W
SOT-23-5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . .
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . .
4.0 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range (R) . . . . . . . . . 65
C to +125
C
Operating Temperature Range (A Grade) . . 40
C to +85
C
Lead Temperature Range (Soldering 10 sec) . . . . . . . +300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead SOIC Package:
JA
= 160
C/W
5-Lead SOT-23-5 Package:
JA
= 240
C/W
8-Lead
SOIC Package:
JA
= 200
C/W
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Descriptions
Options
Brand Code
AD8057AR
40
C to +85
C
8-Lead Narrow Body SOIC
SO-8
Standard
AD8057ACHIPS
40
C to +85
C
Die
Waffle Pak
N/A
AD8057AR-REEL
40
C to +85
C
8-Lead SOIC, 13" Reel
SO-8
Standard
AD8057AR-REEL7
40
C to +85
C
8-Lead SOIC, 7" Reel
SO-8
Standard
AD8057ART-REEL
40
C to +85
C
5-Lead SOT-23, 13" Reel
RT-5
H7A
AD8057ART-REEL7
40
C to +85
C
5-Lead SOT-23, 7" Reel
RT-5
H7A
AD8058AR
40
C to +85
C
8-Lead Narrow Body SOIC
SO-8
Standard
AD8058ACHIPS
40
C to +85
C
Die
Waffle Pak
N/A
AD8058AR-REEL
40
C to +85
C
8-Lead SOIC, 13" Reel
SO-8
Standard
AD8058AR-REEL7
40
C to +85
C
8-Lead SOIC, 7" Reel
SO-8
Standard
AD8058ARM
40
C to +85
C
8-Lead
SOIC
RM-8
H8A
AD8058ARM-REEL
40
C to +85
C
8-Lead
SOIC, 13" Reel
RM-8
H8A
AD8058ARM-REEL7
40
C to +85
C
8-Lead
SOIC, 7" Reel
RM-8
H8A
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8057/AD8058 is limited by the associated rise in junction
temperature. Exceeding a junction temperature of +175
C for
an extended period can result in device failure. While the
AD8057/AD8058 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction tem-
perature (+150
C) is not exceeded under all conditions.
To ensure proper operation, it is necessary to observe the maxi-
mum power derating curves.
AMBIENT TEMPERATURE C
2.0
1.5
0
50
80
40
MAXIMUM POWER DISSIPATION Watts
30 20 10
0
10
20
30
40
50
60
70
1.0
0.5
90
T
J
= +150 C
8-LEAD SOIC PACKAGE
SOIC
SOT-23-5
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature
AD8057/AD8058
5
REV. A
LOAD RESISTANCE
4.5
4.0
0
10
100k
100
OUTPUT VOLTAGE
1k
10k
2.5
1.5
1.0
0.5
3.5
3.0
2.0
(+) OUTPUT
VOLTAGE
ABS ()
OUTPUT
Figure 3. Output Swing vs. Load Resistance
40
85
30 20 10
0
10
20
30
40
50
60
70
80
TEMPERATURE C
3.0
6.5
8.0
I
SUPPLY
mA
3.5
6.0
7.0
7.5
4.5
5.5
4.0
5.0
I
SUPPLY
@ 5V
I
SUPPLY
@ 1.5V
Figure 4. I
SUPPLY
vs. Temperature
TEMPERATURE C
5.0
1.5
0.0
40
85
30
VOLTS
20 10
0
10
20
30
40
50
60
70
80
4.5
2.0
1.0
0.5
3.5
2.5
4.0
3.0
+5V SWING R
L
= 150
+2.5V SWING R
L
= 150
+1.5V SWING R
L
= 150
Figure 5. Positive Output Voltage Swing vs.
Temperature
Typical Performance Characteristics
40
85
30 20 10
0
10
20
30
40
50
60
70
80
TEMPERATURE C
0.0
3.5
5.0
VOLTS
0.5
3.0
4.0
4.5
1.5
2.5
1.0
2.0
5V SWING R
L
= 150
2.5V SWING R
L
= 150
1.5V SWING R
L
= 150
Figure 6. Negative Output Voltage Swing vs.
Temperature
TEMPERATURE C
6
2
6
40 30
V
OS
mV
20 10
0
10
20
30
40
50
60
70
80
4
2
0
4
V
OS
@ 5V
V
OS
@ 1.5V
Figure 7. V
OS
vs. Temperature
TEMPERATURE C
3.5
1.5
0
40 30
A
VOL
mV/V
20 10
0
10
20
30
40
50
60
70
80
0.5
2.5
2.0
3.0
A
VOL
@ 2.5V
A
VOL
@ 5V
85
1.0
Figure 8. Open-Loop Gain vs. Temperature
AD8057/AD8058
6
REV. A
Typical Performance Characteristics
40
85
30 20 10
0
10
20
30
40
50
60
70
80
TEMPERATURE C
0.00
0.40
0.60
I
B
A
0.50
0.20
0.30
0.10
0.80
0.70
+I
B
@ 5V
+I
B
@ 2.5V
I
B
@ 5V
I
B
@ 1.5V
I
B
@ 2.5V
+I
B
@ 1.5V
Figure 9. Input Bias Current vs. Temperature
40
85
30 20 10
0
10
20
30
40
50
60
70
80
TEMPERATURE C
4
0
PSRR mV/V
1
3
2
PSRR @ 1.5V 5V
Figure 10. PSRR vs. Temperature
FREQUENCY MHz
0
10
60
0.1
1000
1
PSRR dB
10
100
20
30
50
40
+PSRR V
S
= 2.5V
PSRR V
S
= 2.5V
Figure 11.
PSRR vs. Frequency
0.01 F
0.001 F
4.7 F
V
S
50
V
IN
HP8130A
PULSE
GENERATOR
T
R
/T
F
= 1ns
AD8057/58
0.001 F
0.01 F
4.7 F
1k
+V
S
V
OUT
Figure 12. Test Circuit G = +1, R
L
= 1 k
for Figures 13
and 14
100mV
20mV/
DIV
100mV
4ns/DIV
Figure 13. Small Signal Step Response G = +1, R
L
= 1 k
,
V
S
=
5 V
5V
1V/DIV
5V
4ns/DIV
Figure 14. Large Signal Step Response G = +1, R
L
= 1 k
,
V
S
=
5.0 V
AD8057/AD8058
7
REV. A
0.01 F
0.001 F
4.7 F
V
S
1k
50
V
IN
HP8130A
PULSE
GENERATOR
T
R
/T
F
= 1ns
AD8057/58
0.001 F
0.01 F
4.7 F
1k
+V
S
1k
V
OUT
Figure 15. Test Circuit G = 1, R
L
= 1 k
for Figures 16
and 17
100mV
20mV/
DIV
100mV
4ns/DIV
0V
Figure 16. Small Signal Step Response G = 1, R
L
= 1 k
5V
1V/DIV
5V
4ns/DIV
Figure 17. Large Signal Step Response G = 1, R
L
= 1 k
FREQUENCY MHz
1
1000
10
GAIN dB
100
5
4
5
3
2
1
0
1
2
3
4
G = +2
G = +10
G = +5
G = +1
Figure 18. Small Signal Frequency Response,
V
OUT
= 0.2 V p-p
FREQUENCY MHz
1
1000
10
GAIN dB
100
5
4
5
3
2
1
0
1
2
3
4
G = +2
G = +10
G = +5
G = +1
Figure 19. Large Signal Frequency Response, V
OUT
= 2 V p-p
FREQUENCY MHz
1
1000
10
GAIN dB
100
5
4
5
3
2
1
0
1
2
3
4
G = 2
G = 10
G = 5
G = 1
Figure 20. Large Signal Frequency Response
AD8057/AD8058
8
REV. A
FREQUENCY MHz
1
1000
10
GAIN dB
100
0.5
0.4
0.5
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
V
OUT
= 0.2V
G = +2
R
L
= 1.0k
R
F
= 1.0k
Figure 21. 0.1 dB Flatness G = +2
FREQUENCY MHz
0.1
100
1
DISTORTION dBc
10
50
60
70
80
90
100
110
THD
2ND
3RD
Figure 22. Distortion vs. Frequency, R
L
= 150
V
OUT
V p-p
40
50
80
0.0
4.0
0.4
DISTORTION dBc
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
60
70
20MHz
5MHz
Figure 23. Distortion vs. V
OUT
@ 20 MHz, 5 MHz, R
L
= 150
,
V
S
=
5.0 V
V
OUT
V p-p
5.0
4.5
0.0
0
4
1
2
3
3.0
1.5
1.0
0.5
4.0
3.5
2.0
2.5
RISE TIME AND FALL TIME ns
RISE TIME
FALL TIME
Figure 24. Rise Time and Fall Time vs. V
OUT
. G = +1,
R
L
= 1 k
, R
F
= 0
V
OUT
V p-p
5
4
0
0
4
1
RISE TIME AND FALL TIME ns
2
3
3
2
1
RISE TIME
FALL TIME
Figure 25. Rise Time and Fall Time vs. V
OUT
. G = +2,
R
L
= 100
, R
F
= 402
0.4%
0.3%
0.2%
0.1%
0.0%
0.1%
0.2%
0.3%
0.4%
0
10 20
30 40
50 60
V
OUT
= 1V TO + 1V OR +1V TO 1V
G = +2
R
L
= 100 /1k
TIME ns
Figure 26. Settling Time
AD8057/AD8058
9
REV. A
500mV/
DIV
0V
20ns/DIV
V
S
= 2.5V
R
L
= 1k
G = +1
INPUT SIGNAL
OUTPUT RESPONSE
2.5V
Figure 27. Input Overload Recovery, V
S
=
2.5 V
5.0V
1V/DIV
0V
20ns/DIV
V
S
= 5.0V
R
L
= 1k
G = +1
INPUT SIGNAL 5V
OUTPUT SIGNAL = 4.0V
Figure 28. Output Overload Recovery, V
S
=
5.0 V
FREQUENCY MHz
0.1
100
1
CMRR dB
10
0
10
70
20
30
40
50
60
Figure 29. CMRR vs. Frequency
1.8V
20ns/DIV
V
S
= 2.5V
R1 = 1k
G = +4
INPUT SIGNAL = 0.6V
OUTPUT SIGNAL 1.7V
200mV/
DIV
Figure 30. Output Overload Recovery, V
S
=
2.5 V
4.5V
500mV/
DIV
20ns/DIV
37ns
V
S
= 5.0V
R1 = 1k
G = +4
Figure 31. Output Overload Recovery, V
S
=
5.0 V
FREQUENCY MHz
0
20
120
0.1
1
CROSSTALK dB
10
100
60
80
100
40
SIDE B DRIVEN
SIDE A DRIVEN
Figure 32. Crosstalk (Output-to-Output) vs. Frequency
AD8057/AD8058
10
REV. A
0.015
0.015
0.010
0.005
0.000
0.005
0.010
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.14
1st
11th
6th
2nd
7th
3rd
8th
4th
9th
5th
10th
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.02
0.00
0.13
0.07
0.00
0.09
0.02
0.10
0.03
0.11
0.05
0.12
DIFFERENTIAL PHASE (Degrees)
DIFFERENTIAL GAIN (%)
V
S
= 5.0V
R
L
= 150
V
S
= 5.0V
R
L
= 150
a.
0.015
0.015
0.010
0.005
0.000
0.005
0.010
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.14
1st
11th
6th
2nd
7th
3rd
8th
4th
9th
5th
10th
0.00
0.01
0.00
0.00
0.00
0.00
0.00
0.01
0.00
0.01
0.01
0.02
0.00
0.01`
0.00
0.00
0.01
0.00
0.01
0.00
0.01
0.00
0.01
DIFFERENTIAL PHASE (Degrees)
DIFFERENTIAL GAIN (%)
V
S
= 5.0V
R
L
= 1k
V
S
= 5.0V
R
L
= 1k
b.
Figure 33. Differential Gain and Differential Phase One
Back Terminated Load (150
) (Video Op Amps Only)
FREQUENCY MHz
180
135
90
0.01
1000
0.1
PHASE Degrees
1
10
100
45
0
45
90
80
60
40
20
0
20
OPEN-LOOP GAIN dB
Figure 34. Open-Loop Gain and Phase vs. Frequency
0.01
0.05
0.00
0.01
0.02
0.03
0.04
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.14
1st
11th
6th
2nd
7th
3rd
8th
4th
9th
5th
10th
0.00
0.04
0.01
0.00
0.01
0.00
0.01
0.01
0.02
0.01
0.03
0.02
0.00
0.13
0.09
0.01
0.11
0.03
0.12
0.05
0.12
0.07
0.13
DIFFERENTIAL PHASE (Degrees)
DIFFERENTIAL GAIN (%)
V
S
= +5V
R
L
= 150
V
S
= +5V
R
L
= 150
a.
0.01
0.05
0.00
0.01
0.02
0.03
0.04
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.14
1st
11th
6th
2nd
7th
3rd
8th
4th
9th
5th
10th
0.00
0.05
0.01
0.01
0.02
0.00
0.02
0.01
0.03
0.01
0.04
0.02
0.00
0.02
0.00
0.00
0.00
0.00
0.00
0.00
0.01
0.00
0.01
DIFFERENTIAL PHASE (Degrees)
DIFFERENTIAL GAIN (%)
V
S
= +5V
R
L
= 1k
V
S
= +5V
R
L
= 1k
b.
Figure 35. Differential Gain and Differential Phase
a. R
L
= 150
, b. R
L
= 1 k
FREQUENCY Hz
100
10
0.1
10
100M
100
V
NOISE
nV/
Hz
1k
10k
100k
1
1M
10M
Figure 36. Voltage Noise vs. Frequency
AD8057/AD8058
11
REV. A
FREQUENCY Hz
100
10
0.1
10
100M
100
I
NOISE
pA/
Hz
1k
10k
100k
1
1M
10M
Figure 37. Current Noise vs. Frequency
FREQUENCY MHz
100
10
0.1
0.1
1000
1
Z
OUT
10
100
1
Figure 38. Output Impedance vs. Frequency
APPLICATIONS
Driving Capacitive Loads
When driving a capacitive load, most op amps will exhibit over-
shoot in their pulse response.
Figure 39 shows the relationship between the capacitive load that
results in 30% overshoot and closed loop gain of an AD8058. It can
be seen that, under the Gain = +2 condition, the device is stable
with capacitive loads of up to 69 pF.
In general, to minimize peaking or to ensure device stability for
larger values of capacitive loads, a small series resistor, R
S
, can
be added between the op amp output and the load capacitor, C
L
,
as shown in Figure 40.
For the setup shown in Figure 40, the relationship between R
S
and C
L
was empirically derived and is shown in Table I.
CLOSED-LOOP GAIN
500
400
0
1
5
2
C
L
pF
3
4
300
200
100
R
S
= 2.4
R
S
= 0
Figure 39. Capacitive Load Drive vs. Closed-Loop Gain
Table I. Recommended Value for Resistors R
S
, R
F
, R
G
vs.
Capacitive Load, C
L
, Which Results in 30% Overshoot
Gain
R
F
R
G
C
L
w/R
S
= 0
C
L
w/R
S
= 2.4
1
100
11
13
2
100
100
51
69
3
100
50
104
153
4
100
33.2
186
270
5
100
25
245
500
10
100
11
870
1580
2.5V
R
G
50k
V
IN
= 200mV p-p
AD8058
0.1 F
10 F
0.1 F
10 F
+2.5V
R
F
C
L
R
S
V
OUT
FET PROBE
Figure 40. Capacitive Load Drive Circuit
100mV
50ns/DIV
200mV
100mV
200mV
+ OVERSHOOT
29.0%
100mV
Figure 41. Typical Pulse Response with C
L
= 65 pF,
Gain = +2, and V
S
=
2.5 V
AD8057/AD8058
12
REV. A
Video Filter
Some composite video signals that are derived from a digital
source contain some clock feedthrough that can cause problems
with downstream circuitry. This clock feedthrough is usually at
27 MHz, which is a standard clock frequency for both NTSC
and PAL video systems. A filter that passes the video band and
rejects frequencies at 27 MHz can be used to remove these
frequencies from the video signal.
Figure 42 shows a circuit that uses an AD8057 to create a single
+5 V supply, three-pole Sallen-Key filter. This circuit uses a
single RC pole in front of a standard two-pole active section. To
shift the dc operating point to midsupply, ac coupling is pro-
vided by R4, R5 and C4.
2
3
0.1 F
+
10 F
AD8057
7
4
6
+5V
+5V
R4
10k
R5
10k
C4
0.1 F
R3
49.9
R2
499
C1
100pF
R1
200
R
F
1k
C2
680pF
C3
36pF
Figure 42. Low-Pass Filter for Video
Figure 43 shows a frequency sweep of this filter. The response is
down 3 dB at 5.7 MHz, so it passes the video band with little
attenuation. The rejection at 27 MHz is 42 dB, which provides
more than a factor of 100 in suppression of the clock compo-
nents at this frequency.
FREQUENCY Hz
LOG MAGNITUDE dB
40
100k
100M
0
1M
10M
10
20
30
50
60
70
80
90
10
Figure 43. Video Filter Response
Differential A-to-D Driver
As system supply voltages are dropping, many A-to-D convert-
ers provide differential analog inputs to increase the dynamic
range of the input signal, while still operating on a low supply
voltage. Differential driving can also reduce second and other
even-order distortion products.
Analog Devices offers an assortment of 12- and 14-bit high
speed converters that have differential inputs and can be run
from a single +5 V supply. These include the AD9220, AD9221,
AD9223, AD9224 and AD9225 at 12 bits, and the AD9240,
AD9241, and AD9243 at 14 bits. Although these devices can
operate over a range of common-mode voltages at their analog
inputs, they work best when the common-mode voltage at the
input is at the midsupply or 2.5 V.
Op amp architectures that require upwards of 2 V of headroom
at the output have significant problems when trying to drive
such A-to-Ds while operating with a +5 V positive supply. The
low headroom output design of the AD8057 and AD8058 make
them ideal for driving these types of A-to-D converters.
The AD8058 can be used to make a dc-coupled, single-ended-
to-differential driver for one of these A-to-Ds. Figure 44 is a
schematic of such a circuit for driving an AD9225, a 12-bit,
25 MSPS A-to-D converter.
2
3
0.1 F
+
10 F
8
1
+5V
1k
1k
AD8058
1k
1k
1k
6
1k
5
7
1k
0.1 F
+
10 F
1k
5V
4
V
IN
0V
50
50
VINB
VINA
AD9225
+5V
0.1 F
+
10 F
REF
+2.5V
AD8058
Figure 44. Schematic Circuit for Driving AD9225
In this circuit, one of the op amps is configured in the inverting
mode, while the other is in the noninverting mode. However, to
provide better bandwidth matching, each op amp is configured
for a noise gain of 2. The inverting op amp is configured for a
gain of 1, while the noninverting op amp is configured for a
gain of +2. Each of these produces a noise gain of 2, which is
only determined by the inverse of the feedback ratio. The input
signal to the noninverting op amp is divided by 2 in order to
normalize its level and make it equal to the inverting output.
AD8057/AD8058
13
REV. A
For zero volts input, the outputs of the op amps want to be at
2.5 V, which is the midsupply level of the A-to-D. This is ac-
complished by first taking the 2.5 V reference output of the
A-to-D and dividing it by two by a pair of 1 k
resistors. The
resulting 1.25 V is applied to each op amp's positive input. This
voltage is then multiplied by the gain of 2 of the op amps to
provide a 2.5 V level at each output.
The assumption for this circuit is that the input signal is bipolar
with respect to round and the circuit must be dc coupled. This
implies the existence of a negative supply elsewhere in the system.
This circuit uses 5 V as the negative supply for the AD8058.
If the AD8058 negative supply were tied to ground, there would
be a problem at the input of the noninverting op amp. The
input common-mode voltage can only go to within 1 V of the
negative rail. Since this circuit requires that the positive inputs
operate with a 1.25 V bias, there is not enough room to swing
this voltage in the negative direction. The inverting stage does
not have this problem, because its common-mode input voltage
remains fixed at 1.25 V. If dc-coupling is not required, various
ac-coupling techniques can be used to eliminate this problem.
Layout
The AD8057 and AD8058 are high speed op amps and should
be used in a board layout that follows standard high speed de-
sign rules. All the signal traces should be as short and direct as
possible. In particular, the parasitic capacitance on the inverting
input of each device should be kept to a minimum to avoid
excessive peaking and other undesirable performance.
The power supplies should be bypassed very close to the power
pins of the package with 0.1
F in parallel with a larger, approxi-
mately 10
F tantalum capacitor. These capacitors should be
connected to a ground plane that is either on an inner layer, or
fills the area of the board that is not used for other signals.
AD8057/AD8058
14
REV. A
8-Lead SOIC
(RM-8)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33
27
0.120 (3.05)
0.112 (2.84)
8-Lead Narrow Body SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
4
1
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
5-Lead Surface Mount (SOT-23)
(RT-5)
0.1181 (3.00)
0.1102 (2.80)
PIN 1
0.0669 (1.70)
0.0590 (1.50)
0.1181 (3.00)
0.1024 (2.60)
1
3
4
5
0.0748 (1.90)
BSC
0.0374 (0.95) BSC
2
0.0079 (0.20)
0.0031 (0.08)
0.0217 (0.55)
0.0138 (0.35)
10
0
0.0197 (0.50)
0.0138 (0.35)
0.0059 (0.15)
0.0019 (0.05)
0.0512 (1.30)
0.0354 (0.90)
SEATING
PLANE
0.0571 (1.45)
0.0374 (0.95)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3388a09/99
PRINTED IN U.S.A.
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