REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD8061/AD8062/AD8063
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
Low-Cost, 300 MHz
Rail-to-Rail Amplifiers
FEATURES
Low Cost
Single (AD8061), Dual (AD8062)
Single with Disable (AD8063)
Rail-to-Rail Output Swing
6 mV V
OS
High Speed
300 MHz, 3 dB Bandwidth (G = 1)
800 V/ s Slew Rate
8.5 nV/
Hz @ 5 V
35 ns Settling Time to 0.1% with 1 V Step
Operates on 2.7 V to 8 V Supplies
Input Voltage Range = 0.2 V to +3.2 V with V
S
= 5
Excellent Video Specs (R
L
= 150 , G = 2)
Gain Flatness 0.1 dB to 30 MHz
0.01% Differential Gain Error
0.04 Differential Phase Error
35 ns Overload Recovery
Low Power
6.8 mA/Amplifier Typical Supply Current
AD8063 400 A when Disabled
Small Packaging
AD8061 Available in SOIC-8 and SOT-23-5
AD8062 Available in SOIC-8 and SOIC
AD8063 Available in SOIC-8 and SOT-23-6
APPLICATIONS
Imaging
Photodiode Preamp
Professional Video and Cameras
Hand Sets
DVD/CD
Base Stations
Filters
A-to-D Driver
PRODUCT DESCRIPTION
The AD8061, AD8062, and AD8063 are rail-to-rail output volt-
age feedback amplifiers offering ease of use and low cost. They
have bandwidth and slew rate typically found in current feed-
back amplifiers. All have a wide input common-mode voltage
range and output voltage swing, making them easy to use on
single supplies as low as 2.7 V.
Despite being low cost, the AD8061, AD8062, and AD8063
provide excellent overall performance. For video applications
their differential gain and phase errors are 0.01% and 0.04
into a 150
load, along with 0.1 dB flatness out to 30 MHz.
Additionally, they offer wide bandwidth to 300 MHz along
with 800 V/
s slew rate.
R
F
= 0
FREQUENCY MHz
3
12
1
1000
NORMALIZED GAIN dB
6
100
10
0
3
9
V
O
= 0.2V p-p
R
L
= 1k
V
BIAS
= 1V
R
F
OUT
IN
V
BIAS
50
R
L
R
F
= 50
Figure 1. Small Signal Response, R
F
= 0
, 50
The AD8061, AD8062, and AD8063 offer a typical low power
of 6.8 mA/amplifier, while being capable of delivering up to
50 mA of load current. The AD8063 has a power-down disable
feature that reduces the supply current to 400
A. These features
make the AD8063 ideal for portable and battery-powered
applications where size and power are critical.
CONNECTION DIAGRAMS
(Top Views)
SOIC-8 (R)
SOT-23-6 (RT)
SOT-23-5 (RT)
+IN
+V
S
V
S
1
2
3
4
IN
V
OUT
5
AD8061
(Not to Scale)
SOIC-8 (R) and SOIC (RM)
V
OUT1
IN1
+IN1
V
S
+V
S
V
OUT2
IN2
+IN2
1
2
3
4
8
7
6
5
(Not to Scale)
AD8062
8
7
6
5
1
2
3
4
NC
IN
+IN
DISABLE
(AD8063 ONLY)
+V
S
V
OUT
NC
V
S
AD8061/
AD8063
NC = NO CONNECT
(Not to Scale)
+IN
+V
S
V
S
AD8063
1
2
3
6
4
IN
V
OUT
(Not to Scale)
5
DISABLE
2
REV. C
AD8061/AD8062/AD8063SPECIFICATIONS
(T
A
= 25 C, V
S
= 5 V, R
L
= 1 k
, V
O
= 1 V,
unless otherwise noted)
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Small Signal Bandwidth
G = 1, V
O
= 0.2 V p-p
150
320
MHz
G = 1, +2, V
O
= 0.2 V p-p
60
115
MHz
3 dB Large Signal Bandwidth
G = 1, V
O
= 1 V p-p
280
MHz
Bandwidth for 0.1 dB Flatness
G = 1, V
O
= 0.2 V p-p
30
MHz
Slew Rate
G = 1, V
O
= 2 V Step, R
L
= 2 k
500
650
V/
s
G = 2, V
O
= 2 V Step, R
L
= 2 k
300
500
V/
s
Settling Time to 0.1%
G = 2, V
O
= 2 V Step
35
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
f
C
= 5 MHz, V
O
= 2 V p-p, R
L
= 1 k
77
dBc
f
C
= 20 MHz, V
O
= 2 V p-p, R
L
= 1 k
50
dBc
Crosstalk, Output to Output
f = 5 MHz, G = 2, AD8062
90
dBc
Input Voltage Noise
f = 100 kHz
8.5
nV/
Hz
Input Current Noise
f = 100 kHz
1.2
pA/
Hz
Differential Gain Error (NTSC)
G = 2, R
L
= 150
0.01
%
Differential Phase Error (NTSC)
G = 2, R
L
= 150
0.04
Degree
Third Order Intercept
f = 10 MHz
28
dBc
SFDR
f = 5 MHz
62
dB
DC PERFORMANCE
Input Offset Voltage
1
6
mV
T
MIN
to T
MAX
2
6
mV
Input Offset Voltage Drift
3.5
V/C
Input Bias Current
3.5
9
A
T
MIN
to T
MAX
4
9
A
Input Offset Current
0.3
4.5
A
Open-Loop Gain
V
O
= 0.5 V to 4.5 V, R
L
= 150
68
70
dB
V
O
= 0.5 V to 4.5 V, R
L
= 2 k
74
90
dB
INPUT CHARACTERISTICS
Input Resistance
13
M
Input Capacitance
1
pF
Input Common-Mode Voltage Range
0.2 to +3.2
V
Common-Mode Rejection Ratio
V
CM
= 0.2 V to +3.2 V
62
80
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing--Load Resistance
R
L
= 150
0.3
0.1 to 4.5
4.75
V
Is Terminated at Midsupply
R
L
= 2 k
0.25
0.1 to 4.9
4.85
V
Output Current
V
O
= 0.5 V to 4.5 V
25
50
mA
Capacitive Load Drive, V
OUT
= 0.8 V
30% Overshoot: G = 1, R
S
= 0
25
pF
G = 2, R
S
= 4.7
300
pF
POWER-DOWN DISABLE
Turn-On Time
40
ns
Turn-Off Time
300
ns
DISABLE Voltage--Off
2.8
V
DISABLE Voltage--On
3.2
V
POWER SUPPLY
Operating Range
2.7
5
8
V
Quiescent Current per Amplifier
6.8
9.5
mA
Supply Current when Disabled
0.4
mA
(AD8063 Only)
Power Supply Rejection Ratio
V
S
= 2.7 V to 5 V
72
80
dB
Specifications subject to change without notice.
3
REV. C
AD8061/AD8062/AD8063
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Small Signal Bandwidth
G = 1, V
O
= 0.2 V p-p
150
300
MHz
G = 1, +2, V
O
= 0.2 V p-p
60
115
MHz
3 dB Large Signal Bandwidth
G = 1, V
O
= 1 V p-p
250
MHz
Bandwidth for 0.1 dB Flatness
G = 1, V
O
= 0.2 V p-p
30
MHz
Slew Rate
G = 1, V
O
= 1 V Step, R
L
= 2 k
190
280
V/
s
G = 2, V
O
= 1.5 V Step, R
L
= 2 k
180
230
V/
s
Settling Time to 0.1%
G = 2, V
O
= 1 V Step
40
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
f
C
= 5 MHz, V
O
= 2 V p-p, R
L
= 1 k
60
dBc
f
C
= 20 MHz, V
O
= 2 V p-p, R
L
= 1 k
44
dBc
Crosstalk, Output to Output
f = 5 MHz, G = 2
90
dBc
Input Voltage Noise
f = 100 kHz
8.5
nV/
Hz
Input Current Noise
f = 100 kHz
1.2
pA/
Hz
DC PERFORMANCE
Input Offset Voltage
1
6
mV
T
MIN
to T
MAX
2
6
mV
Input Offset Voltage Drift
3.5
V/C
Input Bias Current
3.5
8.5
A
T
MIN
to T
MAX
4
8.5
A
Input Offset Current
0.3
4.5
A
Open-Loop Gain
V
O
= 0.5 V to 2.5 V, R
L
= 150
66
70
dB
V
O
= 0.5 V to 2.5 V, R
L
= 2 k
74
90
dB
INPUT CHARACTERISTICS
Input Resistance
13
M
Input Capacitance
1
pF
Input Common-Mode Voltage Range
0.2 to +1.2
V
Common-Mode Rejection Ratio
V
CM
= 0.2 V to +1.2 V
80
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
= 150
0.3
0.1 to 2.87
2.85
V
R
L
= 2 k
0.3
0.1 to 2.9
2.90
V
Output Current
V
O
= 0.5 V to 2.5 V
25
mA
Capacitive Load Drive, V
OUT
= 0.8 V
30% Overshoot, G = 1, R
S
= 0
,
25
pF
G = 2, R
S
= 4.7
300
pF
POWER-DOWN DISABLE
Turn-On Time
40
ns
Turn-Off Time
300
ns
DISABLE Voltage--Off
0.8
V
DISABLE Voltage--On
1.2
V
POWER SUPPLY
Operating Range
2.7
3
V
Quiescent Current per Amplifier
6.8
9
mA
Supply Current when Disabled
0.4
mA
(AD8063 Only)
Power Supply Rejection Ratio
72
80
dB
Specifications subject to change without notice.
(T
A
= 25 C, V
S
= 3 V, R
L
= 1 k
, V
O
= 1 V, unless otherwise noted)
SPECIFICATIONS
4
REV. C
AD8061/AD8062/AD8063SPECIFICATIONS
(T
A
= 25 C, V
S
= 2.7 V, R
L
= 1 k
, V
O
= 1 V,
unless otherwise noted)
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Small Signal Bandwidth
G = 1, V
O
= 0.2 V p-p
150
300
MHz
G = 1, +2, V
O
= 0.2 V p-p
60
115
MHz
G = 1, V
O
= 1 V p-p
230
MHz
Bandwidth for 0.1 dB Flatness
G = 1, V
O
= 0.2 V p-p, V
O
DC = 1 V
30
MHz
Slew Rate
G = 1, V
O
= 0.7 V Step, R
L
= 2 k
110
150
V/
s
G = 2, V
O
= 1.5 V Step, R
L
= 2 k
95
130
V/
s
Settling Time to 0.1%
G = 2, V
O
= 1 V Step
40
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
f
C
= 5 MHz, V
O
= 2 V p-p, R
L
= 1 k
60
dBc
f
C
= 20 MHz, V
O
= 2 V p-p, R
L
= 1 k
44
dBc
Crosstalk, Output to Output
f = 5 MHz, G = 2
90
dBc
Input Voltage Noise
f = 100 kHz
8.5
nV/
Hz
Input Current Noise
f = 100 kHz
1.2
pA/
Hz
DC PERFORMANCE
Input Offset Voltage
1
6
mV
T
MIN
to T
MAX
2
6
mV
Input Offset Voltage Drift
3.5
V/C
Input Bias Current
3.5
A
T
MIN
to T
MAX
4
8.5
A
Input Offset Current
0.3
4.5
A
Open-Loop Gain
V
O
= 0.5 V to 2.2 V, R
L
= 150
63
70
dB
V
O
= 0.5 V to 2.2 V, R
L
= 2 k
74
90
dB
INPUT CHARACTERISTICS
Input Resistance
13
M
Input Capacitance
1
pF
Input Common-Mode Voltage Range
0.2 to +0.9
V
Common-Mode Rejection Ratio
V
CM
= 0.2 V to +0.9 V
80
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
= 150
0.3
0.1 to 2.55
2.55
V
R
L
= 2 k
0.25
0.1 to 2.6
2.6
V
Output Current
V
O
= 0.5 V to 2.2 V
25
mA
Capacitive Load Drive, V
OUT
= 0.8 V
30% Overshoot: G = 1, R
S
= 0
,
25
pF
G = 2, R
S
= 4.7
300
pF
POWER-DOWN DISABLE
Turn-On Time
40
ns
Turn-Off Time
300
ns
DISABLE Voltage--Off
0.5
V
DISABLE Voltage--On
0.9
V
POWER SUPPLY
Operating Range
2.7
8
V
Quiescent Current per Amplifier
6.8
8.5
mA
Supply Current when Disabled
0.4
mA
(AD8063 Only)
Power Supply Rejection Ratio
80
dB
Specifications subject to change without notice.
AD8061/AD8062/AD8063
5
REV. C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8061/AD8062/AD8063 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Internal Power Dissipation
2
Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 0.8 W
SOT-23-5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W
SOT-23-6 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 W
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W
Input Voltage (Common-Mode) (V
S
0.2 V) to (+V
S
1.8 V)
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range R, RM, SOT-23-5,
SOT-23-6 . . . . . . . . . . . . . . . . . . . . . . . . 65
C to +125C
Operating Temperature Range . . . . . . . . . . . 40
C to +85C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead SOIC Package:
JA
= 160
C/W;
JC
= 56
C/W
5-Lead SOT-23-5 Package:
JA
= 240
C/W;
JC
= 92
C/W
6-Lead SOT-23-6 Package:
JA
= 230
C/W;
JC
= 92
C/W
8-Lead
SOIC Package:
JA
= 200
C/W;
JC
= 44
C/W.
ORDERING GUIDE
Temperature
Package
Package
Branding
Model
Range
Description
Option
Information
AD8061AR
40
C to +85C
8-Lead SOIC
SO-8
AD8061AR-REEL
40
C to +85C
8-Lead SOIC
13-Inch Tape and Reel
AD8061AR-REEL7
40
C to +85C
8-Lead SOIC
7-Inch Tape and Reel
AD8061ART-REEL
40
C to +85C
5-Lead SOT-23
RT-5, 13-Inch Tape and Reel
HGA
AD8061ART-REEL7
40
C to +85C
5-Lead SOT-23
RT-5, 7-Inch Tape and Reel
HGA
AD8062AR
40
C to +85C
8-Lead SOIC
SO-8
AD8062AR-REEL
40
C to +85C
8-Lead SOIC
13-Inch Tape and Reel
AD8062AR-REEL7
40
C to +85C
8-Lead SOIC
7-Inch Tape and Reel
AD8062ARM
40
C to +85C
8-Lead
SOIC
RM-8
HCA
AD8062ARM-REEL
40
C to +85C
8-Lead
SOIC
13-Inch Tape and Reel
HCA
AD8062ARM-REEL7
40
C to +85C
8-Lead
SOIC
7-Inch Tape and Reel
HCA
AD8063AR
40
C to +85C
8-Lead SOIC
SO-8
AD8063AR-REEL
40
C to +85C
8-Lead SOIC
13-Inch Tape and Reel
AD8063AR-REEL7
40
C to +85C
8-Lead SOIC
7-Inch Tape and Reel
AD8063ART-REEL
40
C to +85C
6-Lead SOT-23
RT-6, 13-Inch Tape and Reel
HHA
AD8063ART-REEL7
40
C to +85C
6-Lead SOT-23
RT-6, 7-Inch Tape and Reel
HHA
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD806x
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150
C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change
in the stresses exerted on the die by the package. Exceeding a
junction temperature of 175
C for an extended period can result
in device failure. While the AD806x is internally short circuit
protected, this may not be sufficient to guarantee that the
maximum junction temperature (150
C) is not exceeded under
all conditions.
To ensure proper operation, it is necessary to observe the
maximum power derating curves.
AMBIENT TEMPERATURE C
2.0
1.0
0
50 40
MAXIMUM POWER DISSIPATION
Watts
30
70
80
90
1.5
0.5
60
50
40
30
0
10
20
20
10
T
J
= 150 C
SOIC
SOT-23-5, -6
8-LEAD SOIC
PACKAGE
Figure 2. Plot of Maximum Power Dissipation vs.
Temperature for AD8061/AD8062/AD8063
LOAD CURRENT mA
0
0
10
VOLTAGE DIFFERENTIAL FROM V
S
0.2
+V
OUT
@ +85 C
+V
OUT
@ +25 C
+V
OUT
@ 40 C
V
OUT
@ +85 C
V
OUT
@ +25 C
V
OUT
@ 40 C
0.4
0.6
0.8
1.0
1.2
20
30
40
50
60
70
80
90
TPC 1. Output Saturation Voltage vs. Load Current
SINGLE POWER SUPPLY Voltage
18
8
0
2
8
3
POWER SUPPLY CURRENT
mA
4
5
6
7
16
14
12
10
6
4
2
AD8062
AD8061
TPC 2. I
SUPPLY
vs. V
SUPPLY
R
F
= 0
FREQUENCY MHz
3
12
1
1000
NORMALIZED GAIN
dB
6
100
10
0
3
9
V
O
= 0.2V p-p
R
L
= 1k
V
BIAS
= 1V
R
F
OUT
IN
V
BIAS
50
R
L
R
F
= 50
TPC 3. Small Signal Response, R
F
= 0
, 50
FREQUENCY MHz
3
12
1
1000
NORMALIZED GAIN
dB
6
100
10
0
3
9
G = 1
G = 2
G = 5
V
O
= 0.2V p-p
R
L
= 1k
V
BIAS
= 1V
TPC 4. Small Signal Frequency Response
FREQUENCY MHz
3
12
1
1000
NORMALIZED GAIN
dB
6
100
10
0
3
9
G = 2
G = 5
G = 1
V
O
= 1.0V p-p
R
L
= 1k
V
BIAS
= 1V
TPC 5. Large Signal Frequency Response
G = 1
FREQUENCY MHz
3
12
1
1000
NORMALIZED GAIN
dB
6
100
10
0
3
9
G = 2
G = 5
V
S
= 5V
V
O
= 0.2V p-p
R
L
= 1k
V
BIAS
= 1V
R
F
OUT
IN
V
BIAS
50
R
L
TPC 6. Small Signal Frequency Response
AD8061/AD8062/AD8063Typical Performance Characteristics
6
REV. C
AD8061/AD8062/AD8063
7
REV. C
FREQUENCY MHz
3
12
1
1000
NORMALIZED GAIN
dB
6
100
10
0
3
9
G = 1
G = 2
G = 5
V
S
= 5V
V
O
= 1V p-p
R
L
= 1k
V
BIAS
= 1V
TPC 7. Large Signal Frequency Response
FREQUENCY MHz
0.1
0.5
1
1000
NORMALIZED GAIN
dB
0.2
100
10
0
0.1
0.3
0.4
V
S
= 5.0V
V
S
= 3.0V
V
S
= 2.7V
V
O
= 0.2V p-p
R
L
= 1k
V
BIAS
= 1V
G = 1
TPC 8. 0.1 dB Flatness
0.01 0.1 1.0 10 100 1000
80
60
40
20
0
20
40
200
150
100
50
0
50
100
150
200
250
300
OPEN-LOOP GAIN
dB
PHASE
Degrees
FREQUENCY MHz
SERIES 2
SERIES 1
TPC 9. AD8062 Open-Loop Gain and Phase vs.
Frequency, V
S
= 5 V, R
L
= 1 k
INPUT SIGNAL BIAS V
0
50
100
0.5
HARMONIC DISTORTION
dBc
1.0
3.0
3.5
10
20
30
40
60
70
80
90
2.5
2.0
1.5
3RD @ 1MHz
3RD @ 10MHz
2ND @ 1MHz
2ND @ 10MHz
V
S
= 5V
R
L
= 1k
G = 1
TPC 10. Harmonic Distortion for a 1 V p-p Signal vs.
Input Signal DC Bias
FREQUENCY MHz, START = 10kHz, STOP = 30MHz
70
0.01
DISTORTION
dB
40
50
60
80
90
100
110
0.1
1
10
50
3RD H
2ND H
+1.25V
dc
50
604
1k
52.3
0.1 F
10 F
+5V
+
+
0.1 F
1k
(R
LOAD
)
1M
INPUT
TPC 11. Harmonic Distortion for a 1 V p-p Output
Signal vs. Input Signal DC Bias
OUTPUT SIGNAL DC BIAS V
50
120
0
DISTORTION
dB
1
5
30
40
60
70
80
90
4
3
2
110
100
V
S
= 5V
R
L
= 1k
G = 5
V
O
= 1V p-p
3RD
2ND
10MHz
5MHz
2ND
3RD
1MHz
3RD
2ND
TPC 12. Harmonic Distortion vs. Output Signal
DC Bias
AD8061/AD8062/AD8063
8
REV. C
RTO OUTPUT V p-p
100
DISTORTION
dB
1.0
3.0
3.5
40
50
60
70
2.5
2.0
1.5
3RD @ 2MHz
2ND @ 2MHz
2ND @ 10MHz
90
80
4.0
4.5
V
S
= 5V
R
F
= R
L
= 1k
G = 2
110
3RD @ 500kHz
+
1k
5V
10 F
0.1 F
1k
50
1k
50
1M
INPUT
TO
3589A
2ND @ 500kHz
TPC 13. Harmonic Distortion vs. Output Signal
Amplitude
FREQUENCY MHz, START = 10kHz, STOP = 30MHz
DISTORTION
dB
0.01
0.1
1
10
30
40
50
60
70
80
90
100
V
S
= 5V
R
I
= R
L
= 1k
V
O
= 2V p-p
G = +2
S1 2ND HARMONIC/
DUAL 2.5V SUPPLY
S1 3RD HARMONIC/
SINGLE +5V SUPPLY
S1 2ND HARMONIC/
SINGLE +5V SUPPLY
S1 3RD HARMONIC/
DUAL
2.5V SUPPLY
110
TPC 14. Harmonic Distortion vs. Frequency
TIME s
0.7
0
OUTPUT VOLTAGE
V
0.20
1.0
0.9
0.8
0.6
0.5
0.4
0.3
0.10
0
0.1
0.2
0.30
0.40
0.50
V
S
= 5V
R
L
= 1k
G = 1
TPC 15. 400 mV Pulse Response
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
DIFFERENTIAL PHASE
Degrees
0.02
0.00
0.02
0.04
0.06
DIFFERENTIAL GAIN
%
0.01
0.00
0.01
0.02
0.04
0.06
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
TPC 16. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, R
L
= 1 k
, V
S
= 5 V
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
0.04
0.03
0.02
0.01
0.00
0.010
0.005
0.000
0.005
0.010
0.01
0.02
DIFFERENTIAL PHASE
Degrees
DIFFERENTIAL GAIN
%
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
TPC 17. Differential Gain and Phase Error, G = 2,
NTSC Input Signal, R
L
= 150
, V
S
= 5 V
OUTPUT STEP AMPLITUDE V
1000
500
SLEW RATE
V/
s
700
1.0
900
800
600
1.5
2.0
2.5
3.0
400
FALLING EDGE
RISING EDGE
100
300
200
0
V
S
= 5V
R
L
= 1k
G = 1
TPC 18. Slew Rate vs. Output Step Amplitude
AD8061/AD8062/AD8063
9
REV. C
OUTPUT STEP V
1400
0
4.0
SLEW RATE
V/
s
1.0
2.0
2.5
1200
1000
800
600
400
200
0
0.5
1.5
3.0
3.5
FALLING EDGE
V
S
= +5V
FALLING EDGE
V
S
= 4V
RISING EDGE
V
S
= 4V
RISING EDGE
V
S
= +5V
TPC 19. Slew Rate vs. Output Step Amplitude, G = 2,
R
L
= 1 k
, V
S
= 5 V
VOLTAGE NOISE
nV/ Hz
V
S
= 5V
R
L
= 1k
FREQUENCY Hz
1000
10
10M
100
1k
100k
1M
100
10
1
10k
TPC 20. Voltage Noise vs. Frequency
FREQUENCY Hz
100
10
10M
CURRENT NOISE
pA/ Hz
100
1k
100k
1M
10
0
10k
1
V
S
= 5V
R
L
= 1k
TPC 21. Current Noise vs. Frequency
500mV/DIV
0
20
40
60
80
100
120
140
160
180
200
2.5V
VOLTS
TIME ns
0.0V
V
IN
V
OUT
V
S
= 2.5V
G = 1
R
L
= 1k
TPC 22. Input Overload Recovery, Input Step = 0 V to 2 V
500mV/DIV
V
S
= 2.5V
G = 5
R
L
= 1k
0
20
40
60
80
100
120
140
160
180
200
2.5V
VOLTS
TIME ns
1.0V
0.0V
V
IN
V
OUT
TPC 23. Output Overload Recovery, Input Step = 0 V to 1 V
FREQUENCY MHz
0.01
500
CMRR
dB
0.1
10
100
100
90
80
70
60
50
40
30
20
10
0
1
SIDE 1
SIDE 2
V
CM
= 0.2V p-p
R
L
= 100
V
S
= 2.5V
154
154
57.6
50
V
IN
200mV p-p
604
604
TPC 24. CMRR vs. Frequency
AD8061/AD8062/AD8063
10
REV. C
PSRR
dB
FREQUENCY MHz
500
0.1
10
100
100
90
80
70
60
50
40
30
20
10
0
1
PSRR
+PSRR
V
S
= 0.2V p-p
R
L
= 1k
V
S
= 5V
0.01
TPC 25.
PSRR vs. Frequency Delta
FREQUENCY MHz
0.01
500
OUTPUT TO OUTPUT CROSSTALK
dB
0.1
10
100
120
110
100
80
70
60
50
40
30
20
1
INPUT = SIDE 2
INPUT = SIDE 1
V
S
= 5V
V
IN
= 400mV rms
R
L
= 1k
G = 2
90
IN
1k
1k
50
+2.5V
1k
OUT
2.5V
TPC 26. AD8062 Crosstalk, V
OUT
= 2.0 V p-p, R
L
= 1 k
,
G = 2, V
S
= 5 V
FREQUENCY MHz
0
1
1000
DISABLED ISOLATION
dB
20
100
10
10
30
50
40
60
70
80
90
V
S
= 5V
V
O
= 0.2V p-p
R
L
= 1k
V
BIAS
= 1V
TPC 27. Disabled Output Isolation Frequency Response
DISABLE VOLTAGE
7
1.0
5.0
I
SUPPLY
mA
1.5
2.0
2.5
6
5
4
3
1
0
3.0
2
3.5
4.0
4.5
V
S
= 5V
TPC 28.
DISABLE Voltage vs. Supply Current
V
DISABLE
TIME s
6
0
2.0
OUTPUT VOLTAGE
V
0.4
5
4
3
2
0
1
0.8
1
1.2
1.6
V
OUT
V
S
= 5V
G = 2
f
IN
= 10MHz
@ 1.3V
BIAS
R
L
= 100
TPC 29.
DISABLE Function, Voltage = 0 V to 5 V
FREQUENCY MHz
1000
0.1
1000
IMPEDANCE
10
1
10
100
100
1
0.1
0.01
V
S
= 5V
V
O
= 0.2V p-p
R
L
= 1k
V
BIAS
= 1V
TPC 30. Output Impedance vs. Frequency, V
OUT
= 0.2 V
p-p, R
L
= 1 k
, V
S
= 5 V
AD8061/AD8062/AD8063
11
REV. C
20ns/DIV
+0.1%
SETTLING TIME TO 0.1%
0.1%
V
S
= 5V
R
L
= 1k
t = 0
1k
50
1k
R
L
= 1k
TPC 31. Output Settling Time to 0.1%
OUTPUT VOLTAGE STEP
50
0.5
SETTLING TIME
ns
1
1.5
2
45
40
35
30
25
20
15
10
5
0
2.5
FALLING EDGE
RISING EDGE
V
S
= 5V
R
L
= 1k
G = 1
TPC 32. Settling Time vs. V
OUT
2 s
V
S
= 5V
G = 1
R
F
= 1k
R
L
= 1k
4.86
2.43
0.0V
1V
TPC 33. Output Swing
500mV/DIV
V
S
= 5V
G = 2
R
L
= 1k
V
IN
= 1V p-p
0
10
20
80
90
100
3.5V
TIME ns
2.5V
1.5V
70
60
50
40
30
TPC 34. 1 V Step Response
20mV/DIV
V
S
= 5V
G = 2
R
L
= 1k
V
IN
= 100mV
0
10
20
80
90
100
2.6V
TIME ns
2.5V
2.4V
70
60
50
40
30
TPC 35. 100 mV Step Response
2 s/DIV
0.0V
1V/DIV
V
S
= 5V
G = 2
R
F
= R
L
= 1k
V
IN
= 4V p-p
TPC 36. Output Rail-to-Rail Swing
AD8061/AD8062/AD8063
12
REV. C
50mV/DIV
V
S
= 5V
G = 1
R
L
= 1k
0
5
10
40
45
50
2.6V
TIME ns
2.5V
2.4V
35
30
25
20
15
TPC 37. 200 mV Step Response
1V/DIV
V
S
= 5V
G = 2
R
L
= R
F
= 1k
V
IN
= 2V p-p
0
5
10
40
45
50
TIME ns
35
30
25
20
15
4.5V
2.5V
0.5V
TPC 38. 2 V Step Response
CIRCUIT DESCRIPTION
The AD8061/AD8062/AD8063 family are very high-speed volt-
age feedback op amps. The high slew rate input stage is a true
single-supply topology, capable of sensing signals at or below
the minus supply rail. The rail-to-rail output stage can pull
within 30 mV of either supply rail when driving light loads and
within 0.3 V when driving 150
. High-speed performance is
maintained at supply voltages as low as 2.7 V.
Headroom Considerations
These amplifiers are designed for use in low-voltage systems. To
obtain optimum performance, it is useful to understand the
behavior of the amplifier as input and output signals approach
the amplifier's headroom limits.
The AD806x's input common-mode voltage range extends from
the negative supply voltage (actually 200 mV below this), or
"ground" for single supply operation, to within 1.8 V of the
positive supply voltage. Thus, at a gain of 2, the AD806x can
provide full "rail-to-rail" output swing for supply voltage as low
as 3.6 V, assuming the input signal swing from V
S
(or ground)
to +V
S
/2. At a gain of 3, the AD806x can provide a rail-to-rail
output range down to 2.7 V total supply voltage.
Exceeding the headroom limit is not a concern for any inverting
gain on any supply voltage, as long as the reference voltage at
the amplifier's positive input lies within the amplifier's input
common-mode range.
The input stage will be the headroom limit for signals when the
amplifier is used in a gain of 1 for signals approaching the
positive rail. Figure 3 shows a typical offset voltage versus
input common-mode voltage for the AD806x amplifier on a
5 V supply. Accurate dc performance is maintained from about
200 mV below the minus supply to within 1.8 V of the positive
supply. For high-speed signals, however, there are other consid-
erations. Figure 4 shows 3 dB bandwidth versus dc input
V
CM
V
V
OS
mV
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Figure 3. V
OS
vs. Common-Mode Voltage, V
S
= 5 V
V
CM
= 3.0
FREQUENCY MHz
2
8
0.1
GAIN
dB
4
0
2
6
1
10
100
1000
10000
V
CM
= 3.1
V
CM
= 3.2
V
CM
= 3.3
V
CM
= 3.4
Figure 4. Unity Gain Follower Bandwidth vs. Input
Common Mode, V
S
= 5 V
voltage for a unity gain follower. As the common-mode voltage
approaches the positive supply, the amplifier holds together
well, but the bandwidth begins to drop at 1.9 V within +V
S
.
This can manifest itself in increased distortion or settling time.
TPC 10 plots the distortion of a 1 V p-p signal with the AD806x
amplifier used as a follower on a 5 V supply versus signal common-
mode voltage. Distortion performance is maintained until the
input signal center voltage gets beyond 2.5 V, as the peak of the
input sine wave begins to run into the upper common-mode
voltage limit. Higher frequency signals require more headroom
than the lower frequencies to maintain distortion performance.
Figure 5 illustrates how the rising edge settling time for the
amplifier configured as a unity gain follower stretches out as the
top of a 1 V step input approaches and exceeds the specified input
common-mode voltage limit.
AD8061/AD8062/AD8063
13
REV. C
For signals approaching the minus supply and inverting gain
and high positive gain configurations, the headroom limit will be
the output stage. The AD806x amplifiers use a common emitter
style output stage. This output stage maximizes the available
output range, limited by the saturation voltage of the output
transistors. The saturation voltage increases with the drive
current the output transistor is required to supply, due to the
output transistors' collector resistance. The saturation voltage
can be estimated using the equation V
SAT
= 25 mV + I
O
8 ,
where I
O
is the output current, and 8
is a typical value for the
output transistors' collector resistance.
TIME ns
2.0
0
OUTPUT VOLTAGE
V
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
4
8
12
16
20
24
28
32
2V TO 3V STEP
2.1V TO 3.1V STEP
2.2V TO 3.2V STEP
2.3V TO 3.3V STEP
2.4V TO 3.4V STEP
Figure 5. Output Rising Edge for 1 V Step at Input Head-
room Limits, G = 1, V
S
= 5 V, 0 V
As the saturation point of the output stage is approached, the
output signal will show increasing amounts of compression and
clipping. As in the input headroom case, the higher frequency
signals require a bit more headroom than the lower frequency
signals. TPCs 11, 12, and 13 illustrate the point, plotting typical
distortion versus output amplitude and bias for gains of 2 and 5.
Overload Behavior and Recovery
Input
The specified input common-mode voltage of the AD806x is
200 mV below the negative supply to within 1.8 V of the posi-
tive supply. Exceeding the top limit results in lower bandwidth
and increased settling time as seen in Figures 4 and 5. Push-
ing the input voltage of a unity gain follower beyond 1.6 V within
the positive supply leads to the behavior shown in Figure 6--an
increasing amount of output error as well as much increased
settling time. Recovery time from input voltages 1.6 V or closer
to the positive supply is about 35 ns, which is limited by the
settling artifacts caused by transistors in the input stage com-
ing out of saturation.
The AD806x family does not exhibit phase reversal, even for input
voltages beyond the voltage supply rails. Going more than 0.6 V
beyond the power supplies will turn on protection diodes at the
input stage, which will greatly increase the device's current draw.
TIME ns
2.1
0
OUTPUT VOLTAGE
V
2.3
100
VOLTAGE STEP
FROM 2.4V TO 3.4V
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VOLTAGE STEP
FROM 2.4V TO 3.6V
VOLTAGE STEP
FROM 2.4V TO 3.8V,
4V AND 5V
200
300
400
500
600
Figure 6. Pulse Response for G = 1 Follower, Input Step
Overloading the Input Stage
Output
Output overload recovery is typically within 40 ns after the
amplifier's input is brought to a nonoverloading value. Figure
7 shows output recovery transients for the amplifier recovering
from a saturated output from the top and bottom supplies to a
point at midsupply.
TIME ns
0.20
INPUT AND OUTPUT VOLTAGE
V
OUTPUT VOLTAGE
5V TO 2.5V
0.20
0.60
1.0
1.4
1.8
2.2
2.6
3.0
3.4
3.8
4.2
4.6
5.0
0
10
20
30
40
50
60
70
OUTPUT VOLTAGE
0V TO 2.5V
INPUT VOLTAGE
EDGES
R
5V
V
O
2.5V
R
V
IN
Figure 7. Overload Recovery, G = 1, V
S
= 5 V
CAPACITIVE LOAD DRIVE
The AD806x family is optimized for bandwidth and speed, not
for driving capacitive loads. Output capacitance will create a
pole in the amplifier's feedback path, leading to excessive
peaking and potential oscillation. If dealing with load capaci-
tance is a requirement of the application, the two strategies to
consider are (1) using a small resistor in series with the
amplifier's output and the load capacitance and (2) reducing
the bandwidth of the amplifier's feedback loop by increasing the
overall noise gain.
AD8061/AD8062/AD8063
14
REV. C
Figure 8 shows a unity gain follower using the series resistor
strategy. The resistor isolates the output from the capacitance
and, more importantly, creates a zero in the feedback path that
compensates for the pole created by the output capacitance.
AD8061
V
O
R
SERIES
C
LOAD
V
IN
Figure 8. Series Resistor Isolating Capacitive Load
Voltage feedback amplifiers like those in AD806x family will be
able to drive more capacitive load without excessive peaking
when used in higher-gain configurations. This is because the
increased noise gain reduces the bandwidth of the overall feed-
back loop. Figure 9 plots the capacitance that produces 30%
overshoot versus noise gain for a typical amplifier.
CLOSED-LOOP GAIN
10000
1000
10
1
5
2
CAPACITIVE LOAD
pF
100
3
4
R
S
= 0
R
S
= 4.7
Figure 9. Capacitive Load vs. Closed-Loop Gain
DISABLE OPERATION
The internal circuit for the AD8063 disable function is shown in
Figure 10. When the
DISABLE node is pulled below 2 V from
the positive supply, the supply current will decrease from typi-
cally 6.5 mA to under 400
A, and the AD8063 output will
enter a high impedance state. If the
DISABLE node is not con-
nected, and thus is allowed to float, the AD8063 will stay biased
at full power.
VCC
DISABLE
TO AMPLIFIER
BIAS
VEE
2V
Figure 10. Disable Circuit of the AD8063
TPC 28 shows AD8063 supply current versus
DISABLE volt-
age. TPC 29 plots the output seen when the AD8063 input is
driven with a 10 MHz sine wave, and the
DISABLE is toggled
from 0 V to 5 V, illustrating the part's turn-on and turn-off time.
TPC 27 shows the input/output isolation response with the
AD8063 shut off.
BOARD LAYOUT CONSIDERATIONS
Maintaining the high-speed performance of the AD806x family
requires the use of high-speed board layout techniques and low
parasitic components.
The PCB should have a ground plane covering unused portions
of the component side of the board to provide a low impedance
path. The ground plane should be removed near the package to
reduce parasitic capacitance.
Proper bypassing is critical. A ceramic 0.1
F chip capacitor
should be used to bypass both supplies, and be located within
3 mm of each power pin. An additional 4.7
F to 10 F tanta-
lum electrolytic capacitor should be connected in parallel to
provide charge for fast, large signal changes at the output.
Minimizing parasitic capacitance at the amplifier's inverting
input pin is very important. The feedback resistor should be
located close to the inverting input pin. The value of the feed-
back resistor may come into play--for instance, 1 k
interacting
with 1 pF of parasitic capacitance creates a pole at 159 MHz.
Stripline design techniques should be used for signal traces
longer than 25 mm. These should be designed with either 50
or 75
characteristic impedance and be properly terminated at
each end.
APPLICATIONS
Single Supply Sync Stripper
When a video signal contains synchronization pulses, it is
sometimes desirable to remove them prior to performing
certain operations. In the case of A-to-D conversion, the sync
pulses will consume some of the dynamic range, so removing
them will increase the converter's available dynamic range for
the video information.
Figure 11 shows a basic circuit for creating a sync stripper using
the AD8061 powered by a single supply. When the nega-
tive supply is at ground potential, the lowest potential to
which the output can go is ground. This feature is exploited
to create a waveform whose lowest amplitude is the black level
of the video and does not include the sync level.
75
VIDEO OUT
75
R
G
1k
75
R
F
1k
10 F
3V
AD8061
0.1 F
3
2
4
6
7
VIDEO IN
PIN NUMBERS ARE
FOR 8-PIN PACKAGE
Figure 11. Single 3 V Sync Stripper Using AD8061
In this case, the input video signal has its black level at ground,
so it comes out at ground at the input. Since the sync level is below
the black level, it will not show up at the output. However, all
of the active video portion of the waveform will be amplified
by a gain of two and then be normalized to unity gain by the
back-terminated transmission line. Figure 12 is an oscilloscope
plot of the input and output waveforms.
AD8061/AD8062/AD8063
15
REV. C
500mV
INPUT
OUTPUT
1
2
10 s
Figure 12. Input and Output Waveforms for a Single
Supply Video Sync Stripper Using an AD8061
Some video signals with sync are derived from single supply
devices, such as video DACs. These signals can contain sync,
but the whole waveform is positive, and the black level is not at
ground but at some positive voltage. The circuit can be modified to
provide the sync stripping function for such a waveform. Instead
of connecting RG to ground, it should be connected to a dc
voltage that is two times the black level of the input signal. The
gain from the +input to the output is two, which means that
the black level will be amplified by two to the output. However,
the gain through RG is unity to the output. It will take a dc
level of twice the input black level to shift the black level to
ground at the output. When this occurs, the sync will be
stripped, and the active video will be passed as in the ground
referenced case.
75
10 F
0.1 F
3V
3
2
4
6
7
75
MONITOR
#1
75
75
75
1k
1k
1k
1k
3V
1k
3
2
5
6
7
8
1
4
MONITOR
#2
GREEN
DAC
RED
GREEN
BLUE
RED
DAC
BLUE
DAC
75
75
75
75
AD8061
75
10 F
0.1 F
1k
AD8062
75
AD8062
75
Figure 13. RGB Cable Driver Using AD8061 and AD8062
RGB Amplifier
Most RGB graphics signals are created by video-DAC outputs
that drive a current through a resistor to ground. At the video
black level, the current goes to zero, and thus the voltage of the
video is also zero. Before the availability of high-speed rail-to-
rail op amps, it was essential that an amplifier have a negative
supply to amplify such a signal. Such an amplifier is necessary
if one wants to drive a second monitor with from the same
DAC outputs.
However, high-speed, rail-to-rail output amplifiers like the
AD8061 and AD8062 can accept ground level input signals and
output ground level signals and thus be used as RGB signal
amplifiers. A combination of the AD8061 (single) and AD8062
(dual) can amplify the three video channels of an RGB system.
Figure 13 shows a circuit that performs this function.
Multiplexer
The AD8063 has a disable pin that can be used to power down
the amplifier to save power, or can be used to create a mux circuit.
If two (or more) AD8063 outputs are connected together and
only one is enabled, then only the signal of the enabled amplifier
will appear at the output. This configuration can be used to select
from various input-signal sources. Additionally, the same input
signal can be applied to different gain stages or differently
tuned filters to make a gain-step amplifier or a selectable-
frequency amplifier.
Figure 14 shows a schematic of two AD8063s used to create a
mux that selects between two inputs. One of these is a 1 V p-p,
3 MHz sine wave and the other is a 2 V p-p, 1 MHz sine wave.
49.9
1k
+4V
1
4V
49.9
TIME
BASE
OUT
TIME
BASE
IN
1V
P-P
3MHz
2V
P-P
1MHz
V
OUT
49.9
SELECT
HCO4
1k
10 F
0.1 F
10 F
0.1 F
AD8063
49.9
1k
+4V
1
4V
1k
10 F
0.1 F
10 F
0.1 F
AD8063
Figure 14. Two-to-One Multiplexer Using Two AD8063s
16
C0106505/01(C)
PRINTED IN U.S.A.
AD8061/AD8062/AD8063
REV. C
5-Lead SOT-23-5
(RT-5)
1
3
2
5
4
0.1220 (3.100)
0.1063 (2.700)
PIN 1
0.0709 (1.800)
0.0590 (1.500)
0.1181 (3.000)
0.0984 (2.500)
0.0748 (1.900)
REF
0.0374 (0.950) REF
0.0197 (0.500)
0.0118 (0.300)
0.0512 (1.300)
0.0354 (0.900)
SEATING
PLANE
0.0571 (1.450)
0.0354 (0.900)
0.0059 (0.150)
0.0000 (0.000)
0.0079 (0.200)
0.0035 (0.090)
0.0236 (0.600)
0.0039 (0.100)
10
0
6-Lead SOT-23-6
(RT-6)
0.122 (3.10)
0.106 (2.70)
PIN 1
0.118 (3.00)
0.098 (2.50)
0.075 (1.90)
BSC
0.037 (0.95) BSC
1
3
4
5
6
2
0.071 (1.80)
0.059 (1.50)
0.009 (0.23)
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
10
0
0.020 (0.50)
0.010 (0.25)
0.006 (0.15)
0.000 (0.00)
0.051 (1.30)
0.035 (0.90)
SEATING
PLANE
0.057 (1.45)
0.035 (0.90)
8-Lead SOIC
(SO-8)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
45
8
5
4
1
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
8-Lead SOIC
(RM-8)
0.009 (0.23)
0.005 (0.13)
0.028 (0.70)
0.016 (0.40)
6
0
0.037 (0.95)
0.030 (0.75)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
0.193
(4.90)
BSC
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.016 (0.40)
0.010 (0.25)
0.043
(1.10)
MAX
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
AD8061/AD8062/AD8063Revision History
Location
Page
Data Sheet changed from REV. B to REV. C.
Replaced TPC 9 with new graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
The SELECT signal and the output waveforms for this circuit
are shown in Figure 15. For synchronization clarity, two differ-
ent frequency synthesizers whose time bases are locked to each
other generate the signals.
1V
2V
2 s
SELECT
OUTPUT
Figure 15. AD8063 Mux Output
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