REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8072/AD8073
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
Low Cost, Dual/Triple
Video Amplifiers
FUNCTIONAL BLOCK DIAGRAMS
8-Lead Plastic (N), SOIC (R), and SOIC (RM) Packages
1
2
3
4
8
7
6
5
AD8072
IN2
IN2
OUT2
V
S
OUT1
IN1
IN1
V
S
14-Lead Plastic (N), and SOIC (R) Packages
AD8072
IN2
OUT2
NC
NC
NC
V
S
IN3
7
IN1
IN1
OUT1
IN2
V
S
IN3
8 OUT3
AD8073
NC = NO CONNECT
6
9
5
10
4
11
3
12
2
13
1
14
FEATURES
Very Low Cost
Good Video Specifications (R
L
= 150 )
Gain Flatness of 0.1 dB to 10 MHz
0.05% Differential Gain Error
0.1 Differential Phase Error
Low Power
3.5 mA/Amplifier Supply Current
Operates on Single +5 V to +12 V Supply
High Speed
100 MHz, 3 dB Bandwidth (G = +2)
500 V/ s Slew Rate
Fast Settling Time of 25 ns (0.1%)
Easy to Use
30 mA Output Current
Output Swing to 1.3 V of Rails on Single +5 V Supply
APPLICATIONS
Video Line Driver
Computer Video Plug-In Boards
RGB or S-Video Amplifier in Component Systems
PRODUCT DESCRIPTION
The AD8072 (dual) and AD8073 (triple) are low cost, current
feedback amplifiers intended for high volume, cost sensitive
applications. In addition to being low cost, these amplifiers
deliver solid video performance into a 150
load while consuming
only 3.5 mA per amplifier of supply current. Furthermore, the
AD8073 is three amplifiers in a single 14-lead narrow-body
SOIC package. This makes it ideal for applications where small
size is essential. Each amplifier's inputs and output are acces-
sible providing added gain setting flexibility.
These devices provide 30 mA of output current per amplifier,
and are optimized for driving one back terminated video load
(150
) each. These current feedback amplifiers feature gain
flatness of 0.1 dB to 10 MHz while offering differential gain and
phase error of 0.05% and 0.1
. This makes the AD8072 and
AD8073 ideal for business and consumer video electronics.
Both will operate from a single +5 V to +12 V power supply.
The outputs of each amplifier swing to within 1.3 volts of either
supply rail to accommodate video signals on a single +5 V supply.
The high bandwidth of 100 MHz, 500 V/
s of slew rate, along
with settling to 0.1% in 25 ns, make the AD8072 and AD8073
useful in many general purpose, high speed applications where a
single +5 V or dual power supplies up to
6 V are needed. The
AD8072 is available in 8-lead plastic DIP, SOIC, and
SOIC
packages while the AD8073 is available in 14-lead plastic DIP and
SOIC packages. Both operate over the commercial temperature
range of 0
C to +70C. Additionally, the AD8072ARM oper-
ates over the industrial temperature range of 40
C to +85C.
FREQUENCY MHz
6.1
GAIN FLATNESS
dB
6.0
5.3
0.1
500
1
10
100
5.9
5.8
5.4
5.7
5.6
5.5
6
5
4
3
2
1
0
V
S
= 5V
V
O
= 2V p-p
R
F
= R
G
= 1k
R
L
= 150
A
V
= 2
CLOSED-LOOP GAIN
dB
7
1
0.1 dB
DIV
1 dB
DIV
Figure 1. Large Signal Frequency Response
REV. A
2
AD8072/AD8073SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AD8072/AD8073
Parameter
Conditions
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
R
F
= 1 k
3 dB Bandwidth, Small Signal
No Peaking, G = +2
80
100
MHz
0.1 dB Bandwidth, Small Signal
No Peaking, G = +2
8
10
MHz
Slew Rate
V
O
= 4 V Step
500
V/
s
Settling Time to 0.1%
V
O
= 2 V Step
25
ns
DISTORTION/NOISE PERFORMANCE
R
F
= 1 k
Differential Gain
f = 3.58 MHz, G = +2
0.05
0.15
%
Differential Phase
f = 3.58 MHz, G = +2
0.1
0.3
Degrees
Crosstalk
f = 5 MHz
60
dB
Input Voltage Noise
f = 10 kHz
3
nV/
Hz
Input Current Noise
f = 10 kHz (
I
IN
)
6
pA/
Hz
DC PERFORMANCE
Transimpedance
0.3
M
Input Offset Voltage
2
6
mV
T
MIN
to T
MAX
8
mV
Offset Drift
11
V/C
Input Bias Current (
)
4
12
A
Input Bias Current Drift (
)
12
nA/
C
INPUT CHARACTERISTICS
Input Resistance
120
+Input Resistance
1
M
Input Capacitance
1.6
pF
Common-Mode Rejection Ratio
V
CM
= 3.8 V to +3.8 V
56
dB
Input Common-Mode Voltage Range
3.8
V
OUTPUT CHARACTERISTICS
+Output Voltage Swing
3
3.3
V
Output Voltage Swing
2.25
3
V
Output Current
R
L
= 10
30
mA
Short Circuit Current
80
mA
POWER SUPPLY
Operating Range
2.5 to 6
V
Power Supply Rejection Ratio
V
S
=
4 V to 6 V
70
dB
Quiescent Current per Amplifier
3.5
5
mA
OPERATING TEMPERATURE RANGE
0
+70
C
Specifications subject to change without notice.
(@ T
A
= +25 C, V
S
= 5 V, R
L
= 150
, unless otherwise noted)
REV. A
3
AD8072/AD8073
ELECTRICAL CHARACTERISTICS
AD8072/AD8073
Parameter
Conditions
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
R
F
= 1 k
3 dB Bandwidth, Small Signal
No Peaking, G = +2
78
100
MHz
0.1 dB Bandwidth, Small Signal
No Peaking, G = +2
7.8
10
MHz
Slew Rate
V
O
= 2 V Step
350
V/
s
Settling Time to 0.1%
V
O
= 2 V Step
25
ns
DISTORTION/NOISE PERFORMANCE
R
F
= 1 k
Differential Gain
f = 3.58 MHz, G = +2, R
L
to 1.5 V
0.1
%
Differential Phase
f = 3.58 MHz, G = +2, R
L
to 1.5 V
0.1
Degrees
Crosstalk
f = 5 MHz
60
dB
Input Voltage Noise
f = 10 kHz
3
nV/
Hz
Input Current Noise
f = 10 kHz (
I
IN
)
6
pA/
Hz
DC PERFORMANCE
Transimpedance
0.25
M
Input Offset Voltage
1.5
4
mV
T
MIN
to T
MAX
6
mV
Offset Drift
9
V/C
Input Bias Current (
)
3
10
A
Input Bias Current Drift (
)
10
nA/
C
INPUT CHARACTERISTICS
Input Resistance
120
+Input Resistance
1
M
Input Capacitance
1.6
pF
Common-Mode Rejection Ratio
V
CM
= +1.2 V to +3.8 V
54
dB
Input Common-Mode Voltage Range
+1.2 to +3.8
V
OUTPUT CHARACTERISTICS
Output Voltage Swing
+1.5 to +3.5
+1.3 to +3.7
V
Output Current
R
L
= 10
20
mA
Short Circuit Current
60
mA
POWER SUPPLY
Operating Range
2.5 to 6
V
Power Supply Rejection Ratio
V
S
= +4 V to +6 V
64
dB
Quiescent Current per Amplifier
3
4.5
mA
OPERATING TEMPERATURE RANGE
0
+70
C
(@ T
A
= +25 C, V
S
= +5 V, R
L
= 150 to 2.5 V, unless otherwise noted)
REV. A
AD8072/AD8073
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8072 and AD8073 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 V
Internal Power Dissipation
2
AD8072 8-Lead Plastic (N) . . . . . . . . . . . . . . . . . 1.3 Watts
AD8072 8-Lead Small Outline (SO-8) . . . . . . . . . 0.9 Watts
AD8072 8-Lead
SOIC (RM) . . . . . . . . . . . . . . . 0.6 Watts
AD8073 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts
AD8073 14-Lead Small Outline (R) . . . . . . . . . . . 1.0 Watts
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . .
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . .
1.25 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . .
Observe Power Derating Curves
Storage Temperature Range
N, R, RM Packages . . . . . . . . . . . . . . . . . 65
C to +125C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead Plastic Package:
JA
= 90
C/W
8-Lead SOIC Package:
JA
= 140
C/W
8-Lead
SOIC Package:
JA
= 214
C/W
14-Lead Plastic Package:
JA
= 75
C/W
14-Lead SOIC Package:
JA
= 120
C/W
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD8072ARM
40
C to +85C 8-Lead SOIC
RM-8
AD8072ARM-REEL
40
C to +85C 13" Reel 8-Lead SOIC RM-8
AD8072ARM-REEL7 40
C to +85C 7" Reel 8-Lead SOIC RM-8
AD8072JN
0
C to +70C
8-Lead Plastic DIP
N-8
AD8072JR
0
C to +70C
8-Lead SOIC
SO-8
AD8072JR-REEL
0
C to +70C
13" Reel 8-Lead SOIC
SO-8
AD8072JR-REEL7
0
C to +70C
7" Reel 8-Lead SOIC
SO-8
AD8073JN
0
C to +70C
14-Lead Plastic DIP
N-14
AD8073JR
0
C to +70C
14-Lead Narrow SOIC R-14
AD8073JR-REEL
0
C to +70C
13" Reel 14-Lead SOIC R-14
AD8073JR-REEL7
0
C to +70C
7" Reel 14-Lead SOIC
R-14
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8072 and AD8073 is limited by the associated rise in junc-
tion temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass transition
temperature of the plastic, approximately +150
C. Exceeding
this limit temporarily may cause a shift in parametric perfor-
mance due to a change in the stresses exerted on the die by the
package. Exceeding a junction temperature of +175
C for an
extended period can result in device failure.
While the AD8072 and AD8073 are internally short circuit pro-
tected, this may not be sufficient to guarantee that the maximum
junction temperature (+150
C) is not exceeded under all condi-
tions. To ensure proper operation, it is necessary to observe the
maximum power derating curves shown in Figures 2 and 3.
MAXIMUM POWER DISSIPATION
Watts
AMBIENT TEMPERATURE C
2.0
1.5
0
50
90
40 30 20 10
0
10 20
30
50 60
70 80
40
1.0
0.5
8-LEAD MINI-DIP PACKAGE
8-LEAD SOIC PACKAGE
T
J
= 150 C
SOIC
Figure 2. AD8072 Maximum Power Dissipation vs.
Temperature
AMBIENT TEMPERATURE C
2.5
2.0
0.5
50
90
40
MAXIMUM POWER DISSIPATION
Watts
30 20 10 0
10 20
30 40 50
60
80
1.5
1.0
70
14-LEAD SOIC
14-LEAD DIP PACKAGE
T
J
= 150 C
Figure 3. AD8073 Maximum Power Dissipation vs.
Temperature
WARNING!
ESD SENSITIVE DEVICE
REV. A
AD8072/AD8073
5
FREQUENCY MHz
7
CLOSED-LOOP GAIN
dB
6
0.1
0.1
1000
1.0
10
100
5
4
0
3
2
1
V
S
= 5V
R
F
= 1k
R
L
= 150 TO 2.5V
A
V
= 2
V
IN
= 100mV p-p
0 C
25 C
70 C
Figure 4. Frequency Response Over Temperature; V
S
= +5 V
FREQUENCY MHz
7
CLOSED-LOOP GAIN
dB
6
0.1
0.1
1000
1.0
10
100
5
4
0
3
2
1
V
S
= 5V
R
F
= 1k
R
L
= 150
A
V
= 2
V
IN
= 100mV p-p
0 C
25 C
70 C
Figure 5. Frequency Response Over Temperature; V
S
=
5 V
FREQUENCY MHz
6.1
GAIN FLATNESS
dB
6.0
5.3
0.1
500
1.0
10
100
5.9
5.8
5.4
5.7
5.6
5.5
V
S
= 5V
R
F
= 1k
R
L
= 150 TO 2.5V
A
V
= 2
V
IN
= 100mV p-p
70 C
0 C, 25 C
Figure 6. 0.1 dB Flatness vs. Frequency Over Tempera-
ture; V
S
= +5 V
FREQUENCY MHz
6.1
GAIN FLATNESS
dB
6.0
5.3
0.1
500
1.0
10
100
5.9
5.8
5.4
5.7
5.6
5.5
V
S
= 5V
R
F
= 1k
R
L
= 150
A
V
= 2
V
IN
= 100mV p-p
0 C, 25 C
70 C
Figure 7. 0.1 dB Flatness vs. Frequency Over Tempera-
ture; V
S
=
5 V
0.00
0.03
0.07
0.08
0.08
0.08
0.09
0.08
0.08
0.07
0.06
DIFFERENTIAL GAIN
%
MIN = 0.00 MAX = 0.09 p-p/MAX = 0.09
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.02
V
S
= 5V, R
F
= 1k , R
L
= 150 TO 1.5V, A
V
= 2
0.00
0.05
0.09
0.10
0.09
0.08
0.06
0.06
0.05
0.04
0.02
1
ST
2
ND
3
RD
4
TH
5
TH
6
TH
7
TH
8
TH
9
TH
10
TH
11
TH
MODULATING RAMP LEVEL IRE
DIFFERENTIAL PHASE
deg
MIN = 0.00 MAX = 0.10 p-p = 0.10
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.02
V
S
= 5V, R
F
= 1k , R
L
= 150 TO 1.5V, A
V
= 2
Figure 8. Differential Gain and Phase, V
S
= +5 V
0.00
0.00
0.00 0.00
0.00 0.01 0.01 0.02 0.03 0.03 0.03
DIFFERENTIAL GAIN
%
MIN = 0.03 MAX = 0.00 p-p/MAX = 0.03
0.00
0.01
0.02
0.03
0.00
0.00 0.00 0.02 0.03 0.05 0.07 0.08 0.10 0.10 0.10
1
ST
2
ND
3
RD
4
TH
5
TH
6
TH
7
TH
8
TH
9
TH
10
TH
11
TH
MODULATING RAMP LEVEL IRE
DIFFERENTIAL PHASE
deg
MIN = 0.10 MAX = 0.00 p-p = 0.10
0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
V
S
= 5V,
R
F
= 1k
R
L
= 150
A
V
= 2
V
S
= 5V,
R
F
= 1k
R
L
= 150
A
V
= 2
Figure 9. Differential Gain and Phase, V
S
=
5 V
REV. A
AD8072/AD8073
6
FREQUENCY MHz
0
10
80
0.1
500
1.0
10
100
20
30
70
40
50
60
90
0.1
CROSSTALK
dB
AMP 2 OUTPUT
SOIC PACKAGE
DRIVE AMP 2
RECEIVE AMPS 1, 3 AD8073
RECEIVE AMP 1 AD8072
V
S
= 5V, 5V
R
F
= 1k , R
L
= 150
A
V
= 2
V
IN
= 1V p-p
Figure 10. Crosstalk vs. Frequency
FREQUENCY MHz
40
50
100
0.1
1
DISTORTION
dBc
10
70
80
90
60
V
S
= 5V
R
F
= 1k
R
L
= 150
A
V
= 2
V
OUT
= 2V p-p
3RD
HARMONIC
2ND
HARMONIC
Figure 11. Distortion vs. Frequency; V
S
=
5 V
FREQUENCY MHz
40
DISTORTION
dBc
50
100
0.1
1
10
70
80
90
60
3RD
HARMONIC
2ND
HARMONIC
V
S
= 5V
R
F
= 1k
R
L
= 150 TO 2.5V
A
V
= 2
V
OUT
= 2V p-p
Figure 12. Distortion vs. Frequency; V
S
= +5 V
100M
1k
10
10k
100
1k
100k
10k
10M
1M
100k
FREQUENCY Hz
DEGREES
0
20
40
60
80
100
120
140
160
180
1G
DEGREES
OHMS ( )
T
Z
1M
Figure 13. Open-Loop Transimpedance vs. Frequency
FREQUENCY MHz
0.1
1k
1
10
100
3
2
1
0
1
2
3
4
5
6
A
V
= 5
V
S
= 5V
R
F
= 1k
R
L
= 150
V
OUT
= 200mV p-p
A
V
= 1
A
V
= 10
A
V
= 2
NORMALIZED CLOSED-LOOP GAIN
dB
Figure 14. Normalized Frequency Response; V
S
=
5 V
FREQUENCY MHz
6.1
GAIN FLATNESS
dB
6.0
5.3
0.1
500
1
10
100
5.9
5.8
5.4
5.7
5.6
5.5
6
5
4
3
2
1
0
0.1 dB
DIV
1 dB
DIV
CLOSED-LOOP GAIN
dB
7
1
V
S
= 5V
V
O
= 2V p-p
R
F
= R
G
= 1k
R
L
= 150 TO 2.5V
A
V
= 2
Figure 15. Large Signal Frequency Response
REV. A
AD8072/AD8073
7
FREQUENCY MHz
100
OUTPUT RESISTANCE
0.1
500
1
10
100
10
1
0.1
V
S
= 5V
R
F
= 1k
A
V
= 2
Figure 16. Output Resistance vs. Frequency; V
S
=
5 V
FREQUENCY Hz
50
40
0
1
100k
10
INPUT VOLTAGE NOISE
nV/ Hz
100
1k
10k
30
20
10
Figure 17. Noise vs. Frequency; V
S
=
5 V
50
FREQUENCY MHz
5
CMRR
dB
10
45
0.1
500
1
10
100
15
20
40
25
30
35
0.02
55
V
IN
2V p-p
1k
1k
60.4
154
154
150
V
OUT
Figure 20. CMRR vs. Frequency; V
S
=
5 V
FREQUENCY Hz
100
80
0
1
100k
10
INPUT CURRENT NOISE
pA/ Hz
100
1k
10k
60
40
20
Figure 18. Noise vs. Frequency; V
S
=
5 V
FREQUENCY MHz
10
PSRR
dB
0
70
0.1
500
1
10
100
10
20
60
30
40
50
0.02
V
S
= 5V
R
F
= 1k
R
L
= 150
A
V
= 2
100mV p-p ON TOP
OF V
S
PSRR
PSRR
Figure 19. PSRR vs. Frequency
REV. A
AD8072/AD8073
8
1k
1k
R
L
150
50
V
IN
V
OUT
0.1 F
0.1 F
0.001 F
0.001 F
10 F
10 F
+
+
V
S
V
S
Figure 21. Test Circuit; Gain = +2
Note: V
S
=
2.5 V operation is identical to V
S
= +5 V single supply operation.
20ns
250mV
Figure 22. 2 V Step Response; G = +2, V
S
=
5 V
20ns
50mV
Figure 23. 200 mV Step Response; G = +2, V
S
=
5 V
20ns
1V
Figure 24. Sine Response; G = +2, V
S
=
5 V
10ns
250mV
Figure 25. 2 V Step Response; G = +2, V
S
=
2.5 V
20ns
50mV
Figure 26. 200 mV Step Response; G = +2, V
S
=
2.5 V
20ns
250mV
Figure 27. Sine Response; G = +2, V
S
=
2.5 V
REV. A
AD8072/AD8073
9
APPLICATIONS
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this overdrive
condition and resume normal operation. As shown in Figure 28,
the AD8072 and AD8073 recover within 75 ns from positive
overdrive and 30 ns from negative overdrive.
25ns
1V
V
IN
V
OUT
Figure 28. Overload Recovery; V
S
=
5 V, V
IN
= 8 V p-p,
R
F
= 1 k
, R
L
= 150
, G = +2
Bandwidth vs. Feedback Resistor Value
The closed-loop frequency response of a current feedback am-
plifier is a function of the feedback resistor. A smaller feedback
resistor will produce a wider bandwidth response. However, if
the feedback resistance becomes too small, the gain flatness can
be affected. As a practical consideration, the minimum value of
feedback resistance for the AD8072/AD8073 was found to be
649
. For resistances below this value, the gain flatness will be
affected and more significant lot to lot variations in device per-
formance will be noticed. Figure 29 shows a plot of the frequency
response of an AD8072/AD8073 at a gain of two with both feed-
back and gain resistors equal to 649
.
On the other hand, the bandwidth of a current feedback ampli-
fier can be decreased by increasing the feedback resistance. This
can sometimes be useful where it is desired to reduce the noise
bandwidth of a system. As a practical matter, the maximum
value of feedback resistor was found to be 2 k
. Figure 29
shows the frequency response of an AD8072/AD8073 at a gain
of two with both feedback and gain resistors equal to 2 k
.
FREQUENCY MHz
6.1
GAIN FLATNESS
dB
6.0
0.1
500
1
10
100
5.9
5.8
5.4
5.7
5.6
5.5
R
F
= 2k
R
F
= 649
1 dB
DIV
0.1 dB
DIV
6
7
5
4
3
2
1
0
V
S
= 5V
A
V
= 2
R
L
= 150
V
O
= 0.2V p-p
CLOSED-LOOP GAIN
dB
Figure 29. Frequency Response vs. R
F
Capacitive Load Drive
When an op amp output drives a capacitive load, extra phase
shift due to the pole formed by the op amp's output impedance
and the capacitor can cause peaking or even oscillation. The top
trace of Figure 30, R
S
= 0
, shows the output of one of the am-
plifiers of the AD8072/AD8073 when driving a 50 pF capacitor
as shown in the schematic of Figure 31.
The amount of peaking can be significantly reduced by adding
a resistor in series with the capacitor. The lower trace of Fig-
ure 30 shows the same capacitor being driven with a 25
resis-
tor in series with it. In general, the resistor value will have to be
experimentally determined, but from 10
to 50 is a practical
range of values to experiment with for capacitive loads of up to a
few hundred pF.
20ns
50mV
R
S
= 0
R
S
= 25
Figure 30. Capacitive Low Drive
1k
1k
50
V
IN
= 100mV p-p
R
L
1k
C
L
50pF
R
S
Figure 31. Capacitive Load Drive Circuit
REV. A
AD8072/AD8073
10
Crosstalk
Crosstalk between internal amplifiers may vary depending on
which amplifier is being driven and how many amplifiers are
being driven. This variation typically stems from pin location on
the package and the internal layout of the IC itself. Table I
illustrates the typical crosstalk results for a combination of
conditions.
Table I. AD8073JR Crosstalk Table (dB)
Receive Amplifier
AD8073JR
1
2
3
1
X
60
56
Drive
2
60
X
60
Amplifier
3
54
60
X
All Hostile
53
55
54
CONDITIONS
V
S
=
5 V
R
F
= 1 k
, R
L
= 150
A
V
= +2
V
OUT
= 2 V p-p on Drive Amplifier
Layout Considerations
The specified high speed performance of the AD8072 and
AD8073 require careful attention to board layout and compo-
nent selection. Proper RF
design techniques and low parasitic
component selection are mandatory.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
ground path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing. One end
of the capacitor should be connected to the ground plane and
the other within 1/8 inches of each power pin. An additional
large (4.7
F10 F) tantalum electrolytic capacitor should be
connected in parallel, but not necessarily as close to the supply
pins, to provide current for fast large-signal changes at the
device's output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the invert-
ing input will affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50
or 75 and be properly termi-
nated at each end.
REV. A
AD8072/AD8073
11
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8
1
4
5
0.430 (10.92)
0.348 (8.84)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
14-Lead Plastic DIP
(N-14)
14
1
7
8
0.795 (20.19)
0.725 (18.42)
0.280 (7.11)
0.240 (6.10)
PIN 1
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
8-Lead Plastic SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
4
1
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
8-Lead SOIC
(RM-8)
14-Lead SOIC
(R-14)
14
8
7
1
0.3444 (8.75)
0.3367 (8.55)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33
27
0.120 (3.05)
0.112 (2.84)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
C212603/00 (rev. A)
PRINTED IN U.S.A.
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