REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD8091/AD8092
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
Low-Cost, High-Speed
Rail-to-Rail Amplifiers
FEATURES
Low-Cost Single (AD8091), Dual (AD8092)
Voltage Feedback Architecture
Fully Specified at +3 V, +5 V, and 5 V Supplies
Single-Supply Operation
Output Swings to within 25 mV of Either Rail
Input Voltage Range
0.2 V to +4 V; V
S
= +5 V
High-Speed and Fast Settling on +5 V
110 MHz 3 dB Bandwidth (G = +1)
145 V/ s Slew Rate
50 ns Settling Time to 0.1%
Good Video Specifications (G = +2)
Gain Flatness of 0.1 dB to 20 MHz; R
L
= 150
0.03% Differential Gain Error; R
L
= 1 k
0.03 Differential Phase Error; R
L
= 1 k
Low Distortion
80 dBc Total Harmonic @ 1 MHz; R
L
= 100
Outstanding Load Drive Capability
Drives 45 mA, 0.5 V from Supply Rails
Drives 50 pF Capacitive Load (G = +1)
Low Power of 4.4 mA/Amplifier
APPLICATIONS
Coaxial Cable Driver
Active Filters
Video Switchers
Professional Cameras
CCD Imaging Systems
CD/DVD
PRODUCT DESCRIPTION
The AD8091 (single) and AD8092 (dual) are low-cost, voltage
feedback, high-speed amplifiers designed to operate on +3 V, +5 V,
or
5 V supplies. They have true single-supply capability with
an input voltage range extending 200 mV below the negative rail
and within 1 V of the positive rail.
Despite their low cost, the AD8091/AD8092 provide excellent over-
all performance and versatility. The output voltage swing extends
to within 25 mV of each rail, providing the maximum output
dynamic range with excellent overdrive recovery. This makes the
AD8091/AD8092 useful for video electronics, such as cameras,
video switchers, or any high-speed portable equipment. Low distor-
tion and fast settling make them ideal for active filter applications.
The AD8091/AD8092 offer a low-power supply current and
can operate on a single +3 V power supply. These features are
ideally suited for portable and battery-powered applications
where size and power are critical.
The wide bandwidth and fast slew rate make these amplifiers
useful in many general-purpose, high-speed applications where
dual power supplies of up to
6 V and single supplies from +3 V
to +12 V are needed.
All of this low-cost performance is offered in an 8-lead SOIC
(AD8091/AD8092), along with a tiny SOT23-5 package
(AD8091) and a
SOIC package (AD8092).
CONNECTION DIAGRAMS
SOIC-8
(R-8)
8
7
6
5
1
2
3
4
NC
IN
+IN
NC
+V
S
V
OUT
NC
V
S
AD8091
NC = NO CONNECT
SOIC-8 and SOIC-8
(RM-8, R-8)
8
7
6
5
1
2
3
4
+
+
OUT1
IN1
+IN1
OUT
+V
S
IN2
V
S
AD8092
+IN2
SOT23-5
(RT-5)
5
4
1
2
3
V
OUT
V
S
+IN
+V
S
IN
AD8091
2
REV. A
AD8091/AD8092SPECIFICATIONS
AD8091A/AD8092A
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Small Signal Bandwidth
G = +1, V
O
= 0.2 V p-p
70
110
MHz
G = 1, +2, V
O
= 0.2 V p-p
50
MHz
Bandwidth for 0.1 dB Flatness
G = +2, V
O
= 0.2 V p-p,
R
L
= 150
to +2.5 V,
R
F
= 806
20
MHz
Slew Rate
G = 1, V
O
= 2 V Step
100
145
V/
s
Full Power Response
G = +1, V
O
= 2 V p-p
35
MHz
Settling Time to 0.1%
G = 1, V
O
= 2 V Step
50
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
*
f
C
= 5 MHz, V
O
= 2 V p-p, G = +2
67
dB
Input Voltage Noise
f = 10 kHz
16
nV/
Hz
Input Current Noise
f = 10 kHz
850
fA/
Hz
Differential Gain Error (NTSC)
G = +2, R
L
= 150
to +2.5 V
0.09
%
R
L
= 1 k
to +2.5 V
0.03
%
Differential Phase Error (NTSC)
G = +2, R
L
= 150
to +2.5 V
0.19
Degrees
R
L
= 1 k
to +2.5 V
0.03
Degrees
Crosstalk
f = 5 MHz, G = +2
60
dB
DC PERFORMANCE
Input Offset Voltage
1.7
10
mV
T
MIN
to T
MAX
25
mV
Offset Drift
10
V/C
Input Bias Current
1.4
2.5
A
T
MIN
to T
MAX
3.25
A
Input Offset Current
0.1
0.75
A
Open-Loop Gain
R
L
= 2 k
to +2.5 V
86
98
dB
T
MIN
to T
MAX
96
dB
R
L
= 150
to +2.5 V
76
82
dB
T
MIN
to T
MAX
78
dB
INPUT CHARACTERISTICS
Input Resistance
290
k
Input Capacitance
1.4
pF
Input Common-Mode Voltage Range
0.2 to +4
V
Common-Mode Rejection Ratio
V
CM
= 0 V to +3.5 V
72
88
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
= 10 k
to +2.5 V
0.015 to 4.985
V
R
L
= 2 k
to +2.5 V
0.100 to 4.900 0.025 to 4.975
V
R
L
= 150
to +2.5 V
0.300 to 4.625 0.200 to 4.800
V
Output Current
V
OUT
= +0.5 V to +4.5 V
45
mA
T
MIN
to T
MAX
45
mA
Short Circuit Current
Sourcing
80
mA
Sinking
130
mA
Capacitive Load Drive
G = +1
50
pF
POWER SUPPLY
Operating Range
3
12
V
Quiescent Current/Amplifier
4.4
5
mA
Power Supply Rejection Ratio
V
S
=
1 V
70
80
dB
OPERATING TEMPERATURE RANGE
40
+85
C
*Refer to TPC 7.
Specifications subject to change without notice.
(@ T
A
= 25 C, V
S
= +5 V, R
L
= 2 k to +2.5 V,
unless otherwise noted.)
3
REV. A
AD8091/AD8092
(@ T
A
= 25 C, V
S
= +3 V, R
L
= 2 k to +1.5 V, unless otherwise noted.)
SPECIFICATIONS
AD8091A/AD8092A
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Small Signal Bandwidth
G = +1, V
O
= 0.2 V p-p
70
110
MHz
G = 1, +2, V
O
= 0.2 V p-p
50
MHz
Bandwidth for 0.1 dB Flatness
G = +2, V
O
= 0.2 V p-p,
R
L
= 150
to 2.5 V,
R
F
= 402
17
MHz
Slew Rate
G = 1, V
O
= 2 V Step
90
135
V/
s
Full Power Response
G = +1, V
O
= 1 V p-p
65
MHz
Settling Time to 0.1%
G = 1, V
O
= 2 V Step
55
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
*
f
C
= 5 MHz, V
O
= 2 V p-p,
G = 1, R
L
= 100
to +1.5 V
47
dB
Input Voltage Noise
f = 10 kHz
16
nV/
Hz
Input Current Noise
f = 10 kHz
600
fA/
Hz
Differential Gain Error (NTSC)
G = +2, V
CM
= +1 V
R
L
= 150
to +1.5 V
0.11
%
R
L
= 1 k
to +1.5 V
0.09
%
Differential Phase Error (NTSC)
G = +2, V
CM
= +1 V
R
L
= 150
to +1.5 V
0.24
Degrees
R
L
= 1 k
to +1.5 V
0.10
Degrees
Crosstalk
f = 5 MHz, G = +2
60
dB
DC PERFORMANCE
Input Offset Voltage
1.6
10
mV
T
MIN
to T
MAX
25
mV
Offset Drift
10
V/C
Input Bias Current
1.3
2.6
A
T
MIN
to T
MAX
3.25
A
Input Offset Current
0.15
0.8
A
Open-Loop Gain
R
L
= 2 k
80
96
dB
T
MIN
to T
MAX
94
dB
R
L
= 150
74
82
dB
T
MIN
to T
MAX
76
dB
INPUT CHARACTERISTICS
Input Resistance
290
k
Input Capacitance
1.4
pF
Input Common-Mode Voltage Range
0.2 to +2.0
V
Common-Mode Rejection Ratio
V
CM
= 0 V to 1.5 V
72
88
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
= 10 k
to +1.5 V
0.01 to 2.99
V
R
L
= 2 k
to +1.5 V
0.075 to 2.9
0.02 to 2.98
V
R
L
= 150
to +1.5 V
0.20 to 2.75
0.125 to 2.875
V
Output Current
V
OUT
= +0.5 V to +2.5 V
45
mA
T
MIN
to T
MAX
45
mA
Short Circuit Current
Sourcing
60
mA
Sinking
90
mA
Capacitive Load Drive
G = +1
45
pF
POWER SUPPLY
Operating Range
3
12
V
Quiescent Current/Amplifier
4.2
4.8
mA
Power Supply Rejection Ratio
V
S
= +0.5 V
68
80
dB
OPERATING TEMPERATURE RANGE
40
+85
C
*Refer to TPC 7.
Specifications subject to change without notice.
4
REV. A
AD8091/AD8092SPECIFICATIONS
(@ T
A
= 25 C, V
S
= 5 V, R
L
= 2 k to Ground,
unless otherwise noted.)
AD8091A/AD8092A
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
3 dB Small Signal Bandwidth
G = +1, V
O
= 0.2 V p-p
70
110
MHz
G = 1, +2, V
O
= 0.2 V p-p
50
MHz
Bandwidth for 0.1 dB Flatness
G = +2, V
O
= 0.2 V p-p,
R
L
= 150
,
R
F
= 1.1 k
20
MHz
Slew Rate
G = 1, V
O
= 2 V Step
105
170
V/
s
Full Power Response
G = +1, V
O
= 2 V p-p
40
MHz
Settling Time to 0.1%
G = 1, V
O
= 2 V Step
50
ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
f
C
= 5 MHz, V
O
= 2 V p-p, G = +2
71
dB
Input Voltage Noise
f = 10 kHz
16
nV/
Hz
Input Current Noise
f = 10 kHz
900
fA/
Hz
Differential Gain Error (NTSC)
G = +2, R
L
= 150
0.02
%
R
L
= 1 k
0.02
%
Differential Phase Error (NTSC)
G = +2, R
L
= 150
0.11
Degrees
R
L
= 1 k
0.02
Degrees
Crosstalk
f = 5 MHz, G = +2
60
dB
DC PERFORMANCE
Input Offset Voltage
1.8
11
mV
T
MIN
to T
MAX
27
mV
Offset Drift
10
V/C
Input Bias Current
1.4
2.6
A
T
MIN
to T
MAX
3.5
A
Input Offset Current
0.1
0.75
A
Open-Loop Gain
R
L
= 2 k
88
96
dB
T
MIN
to T
MAX
96
dB
R
L
= 150
78
82
dB
T
MIN
to T
MAX
80
dB
INPUT CHARACTERISTICS
Input Resistance
290
k
Input Capacitance
1.4
pF
Input Common-Mode Voltage Range
5.2 to +4.0
V
Common-Mode Rejection Ratio
V
CM
= 5 V to +3.5 V
72
88
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
= 10 k
4.98 to +4.98
V
R
L
= 2 k
4.85 to +4.85 4.97 to +4.97
V
R
L
= 150
4.45 to +4.30 4.60 to +4.60
V
Output Current
V
OUT
= 4.5 V to +4.5 V
45
mA
T
MIN
to T
MAX
45
mA
Short Circuit Current
Sourcing
100
mA
Sinking
160
mA
Capacitive Load Drive
G = +1 (AD8091/AD8092)
50
pF
POWER SUPPLY
Operating Range
3
12
V
Quiescent Current/Amplifier
4.8
5.5
mA
Power Supply Rejection Ratio
V
S
=
1 V
68
80
dB
OPERATING TEMPERATURE RANGE
40
+85
C
Specifications subject to change without notice.
5
AD8091/AD8092
REV. A
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . .
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . .
2.5 V
Output Short Circuit Duration . . . . . . . . . . . . . See Figure 1
Storage Temperature Range . . . . . . . . . . . 65
C to +125C
Operating Temperature Range . . . . . . . . . . . 40
C to +85C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8091/AD8092
package is limited by the associated rise in junction temperature
(T
J
) on the die. The plastic encapsulating the die will locally reach
the junction temperature. At approximately 150
C, which is the
glass transition temperature, the plastic will change its properties.
Even temporarily exceeding this temperature limit may change the
stresses that the package exerts on the die, permanently shifting the
parametric performance of the AD8091/AD8092. Exceeding a
junction temperature of 175
C for an extended period of time can
result in changes in the silicon devices, potentially causing failure.
The still-air thermal properties of the package (
JA
), ambient
temperature (T
A
), and the total power dissipated in the package
(P
D
) can be used to determine the junction temperature of the die.
The junction temperature can be calculated as follows:
T
T
P
A
D
A
J
J
=
+
(
)
The power dissipated in the package (P
D
) is the sum of the quies-
cent power dissipation and the power dissipated in the package
due to the load drive for all outputs. The quiescent power is the
voltage between the supply pins (V
S
) times the quiescent current
(I
S
). Assuming the load (R
L
) is referenced to midsupply, then the
total drive power is V
S
/2 I
OUT
, some of which is dissipated in
the package and some in the load (V
OUT
I
OUT
). The difference
between the total drive power and the load power is the drive
power dissipated in the package.
P
D
= quiescent power + (total drive power load power)
P
V
I
V
V
R
V
R
S
S
S
OUT
L
OUT
L
D
=
(
)
+
2
2
RMS output voltages should be considered. (If R
L
is referenced
to V
S
, as in single-supply operation, then the total drive power is
V
S
I
OUT
.)
If the rms signal levels are indeterminate, then consider the
worst case, when V
OUT
= V
S
/4 for R
L
to midsupply:
P
V
I
V
R
D
S
S
S
L
=
(
)
+
4
2
(In single-supply operation with R
L
referenced to V
S
, worst case is
V
OUT
= V
S
/2.)
Airflow will increase heat dissipation, effectively reducing
JA
. Also,
more metal directly in contact with the package leads from metal
traces, through holes, ground, and power planes will reduce the
JA
.
Care must be taken to minimize parasitic capacitances at the input
leads of high-speed op amps as discussed in the board layout
section.
Figure 1 shows the maximum safe power dissipation in the package
versus the ambient temperature for the SOIC-8 (125
C/W),
SOT23-5 (180
C/W), and SOIC-8 (150C/W) packages on a
JEDEC standard four-layer board.
AMBIENT TEMPERATURE C
2.0
1.0
0
MAXIMUM POWER DISSIPATION
W
30
1.5
0.5
80
40
50
10
10
30
T
J
= 150 C
SOIC-8
SOIC-8
20
0
20
60
70
90
SOT23-5
40
Figure 1. Maximum Power Dissipation vs. Temperature
for a Four-Layer Board
AD8091/AD8092
6
REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8091/AD8092 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Temperature
Package
Package
Branding
Model
Range
Description
Outline
Information
AD8091AR
40
C to +85C
8-Lead SOIC
SO-8
AD8091AR-REEL
40
C to +85C
8-Lead SOIC
13" Tape and Reel
AD8091AR-REEL7
40
C to +85C
8-Lead SOIC
7" Tape and Reel
AD8091ART-REEL
40
C to +85C
5-Lead SOT-23
RT-5, 13" Tape and Reel
HVA
AD8091ART-REEL7
40
C to +85C
5-Lead SOT-23
RT-5, 7" Tape and Reel
HVA
AD8092AR
40
C to +85C
8-Lead SOIC
SO-8
AD8092AR-REEL
40
C to +85C
8-Lead SOIC
13" Tape and Reel
AD8092AR-REEL7
40
C to +85C
8-Lead SOIC
7" Tape and Reel
AD8092ARM
40
C to +85C
8-Lead
SOIC
RM-8
HWA
AD8092ARM-REEL
40
C to +85C
8-Lead
SOIC
13" Tape and Reel
HWA
AD8092ARM-REEL7
40
C to +85C
8-Lead
SOIC
7" Tape and Reel
HWA
7
AD8091/AD8092
REV. A
FREQUENCY MHz
3
2
7
0.1
1
10
100
V
S
= +5V
GAIN AS SHOWN
R
F
AS SHOWN
R
L
= 2k
V
O
= 0.2V p-p
G = +10
R
F
= 2k
G = +5
R
F
= 2k
G = +1
R
F
= 0
G = +2
R
F
= 2k
1
4
5
6
1
0
3
2
500
NORMALIZED GAIN
dB
TPC 1. Normalized Gain vs. Frequency; V
S
= +5 V
FREQUENCY MHz
3
2
7
0.1
500
1
10
100
1
4
5
6
1
0
3
2
V
S
= +3V
V
S
= 5V
V
S
= +5V
V
S
AS SHOWN
G = +1
R
L
= 2k
V
O
= 0.2V p-p
GAIN
dB
TPC 2. Gain vs. Frequency vs. Supply
FREQUENCY MHz
3
2
7
0.1
500
1
10
100
1
4
5
6
1
0
3
2
40 C
+25 C
+85 C
GAIN
dB
V
S
= +5V
G = +1
R
L
= 2k
V
O
= 0.2V p-p
TEMPERATURE AS SHOWN
TPC 3. Gain vs. Frequency vs. Temperature
Typical Performance Characteristics
FREQUENCY MHz
6.3
6.2
5.3
0.1
1
10
100
V
S
= +5V
G = +2
R
L
= 150
R
F
= 806
V
O
= 0.2V p-p
5.9
5.6
5.5
5.4
6.1
6.0
5.7
5.8
GAIN FLATNESS
dB
TPC 4. 0.1 dB Gain Flatness vs. Frequency; G = +2
FREQUENCY MHz
9
8
1
0.1
500
1
10
100
5
2
1
0
7
6
3
4
V
S
AS SHOWN
G = +2
R
L
= 2k
R
F
= 2k
V
O
AS SHOWN
V
S
= +5V
V
O
= 2V p-p
V
S
= 5V
V
O
= 4V p-p
GAIN
dB
TPC 5. Large Signal Frequency Response; G = +2
FREQUENCY MHz
70
20
0.1
500
1
10
100
40
10
0
10
60
50
20
30
0
45
90
135
180
GAIN
PHASE
50
PHASE
MARGIN
V
S
= +5V
R
L
= 2k
OPEN-LOOP GAIN
dB
PHASE
De
g
rees
TPC 6. Open-Loop Gain and Phase vs. Frequency
AD8091/AD8092
8
REV. A
FUNDAMENTAL FREQUENCY MHz
1
2
3
4
5
6
7
8
9 10
20
30
110
70
80
90
100
50
60
40
V
O
= 2V p-p
V
S
= +3V, G = 1
R
F
= 2k , R
L
= 100
V
S
= +5V, G = +2
R
F
= 2k , R
L
= 100
V
S
= +5V, G = +1
R
L
= 100
V
S
= +5V, G = +2
R
F
= 2k , R
L
= 2k
V
S
= +5V, G = +1
R
L
= 2k
TOTAL HARMONIC DISTORTION
dBc
TPC 7. Total Harmonic Distortion
OUTPUT VOLTAGE V p-p
5.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
30
40
120
80
90
100
110
60
70
50
130
V
S
= +5V
R
L
= 2k
G = +2
1MHz
5MHz
10MHz
WORST HARMONIC
dBc
0
TPC 8. Worst Harmonic vs. Output Voltage
FREQUENCY MHz
4.5
0
50
0.1
1
10
3.0
1.5
1.0
0.5
4.0
3.5
2.0
2.5
5.0
OUTPUT VOLTAGE SWING (THD
0.5%)
V p-p
V
S
= +5V
G = 1
R
F
= 2k
R
L
= 2k
TPC 9. Low Distortion Rail-to-Rail Output Swing
0.05
0.00
0.05
0.10
0.15
0.20
0.25
0.10
0
100
50
10
60
20
70
30
80
40
90
MODULATING RAMP LEVEL IRE
0.10
0.06
0
100
50
0.08
0.06
0.04
0.02
0.00
0.02
0.04
10
60
20
70
30
80
40
90
NTSC SUBSCRIBER (3.58MHz)
V
S
= +5, G = +2
R
F
= 2k , R
L
AS SHOWN
V
S
= +5, G = +2
R
F
= 2k , R
L
AS SHOWN
R
L
= 150
R
L
= 1k
R
L
= 1k
R
L
= 150
DIFFERENTIAL
GAIN ERROR
%
DIFFERENTIAL
PHASE ERROR
Degrees
TPC 10. Differential Gain and Phase Errors
1000
100
1
10
10M
100
VOLTAGE NOISE
nA
Hz
1k
10k
100k
1M
10
V
S
= +5V
FREQUENCY Hz
TPC 11. Input Voltage Noise vs. Frequency
100
10
0.1
10
10M
100
1k
10k
100k
1M
1
V
S
= +5V
FREQUENCY Hz
CURRENT NOISE
pA
Hz
TPC 12. Input Current Noise vs. Frequency
9
AD8091/AD8092
REV. A
FREQUENCY MHz
10
20
0.1
500
1
10
100
50
80
90
100
30
40
70
60
V
S
= +5V
R
F
= 2k
R
L
= 2k
V
O
= 2V p-p
CROSSTALK
dB
TPC 13. AD8092 Crosstalk (Output-to-Output) vs. Frequency
FREQUENCY MHz
0
10
100
0.03
500
0.1
1
10
100
40
70
80
90
20
30
60
50
V
S
= +5V
CMRR
dB
TPC 14. CMRR vs. Frequency
FREQUENCY MHz
100.0
0.1
1
10
100
500
3.1
0.1
0.031
0.01
31.0
10.0
0.31
1
V
S
= +5V
G = +1
OUTPUT RESISTANCE
TPC 15. Closed-Loop Output Resistance vs. Frequency
FREQUENCY MHz
20
10
30
50
70
10
0
20
40
60
80
1
500
10
100
0.1
0.01
V
S
= +5V
PSRR
+PSRR
PSRR
dB
TPC 16. PSRR vs. Frequency
INPUT STEPS V p-p
60
0
40
30
20
10
50
70
0.5
2.0
1.0
1.5
SETTLING TIME T
O
0.1%
ns
V
S
= +5V
G = 1
R
L
= 2k
TPC 17. Settling Time vs. Input Step
LOAD CURRENT mA
1.00
0.30
0
0
65
5 10 15 20 25 30 35 40 45 50 55 60
0.90
0.40
0.20
0.10
0.70
0.50
0.80
0.60
70 75 80 85
V
OH
= +85 C
V
OH
= +25 C
V
OH
= 40 C
V
OL
= +85 C
V
OL
= +25 C
V
OL
= 40 C
OUTPUT SATURATION VOLTAGE
V
V
S
= +5V
TPC 18. Output Saturation Voltage vs. Load Current
AD8091/AD8092
10
REV. A
100
90
60
0
5
0.5
1.0
1.5
2.5
3.5
4
4.5
80
70
R
L
= 2k
R
L
= 150
V
S
= +5V
OPEN-LOOP GAIN
dB
OUTPUT VOLTAGE V
2.5
3.0
TPC 19. Open-Loop Gain vs. Output Voltage
1.50V
TPC 20. 100 mV Step Response; G = +1
20ns
2.50V
2.60V
2.40V
TPC 21. 200 mV Step Response; V
S
= +5 V, G = +1
3.5V
2.5V
1.5V
TPC 22. Large Signal Step Response; V
S
= +5 V, G = +2
5V
2.5V
TPC 23. Output Swing; G = 1, R
L
= 2 k
4V
3V
2V
1V
1V
2V
3V
4V
TPC 24. Large Signal Step Response; V
S
=
5 V, G = +1
11
AD8091/AD8092
REV. A
LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Power Supply Bypassing
Power supply pins are actually inputs and care must be taken
so that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply to
ground at all frequencies, thereby shunting or filtering a majority
of the noise.
Decoupling schemes are designed to minimize the bypassing imped-
ance at all frequencies with a parallel combination of capacitors.
0.01
F or 0.001 F (X7R or NPO) chip capacitors are critical
and should be as close as possible to the amplifier package. Larger
chip capacitors, such as the 0.1
F capacitor, can be shared among
a few closely spaced active components in the same signal path.
A 10
F tantalum capacitor is less critical for high-frequency
bypassing and, in most cases, only one per board is needed at
the supply inputs.
Grounding
A ground plane layer is important in densely packed PC boards to
spread the current minimizing parasitic inductances. However,
an understanding of where the current flows in a circuit is critical
to implementing effective high-speed circuit design. The length
of the current path is directly proportional to the magnitude of
parasitic inductances and thus the high-frequency impedance of
the path. High-speed currents in an inductive ground return will
create an unwanted voltage noise.
The length of the high-frequency bypass capacitor leads are most
critical. A parasitic inductance in the bypass grounding will work
against the low impedance created by the bypass capacitor. Place
the ground leads of the bypass capacitors at the same physical
location. Because load currents flow from the supplies as well,
the ground for the load impedance should be at the same physical
location as the bypass capacitor grounds. For the larger value
capacitors, which are intended to be effective at lower frequencies,
the current return path distance is less critical.
Input Capacitance
Along with bypassing and ground, high-speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
A few pF of capacitance will reduce the input impedance at high
frequencies, in turn increasing the amplifier's gain, causing peaking
of the frequency response or even oscillations, if severe enough.
It is recommended that the external passive components, which
are connected to the input pins, be placed as close as possible to
the inputs to avoid parasitic capacitance. The ground and power
planes must be kept at a distance of at least 0.05 mm from the
input pins on all layers of the board.
Input-to-Output Coupling
The input and output signal traces should not be parallel to mini-
mize capacitive coupling between the inputs and output, avoiding
any positive feedback.
DRIVING CAPACITIVE LOADS
A highly capacitive load will react with the output of the amplifiers,
causing a loss in phase margin and subsequent peaking or even
oscillation, as illustrated in Figures 2 and 3. There are two
methods to effectively minimize its effect.
1. Put a small value resistor in series with the output to isolate
the load capacitor from the amps' output stage.
2. Increase the phase margin with higher noise gains or by adding a
pole with a parallel resistor and capacitor from IN to the output.
FREQUENCY MHz
500
0.1
1
10
100
V
S
= +5V
G = +1
R
L
= 2k
C
L
= 50pF
V
O
= 200mV p-p
8
6
4
2
0
2
4
6
8
10
GAIN
dB
Figure 2. Closed-Loop Frequency Response: C
L
= 50 pF
2.60V
2.55V
2.50V
2.45V
2.40V
p
Figure 3. 200 mV Step Response: C
L
= 50 pF
AD8091/AD8092
12
REV. A
As the closed-loop gain is increased, the larger phase margin allows
for large capacitor loads with less peaking. Adding a low value resis-
tor in series with the load at lower gains has the same effect. Figure 4
shows the effect of a series resistor for various voltage gains. For
large capacitive loads, the frequency response of the amplifier
will be dominated by the series resistor and capacitive load.
R
G
R
F
C
L
R
S
V
OUT
V
IN
100mV STEP
50
R
S
= 3
R
S
= 0
10000
1000
1
1
6
2
CAPACITIVE LOAD
P
F
3
4
5
100
10
A
C L
V / V
V
S
= 5V
30%
OVERSHOOT
Figure 4. Capacitive Load Drive vs. Closed-Loop Gain
Overdrive Recovery
Overdrive of an amplifier occurs when the output and/or input
range are exceeded. The amplifier must recover from this over-
drive condition. As shown in Figure 5, the AD8091/AD8092
recovers within 60 ns from negative overdrive and within 45 ns
from positive overdrive.
Figure 5. Overdrive Recovery
Active Filters
Active filters at higher frequencies require wider bandwidth op amps
to work effectively. Excessive phase shift produced by lower
frequency op amps can significantly impact active filter perfor-
mance.
Figure 6 shows an example of a 2 MHz biquad bandwidth filter
that uses three op amps. Such circuits are sometimes used in
medical ultrasound systems to lower the noise bandwidth of the
analog signal before A/D conversion. Please note that the
unused amplifiers' inputs should be tied to ground.
2
1
R1
3k
V
IN
R2
2k
C1
50pF
R3
2k
6
5
7
R6
1k
R5
2k
2
3
6
AD8092
AD8091
C2
50pF
V
OUT
R4
2k
3
AD8092
Figure 6. 2 MHz Biquad Band-Pass Filter
The frequency response of the circuit is shown in Figure 7.
FREQUENCY Hz
10k
100M
100k
1M
10M
0
10
20
30
40
GAIN
dB
Figure 7. Frequency Response of 2 MHz Band-Pass
Biquad Filter
Sync Stripper
Synchronizing pulses are sometimes carried on video signals so as
not to require a separate channel to carry the synchronizing infor-
mation. However, for some functions, such as A/D conversion, it
is not desirable to have the sync pulses on the video signal. These
13
AD8091/AD8092
REV. A
pulses will reduce the dynamic range of the video signal and do
not provide any useful information for such a function.
A sync stripper will remove the synchronizing pulses from a video
signal while passing all the useful video information. Figure 8 shows
a practical single-supply circuit that uses only a single AD8091.
It is capable of directly driving a reverse terminated video line.
AD8091
0.1 F
10 F
+
R1
1k
R2
1k
100
TO A/D
+0.8V
(OR 2 V
BLANK
)
V
IN
+3V OR +5V
V
BLANK
GROUND
+0.4V
VIDEO WITH SYNC
GROUND
VIDEO WITHOUT SYNC
Figure 8. Sync Stripper
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set equal to 2
via the two 1 k
resistors in the feedback circuit. A bias voltage
must be applied to R1 for the input signal to have the sync pulses
stripped at the proper level.
The blanking level of the input video pulse is the desired place
to remove the sync information. This level is multiplied by 2 by
the amplifier. This level must be at ground at the output in
order for the sync stripping action to take place. Since the gain of
the amplifier from the input of R1 to the output is 1, a voltage
equal to 2
V
BLANK
must be applied to make the blanking level
come out at ground.
Single-Supply Composite Video Line Driver
Many composite video signals have their blanking level at
ground and have video information that is both positive and
negative. Such signals require dual-supply amplifiers to pass
them. However, by ac level shifting, a single-supply amplifier
can be used to pass these signals. The following complications
may arise from such techniques.
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their (bounded)
peak-to-peak amplitude after they are ac-coupled. As a worst case,
the dynamic signal swing will approach twice the peak-to-peak
value. The two conditions that define the maximum dynamic
swing requirements are a signal that is mostly low but goes high
with a duty cycle that is a small fraction of a percent. The oppo-
site condition defines the other extreme.
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame but has a white (full amplitude) minimum width
spike at least once in a frame.
The other extreme is a full white video signal. The blanking intervals
and sync tips of such a signal will have negative-going excursions
in compliance with the composite video specifications. The
combination of horizontal and vertical blanking intervals limit
such a signal to being at the highest (white) level for a maximum of
about 75% of the time.
As a result of the duty cycles between the two extremes presented
above, a 1 V p-p composite video signal that is multiplied by a
gain of 2 requires about 3.2 V p-p of dynamic voltage swing at the
output for an op amp to pass a composite video signal of arbitrary
varying duty cycle without distortion.
Some circuits use a sync tip clamp to hold the sync tips at a rela-
tively constant level to lower the amount of dynamic signal swing
required. However, these circuits can have artifacts like sync tip
compression unless they are driven by a source with a very low
output impedance. The AD8091/AD8092 have adequate signal
swing when running on a single +5 V supply to handle an ac-coupled
composite video signal.
The input to the circuit in Figure 9 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac-coupling.
The noninverting input of the op amp is biased to half of the
supply voltage.
AD8091
R
G
1k
R
F
1k
+5V
IN
+
10 F
4.99k
220 F
+
1000 F
0.1 F
R
BT
75
10k
+
47 F
4.99k
R
T
75
R
L
75
V
OUT
COMPOSITE
VIDEO
0.1 F
10 F
+
Figure 9. Single-Supply Composite Video Line Driver
The feedback circuit provides unity gain for the dc biasing of the
input and provides a gain of 2 for any signals that are in the video
bandwidth. The output is ac-coupled and terminated to drive
the line.
The capacitor values were selected for providing minimum "tilt"
or field time distortion of the video signal. These values would be
required for video that is considered to be studio or broadcast
quality. However, if a lower consumer grade of video, sometimes
referred to as "consumer video," is all that is desired, the values
and the cost of the capacitors can be reduced by as much as a
factor of 5 with minimum visible degradation in the picture.
AD8091/AD8092
14
REV. A
Dimensions shown in mm and (inches)
8-Lead SOIC
(R-8)
0.25 (0.0098)
0.19 (0.0075)
1.27 (0.0500)
0.41 (0.0160)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
2.59 (0.102)
2.39 (0.094)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
0.49 (0.0192)
0.35 (0.0138)
8
5
4
1
5.00 (0.1968)
4.80 (0.1890)
PIN 1
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE
ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE
FOR USE IN DESIGN
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
8-Lead SOIC
(RM-8)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33
27
0.120 (3.05)
0.112 (2.84)
Dimensions shown in mm and (inches)
5-Lead Plastic Surface Mount
(RT-5)
3.10 (0.122)
2.70 (0.106)
PIN 1
1.80 (0.071)
1.50 (0.059)
3.00 (0.118)
2.50 (0.098)
1
3
4
5
1.90 (0.075)
REF
0.95 (0.037) REF
2
0.20 (0.008)
0.09 (0.004)
0.60 (0.024)
0.10 (0.004)
10
0
0.50 (0.020)
0.30 (0.012)
0.15 (0.059)
0.00 (0.000)
1.30 (0.051)
0.90 (0.035)
SEATING
PLANE
1.45 (0.057)
0.90 (0.035)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE
ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR
USE IN DESIGN
15
Revision History
Location
Page
5/02Data Sheet changed from REV. 0 to REV. A.
Edits to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edit to TPC 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edits to TPCs 2124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edits to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AD8091/AD8092
REV. A
16
C0285905/02(A)
PRINTED IN U.S.A.
PDF 
ZIP