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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
700 MHz, 5 mA
4-to-1 Video Multiplexer
AD8184
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1997
PRODUCT DESCRIPTION
The AD8184 is a high speed 4-to-1 multiplexer. It offers 3 dB
signal bandwidth of 700 MHz along with a slew rate of 750 V/
s.
With 95 dB of crosstalk and 115 dB isolation, it is useful in
many high speed applications. The differential gain and differ-
ential phase error of 0.01% and 0.01
, along with 0.1 dB flatness
of 75 MHz, make AD8184 ideal for professional video multi-
plexing. It offers 10 ns switching time, making it an excellent
choice for pixel switching (picture-in-picture) while consuming
less than 4.5 mA on
5 V supply voltage.
The AD8184 offers a high speed disable feature allowing the
output to be put into a high impedance state. This allows mul-
tiple outputs to be connected together for cascading stages while
the "OFF" channels do not load the output bus. It operates on
voltage supplies of
5 V and is offered in 14-lead PDIP and
SOIC packages.
*All trademarks are the property of their respective holders.
Table I. Truth Table
ENABLE
A1
A0
OUTPUT
0
0
0
IN0
0
0
1
IN1
0
1
0
IN2
0
1
1
IN3
1
X
X
High Z
FEATURES
Single and Dual 2-to-1 Also Available (AD8180 and AD8182)
Fully Buffered Inputs and Outputs
Fast Channel Switching: 10 ns
High Speed
> 700 MHz Bandwidth (3 dB)
> 750 V/ s Slew Rate
Fast Settling Time of 15 ns to 0.1%
Excellent Video Specifications (R
L
> 2 k )
Gain Flatness of 0.1 dB of 75 MHz
0.01% Differential Gain Error, R
L
= 10 k
0.01 Differential Phase Error, R
L
= 10 k
Low Power: 4.4 mA
Low Glitch: < 25 mV
Low All-Hostile Crosstalk of 95 dB @ 5 MHz
High "OFF" Isolation of 115 dB @ 5 MHz
Low Cost
Fast Output Disable Feature for Connecting Multiple Devices
APPLICATIONS
Pin Compatible with HA4314* and GX4314*
Video Switchers and Routers
Pixel Switching for "Picture-In-Picture"
Switching in LCD and Plasma Displays
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
14
13
12
11
AD8184
ENABLE
A1
5
6
7
10
9
8
OUT
DECODER
+1
+1
+1
+1
A0
+V
S
NC
V
S
NC = NO CONNECT
IN0
GND
IN1
IN2
GND
IN3
GND
FREQUENCY Hz
1M
NORMALIZED OUTPUT dB
10M
100M
1G
5
4
5
3
2
1
0
1
2
3
4
V
IN
= 50mVrms
R
L
= 5k
Figure 1. Small Signal Frequency Response
AD8184SPECIFICATIONS
REV. 0
2
AD8184A
Parameter
Conditions
Min
Typ
Max
Units
SWITCHING CHARACTERISTICS
Channel Switching Time
1
Channel-to-Channel
50% Logic to 10% Output Settling
IN0 = +1 V, IN1 = 1 V
5
ns
50% Logic to 90% Output Settling
10
ns
50% Logic to 99.9% Output Settling
15
ns
ENABLE to Channel ON Time
2
A0, A1
= 0 or 1
50% Logic to 90% Output Settling
IN0 = +1 V, 1 V or IN1 = 1 V, +1 V
12
ns
ENABLE to Channel OFF Time
2
A0, A1 = 0 or 1
50% Logic to 90% Output Settling
IN1 = +1 V, 1 V or IN1 = 1 V, +1 V
22
ns
Channel Switching Transient (Glitch)
3
All Inputs Are Grounded
25
mV
DIGITAL INPUTS
Logic "1" Voltage
A0, A1 and
ENABLE Inputs
2.0
V
Logic "0" Voltage
A0, A1 and
ENABLE Inputs
0.8
V
Logic "1" Input Current
A0, A1,
ENABLE = +4 V
10
200
nA
Logic "0" Input Current
A0, A1,
ENABLE = +0.4 V
2
3
A
DYNAMIC PERFORMANCE
3 dB Bandwidth (Small Signal)
4
AD8184AR
V
IN
= 50 mV rms, R
L
= 5 k
550
700
MHz
3 dB Bandwidth (Large Signal)
AD8184AR
V
IN
= 1 V rms, R
L
= 5 k
105
135
MHz
0.1 dB Bandwidth
4, 5
AD8184AR
V
IN
= 50 mV rms, R
L
= 5 k
60
75
MHz
Slew Rate
2 V Step
600
750
V/
s
Settling Time to 0.1%
2 V Step
15
ns
DISTORTION/NOISE PERFORMANCE
Differential Gain
= 3.58 MHz, R
L
= 2 k
0.2
%
f = 3.58 MHz,
R
L
= 10 k
0.01
0.02
%
Differential Phase
f = 3.58 MHz, R
L
= 2 k
0.2
Degrees
f = 3.58 MHz,
R
L
= 10 k
0.01
0.02
Degrees
All Hostile Crosstalk
6
AD8184AR
= 5 MHz
95
dB
= 30 MHz
78
dB
OFF Isolation
7
AD8184AR
= 5 MHz, R
L
= 30
115
dB
Voltage Noise
= 30 MHz
4.5
nV/
Hz
Total Harmonic Distortion
C
= 10 MHz, V
O
= 2 V p-p, R
L
= 1 k
74
dBc
DC/TRANSFER CHARACTERISTICS
Voltage Gain
8
V
IN
=
1 V
0.982
V/V
Input Offset Voltage
2
8
mV
T
MIN
to T
MAX
15
mV
Input Offset Voltage Drift
5
V/
C
Input Offset Voltage Matching
Channel-to-Channel
0.6
3
mV
Input Bias Current
2.5
7.5
A
T
MIN
to T
MAX
9.5
A
Input Bias Current Drift
5
nA/
C
INPUT CHARACTERISTICS
Input Resistance
1.0
2.4
M
Input Capacitance
Channel Enabled (R Package)
1.6
pF
Channel Disabled (R Package)
1.6
pF
Input Voltage Range
3.3
V
OUTPUT CHARACTERISTICS
Output Voltage Swing
V
IN
=
4 V, R
L
= 2 k
9
3.15
3.2
V
Short Circuit Current
30
mA
Output Resistance
Enabled
28
33
Disabled
10
M
Output Capacitance
Disabled (R Package)
3.2
pF
POWER SUPPLY
Operating Range
4
6
V
Power Supply Rejection Ratio
+PSRR
+V
S
= +4.5 V to +5.5 V, V
S
= 5 V
54
57
dB
Power Supply Rejection Ratio
PSRR
V
S
= 4.5 V to 5.5 V, +V
S
= +5 V
51
54
dB
Quiescent Current
Enabled
4.4
5.2
mA
T
MIN
to T
MAX
5.7
mA
Disabled
2.1
2.9
mA
T
MIN
to T
MAX
2.9
mA
OPERATING TEMPERATURE RANGE
40
+85
C
(@ T
A
= +25 C, V
S
= 5 V, R
L
= 2 k
unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12.6 V
Internal Power Dissipation
2
AD8184 14-Lead Plastic (N) . . . . . . . . . . . . . . . . 1.6 Watts
AD8184 14-Lead Small Outline (R) . . . . . . . . . . 1.0 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Output Short Circuit Duration . . Observe Power Derating Curves
Storage Temperature Range
N & R Package . . . . . . . . . . . . . . . . . . . . . 65
C to +125
C
Lead Temperature Range (Soldering 10 sec) . . . . . . . +300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air: 14-pin plastic package:
JA
= 75
C/Watt
14-pin SOIC package:
JA
= 120
C/Watt, where P
D
= (T
J
T
A
)/
JA
.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD8184AN
40
C to +85
C
14-Lead Plastic DIP
N-14
AD8184AR
40
C to +85
C
14-Lead Narrow SOIC R-14
AD8184AR-REEL 40
C to +85
C
Reel 14-Lead SOIC
R-14
AD8184-EB
Evaluation Board For AD8184R
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8184
is limited by the associated rise in junction temperature. The maxi-
mum safe junction temperature for plastic encapsulated devices is
determined by the glass transition temperature of the plastic,
approximately +150
C. Exceeding this limit temporarily may
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of +175
C for an extended period can result in
device failure.
NOTES
1
ENABLE pin is grounded. IN0 and IN2 = +1 V dc, IN1 and IN3 = 1 V dc. A0 is driven with a 0 V to +5 V pulse, A1 is grounded. Measure transition time from 50% of the A0
input value (+2.5 V) and 10% (or 90%) of the total output voltage transition from IN0 channel voltage (+1 V) to IN1 (1 V), or vice versa. All inputs are measured in a similar
manner using A0 and A1 to select the channels.
2
ENABLE pin is driven with 0 V to +5 V pulse (with 3 ns edges). The state of the A0 and A1 pins determines which input is activated (refer to Table I). Set IN0 and IN2 = +1 V dc,
IN1 and IN3 = 1 V dc, and measure transition time from 50% of
ENABLE pulse (+2.5 V) to 90% of the total output voltage change. In Figure 4,
t
OFF
is the disable time,
t
ON
is the enable time.
3
All inputs are grounded. A0 input is driven with 0 V to +5 V pulse, A1 is grounded. The output is monitored. Speeding the edges of the A0 pulse increases the glitch magnitude
due to coupling via the ground plane. Removing the A0 and A1 terminations will lower the glitch, as does increasing R
L
.
4
Decreasing R
L
slightly lowers the bandwidth. Increasing C
L
significantly lowers the bandwidth (see Figure 18).
5
A resistor (R
S
) placed in series with the multiplexer inputs serves to optimize 0.1 dB flatness, but is not required (see Figure 19.)
6
Select an input that is not being driven (i.e., A0 and A1 are logic 0, IN0 is selected); drive all other inputs with V
IN
= 0.707 V rms and monitor the output at = 5 and 30 MHz.
R
L
= 2 k
(see Figure 12).
7
Multiplexer is disabled (i.e.,
ENABLE = logic 1) and all inputs are driven simultaneously with V
IN
= 0.446 V rms. Output is monitored at = 5 and 30 MHz. R
L
= 30
to simu-
late R
ON
of one enabled multiplexer within a system (see Figure 13). In this mode the output impedance is very high (typ 10 M
), and the signal couples across the package; the
load impedance determines the crosstalk.
8
Voltage gain decreases for lower values of R
L
. The resistive divider formed by the multiplexers enables output resistance (28
) and R
L
causes a gain that increases as R
L-
decreases (i.e., the voltage gain is approximately 0.97 V/V [3% gain error] for R
L
= 1 k
).
9
Larger values of R
L
provide wider output voltage swings, as well as better gain accuracy. See Note 8.
Specifications subject to change without notice.
AD8184
3
REV. 0
While the AD8184 is internally short circuit protected, this may
not be sufficient to guarantee that the maximum junction tempera-
ture (+150
C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum power
derating curves shown in Figure 2.
AMBIENT TEMPERATURE
C
2.5
2.0
0.5
50
90
40
MAXIMUM POWER DISSIPATION Watts
30 20 10
0
10 20
30
40 50
60
80
1.5
1.0
70
14-PIN SOIC
14-PIN DIP PACKAGE
T
J
= +150
C
Figure 2. Maximum Power Dissipation vs. Temperature
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8184 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
4
REV. 0
AD8184Typical Performance Curves
FREQUENCY Hz
1M
NORMALIZED OUTPUT dB
10M
100M
1G
5
4
5
3
2
1
0
1
2
3
4
V
IN
= 50mVrms
R
L
= 5k
R
S
= 0
Figure 6. Small Signal Frequency Response
0.2
0.5
0.4
0.3
0.2
0.1
0.0
0.1
V
IN
= 50mVrms
R
L
= 5k
R
S
= 0
NORMALIZED FLATNESS dB
1M
10M
100M
1G
FREQUENCY Hz
0.3
0.4
0.5
Figure 7. Gain Flatness vs. Frequency
27
6
9
12
15
18
21
24
1M
10M
100M
1G
FREQUENCY Hz
3
0
3
OUTPUT dBV
V
IN
= 1.0Vrms
R
L
= 5k
V
IN
= 0.5Vrms
V
IN
= 0.25Vrms
V
IN
= 125mVrms
V
IN
= 62.5mVrms
Figure 8. Large Signal Frequency Response
DUT OUT
500mV/DIV
5ns/DIV
1V
1V
OUTPUT
A0 PULSE
0 TO 5V
Figure 3 Channel Switching Characteristics
DUT OUT
800mV/DIV
1V
10ns/DIV
t
OFF
+1V
1V
+1V
t
ON
PULSE
0 TO 5V
Figure 4. Enable and Disable Switching Characteristics
25mV/DIV
25ns/DIV
OUTPUT
SWITCHING A0
OUTPUT
SWITCHING A1
A0 and A1 PULSE
0 TO +5V
Figure 5. Channel Switching Transient (Glitch)
AD8184
5
REV. 0
50mV/DIV
5ns/DIV
OUTPUT @ 50mV
OUTPUT @ 100mV
INPUT
Figure 9. Small Signal Transient Response
+
2V/DIV
OUTPUT = 2V
+
INPUT
OUTPUT = 1V
10ns/DIV
Figure 10. Large Signal Transient Response
0.05
0.04
0.03
0.02
0.01
0.00
0.01
0.02
0.03
0.04
0.05
0.05
0.04
0.03
0.02
0.01
0.00
0.01
0.02
0.03
0.04
0.05
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
11
DIFFERENTIAL GAIN %
DIFFERENTIAL PHASE Deg
R
L
= 2k
NTSC
Figure 11. Differential Gain and Phase Error
FREQUENCY Hz
100k
1G
1M
10M
100M
10
20
110
30
40
50
60
70
80
90
100
CROSSTALK dB
V
IN
= 0.707Vrms
R
L
= 2k
OUTPUT
50
V
IN
50
50
AD8184
2k
1
3
5
7
10
Figure 12. All-Hostile Crosstalk vs. Frequency
OFF ISOLATION dB
FREQUENCY Hz
1G
100k
1M
10M
100M
30
40
130
50
60
70
80
90
100
110
120
V
IN
= 0.446 Vrms
R
L
= 30
OUTPUT
50
V
IN
50
AD8184
30
1
3
5
7
10
= LOGIC 1
Figure 13. "OFF" Isolation vs. Frequency
FREQUENCY Hz
100
10
1
10
1M
100
1k
10k
100k
10M
VOLTAGE NOISE nV/ Hz
30M
Figure 14. Voltage Noise vs. Frequency
AD8184Typical Performance Curves
6
REV. 0
FREQUENCY Hz
0
10
70
100k
1M
10M
100M
30
40
50
60
20
V
OUT
= 2V p-p
R
L
= 1k
HARMONIC DISTORTION dBc 80
90
100
2ND HARMONIC
3RD HARMONIC
Figure 15. Harmonic Distortion vs. Frequency
FREQUENCY Hz
100M
10
100
1G
1k
INPUT AND DISABLED OUTPUT IMPEDANCE
10k
100k
1M
10M
100M
10M
100k
10k
1k
100
1M
Z
IN
Z
OUT
(DISABLED)
Z
OUT
(ENABLED)
110
100
90
80
70
60
50
40
30
20
10
150
140
130
120
ENABLED OUTPUT IMPEDANCE
Figure 16. Output & Input Impedance vs. Frequency
FREQUENCY Hz
0.03M
0.01M
10M
500M
0
10
80
20
30
40
50
60
70
PSSR dB
+PSRR
PSRR
1M
100M
Figure 17. Power Supply Rejection vs. Frequency
100pF
33pF
33pF
100pF
10pF
0pF
NORMALIZED FLATNESS dB
FREQUENCY Hz
1M
10M
100M
1G
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
NORMALIZED OUTPUT dB
9
8
7
6
5
4
3
2
1
0
1
V
IN
= 50mVrms
R
L
= 5k
R
S
= 0
Figure 18. Frequency Response vs. Capacitive Load
0.3
0.2
0.1
NORMALIZED FLATNESS dB
V
IN
= 50mVrms
R
L
= 5k
R
S
= 150
10M
100M
FREQUENCY Hz
1M
0.2
0.1
0
0.4
0.5
1G
R
S
= 0
R
S
= 75
R
S
= 0
R
S
= 75
R
S
= 150
0.6
0.7
0.8
4
5
6
9
8
7
3
2
1
0
1
NORMALIZED OUTPUT dB
Figure 19. Frequency Response vs. Input Series Resistance
INPUT VOLTAGE Volts
5
1
5
5
5
4
3
2
1
0
1
2
3
4
4
0
2
4
2
1
3
3
OUTPUT VOLTAGE Volts
Figure 20. Output Voltage vs. Input Voltage, R
L
= 2 k
AD8184
7
REV. 0
series resistors at the input or output. If better flatness response
is desired, an input series resistance (R
S
) may be used (refer to
Figure 19), although this will increase crosstalk. The dc gain of
the AD8184 is almost independent of load for R
L
> 10 k
. For
heavier loads, the dc gain is approximately that of the voltage
divider formed by the output impedance of the mux (typically
28
and R
L
).
High speed disable clamp circuits (not shown) at the bases of
Q3 and Q4 allow the buffers to turn off quickly and cleanly
without dissipating much power once off. Moreover, these
clamps shunt displacement currents flowing through the junc-
tion capacitances of Q1 and Q2 away from the bases of Q3 and
Q4 and to ac ground through low impedances. The two-pole
high-pass frequency response of the T switch formed by these
clamps is a significant improvement over the one-pole high pass
response of a simple series CMOS switch. As a result, board
and package parasitics, especially stray capacitance between
inputs and outputs, may limit the achievable crosstalk and off
isolation.
LAYOUT CONSIDERATIONS:
Realizing the high speed performance attainable with the
AD8184 requires careful attention to board layout and compo-
nent selection. Proper RF design techniques and low parasitic
component selection are mandatory.
Wire wrap boards, prototype boards and sockets are not recom-
mended because of their high parasitic inductance and capaci-
tance. Instead, surface-mount components should be directly
soldered to a printed circuit board (PCB). The PCB should
have a ground plane covering all unused portions of the compo-
nent side of the board to provide a low impedance ground path.
To reduce stray capacitance the ground plane should be removed
from the area near input and output pins.
THEORY OF OPERATION
The AD8184 video multiplexer is designed for fast switching
(10 ns) and wide bandwidth (> 700 MHz). This performance is
attained with low power dissipation (4.4 mA, enabled) through
the use of proprietary circuit techniques and a dielectrically-
isolated complementary bipolar process. This device has a fast
disable function that allows the outputs of several muxes to be
wired in parallel to form a larger mux with little degradation in
switching time. The low disabled output capacitance (3.2 pF)
helps to preserve the system bandwidth in larger matrices. Un-
like earlier CMOS switches, the switched open-loop buffer ar-
chitecture of the AD8184 provides a unidirectional signal path
with minimal switching glitches and constant, low input capaci-
tance. Since the input impedance of these muxes is nearly inde-
pendent of the load impedance and the state of the mux, the
frequency response of the ON channels in a large switch matrix
is not affected by fanout.
Figure 21 shows a block diagram and simplified schematic of the
AD8184, which contains four switched buffers (S0S3) that
share a common output. The decoder logic translates TTL-
compatible logic inputs (A0, A1 and
ENABLE) to internal, dif-
ferential ECL levels for fast, low-glitch switching. The A0 (LSB)
and A1 (MSB) control inputs constitute a two-bit binary word
that determines which of the four buffers is enabled, unless the
ENABLE input is HIGH, in which case all buffers are disabled
and the output is switched to a high impedance state.
Each open-loop buffer is implemented as a complementary
emitter follower that provides high input impedance, symmetric
slew rate and load drive, and high output-to-input isolation due
to its
2
current gain. The selected buffer is biased ON by fast
switched current sources that allow the buffer to turn on quickly.
Dedicated flatness circuits, combined with the open-loop archi-
tecture of the AD8184, keep peaking low (typically < 0.5 dB)
when driving high capacitive loads, without the need for external
AD8184
1
IN0
S3
I1
I2
Q2
Q1
Q3
Q4
6
S2
I1
I2
Q2
Q1
Q3
Q4
S1
I1
I2
Q2
Q1
Q3
Q4
S0
I1
I2
Q2
Q1
Q3
Q4
DECODER
2
GND
3
IN1
5
IN2
GND
4
GND
7
IN3
14
13
12
11
10
9
8
V
EE
NC
OUT
A1
A0
V
CC
NC = NO CONNECT
Figure 21. Block Diagram and Simplified Schematic of the AD8184 Multiplexer
AD8184
8
REV. 0
Chip capacitors should be used for supply bypassing. One end
of the capacitor should be connected to the ground plane and
the other within 1/4 inch of each power pin. An additional large
(4.7
F10
F) tantalum capacitor should be connected in par-
allel with each of the smaller capacitors for low impedance sup-
ply bypassing over a broad range of frequencies.
Signal traces should be as short as possible. Stripline or
microstrip techniques should be used for long (longer than
about 1 inch) signal traces. These should be designed with a
characteristic impedance of 50
or 75
and be properly ter-
minated at each end using surface mount components.
Careful layout is imperative to minimize crosstalk. Guards
(ground or supply traces) must be run between all signal traces
to limit direct capacitive coupling. Input and output signal lines
should fan out away from the mux as much as possible. If mul-
tiple signal layers are available, a buried stripline structure hav-
ing ground plane above, below and between signal traces will
have the best crosstalk performance.
Return currents flowing through termination resistors can also
increase crosstalk if these currents flow in sections of the finite-
impedance ground circuit shared between more than one input
or output. Minimizing the inductance and resistance of the ground
plane can reduce this effect, but further care should be taken in po-
sitioning the terminations. Terminating cables directly at the con-
nectors will minimize the return current flowing on the board, but
the signal trace between the connector and the mux will look like
an open stub and will degrade the frequency response. Moving the
termination resistors close to the input pins will improve the fre-
quency response, but the terminations from neighboring inputs
should not have a common ground return.
APPLICATIONS
A Buffered 4-to-1 Multiplexer
In applications where the output of a multiplexer must drive a
back-terminated 75
line (R
L
= 75
+ 75
), it is necessary
to buffer the output of the AD8184. In the example in Figure
22, this is accomplished using the AD8009 high speed current
feedback op amp. The amplifier is configured with a gain of 2 to
compensate for the signal halving due to termination at the multi-
plexer input. This gives the overall circuit a gain of unity.
If lower speed can be tolerated, a number of other amplifiers
can replace the AD8009 op amp in the above circuit. In general
there is a trade-off between bandwidth and power consumption.
Table II summarizes the bandwidth and power consumption
characteristics of these op amps.
Table II. Amplifier Options for Multiplexer Buffering
Op Amp Comments
AD8009
Highest Bandwidth, (G = +2) = 700 MHz, I
SY
=
14 mA
AD8001
Lower Power Consumption, Bandwidth (G = +2) =
440 MHz, I
SY
= 5 mA
AD8011
Lower Power Consumption, Bandwidth (G = +2) =
210 MHz, I
SY
= 1 mA
AD8079
Fixed Gain Dual Amplifier (2 or 2.2), Bandwidth =
260 MHz, I
SY
= 5 mA Per Amp
AD8005
Lowest Power Consumption, Bandwidth (G = +2) =
170 MHz, I
SY
= 400
A
V
S
681
+1
DECODER
1
2
3
4
5
6
7
14
13
12
11
10
9
8
+1
+1
+1
AD8184
75
75
75
75
+V
S
NC
V
S
GND
GND
GND
0.1F
10F
V
OUT
0.1F
10F
10F
0.1F
+V
S
+V
S
10F
0.1F
A0
A1
75
V
S
681
AD8009
IN0
IN1
IN2
IN3
Figure 22. A Buffered 4-to-1 Multiplexer
AD8184
9
REV. 0
Color Document Scanner
Figure 23 shows a block diagram of a Color Document Scanner.
Charge Coupled Devices (CCDs) find widespread use in scan-
ner applications. A monochrome CCD delivers a serial stream
of voltages levels, each level being proportional to the light shin-
ing on that cell. In the case of the color image scanner shown,
there are three output streams, representing red, green and blue.
Interlaced with the stream of voltage levels is a voltage repre-
senting the reset level (or black level) of each cell. A Correlated
Double Sampler (CDS) subtracts these two voltages from each
other in order to eliminate the relatively large offsets common
with CCDs.
CONTROL & TIMING
CDS
CDS
0.1F
10F
V
IN
B
V
REF
SENSE
V
IN
A
AD9220
10/12-BIT
10MSPS
A/D
CONVERTER
OUT
CDS
A1
A0
AD8184
R
G
ENABLE
B
CCD
REFERENCE
Figure 23. Color Document Scanner
The next step in the data acquisition process involves digitizing
the three signal streams. Assuming that the analog-to-digital
converter chosen has a fast enough sample rate, multiplexing
the three streams into a single ADC is generally more economi-
cal than using one ADC per channel. In the example shown, we
use the AD8184 as the multiplexer.
Because of its high bandwidth, the AD8184 is capable of driving
the switched capacitor input stage of the AD9220 without addi-
tional buffering. In addition to having the required bandwidth,
it is necessary to consider the settling time of the multiplexer. In
this case, the ADC has a sample rate of 10 MHz, which corre-
sponds to a sampling period of 100 ns. Typically, one phase of
the sampling clock is used for conversion (i.e., all levels are held
steady) and the other is used for switching and settling to the
next channel. Assuming a 50% duty cycle, the signal chain must
settle within 50 ns. With a settling time to 0.1% of 15 ns, the
multiplexer easily satisfies this criterion.
In the example shown, the fourth (spare) channel of the
AD8184 is used to measure a reference voltage. This voltage
would probably be measured less frequently than the R, G and
B signals. Multiplexing a reference voltage offers the advantage
that any temperature drift effects caused by the multiplexer will
equally impact the reference voltage and the to-be-measured sig-
nals. If the fourth channel is unused, it is good design practice
to permanently tie it to ground.
A 4 4 Crosspoint Switch
While large crosspoint arrays are best constructed using highly
integrated devices such as the AD8116, 16
16 crosspoint
switch, smaller or irregular sized arrays can be constructed using
4-to-1 multiplexers such as the AD8184. The circuit below
shows a 4
4 array, constructed using the AD8184 and buff-
ered using the AD8079, a dual, fixed gain of 2 or 2.2, video
amplifier.
750
750
OUT
1/2 AD8079*
AD8184
IN0-IN3
OUT0
750
750
OUT
1/2 AD8079*
AD8184
IN0-IN3
OUT1
750
750
OUT
1/2 AD8079*
AD8184
IN0-IN3
OUT2
750
750
OUT
1/2 AD8079*
AD8184
IN0-IN3
OUT3
IN0-3
4
4
4
4
4
*AD8079 IS A DUAL, FIXED GAIN OF 2 AMPLIFIER
Figure 24. 4
4 Crosspoint Switch
AD8184
10
REV. 0
V
S
+1
DECODER
1
2
3
4
5
6
7
14
13
12
11
10
9
8
+1
+1
+1
AD8184
R3
49.9
+V
S
NC
V
S
GND
GND
GND
0.1F
10F
+V
S
10F
0.1F
IN0
IN1
IN2
IN3
C2
C1
A0
A1
OUT
(SCOPE PROBE ADAPTER)
R5
49.9
R6
49.9
R7
49.9
R8
4.99k
R2
49.9
R1
49.9
R4
49.9
C4
C3
Figure 25. AD8184AR Evaluation Board
EVALUATION BOARD
An evaluation board is available for the AD8184. It has been
carefully laid out and tested to demonstrate the specified high
speed performance of the devices. Figure 25 shows the sche-
matic of the evaluation board. For ordering information,
please refer to the Ordering Guide.
Figure 26 shows the silkscreen of the component side and Fig-
ure 28 shows the silkscreen of the solder side. Figures 27 and 29
show the layout of the component side and solder side respectively.
The evaluation board is provided with 49.9
termination resis-
tors on all inputs. This is to allow the performance to be evalu-
ated at very high frequencies where 50
termination is most
popular. To use the evaluation board in video applications, the
termination resistors should be replaced with 75
resistors.
The FR4 board type has the following stripline dimensions:
60-mil width, 12-mil gap between center conductor and outside
ground plane "island" and 62-mil board thickness.
The multiplexer output is loaded with a 4.99 k
resistor. For
connection to external instruments, an oscilloscope probe
adapter is provided. This allows direct connection of an FET
probe to the board. For verification of data sheet specifications,
use of an FET probe is recommended because of its low input
capacitance. The probe adapter used on the board has the same
footprint as SMA, SMB and SMC type connectors, allowing
easy replacement if necessary.
The side-launched SMA connectors on the analog and digital
inputs can also be replaced by top-mount SMA, SMB or SMC
type connectors. When using top-mount connectors, the
stripline on the outside 1/8" of the board edge should be re-
moved with an X-acto blade as this unused stripline acts as an
open stub, which could degrade the small-signal frequency re-
sponse of the multiplexer.
Input termination resistor placement on the evaluation board is
critical to reducing crosstalk. Each termination resistor is ori-
ented so that the ground return currents flow counterclockwise
to the ground plane "island." Although the direction of this
ground current flow is arbitrary, it is important that no two in-
put or output termination resistors share a connection to the
same ground "island."
AD8184
11
REV. 0
Figure 26. Component Side Silkscreen
Figure 27. Board Layout (Component Side)
Figure 28. Solder Side Silkscreen
Figure 29. Board Layout (Solder Side)
AD8184
12
REV. 0
C3036104/97
PRINTED IN U.S.A.
12
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP
(N-14)
14
1
7
8
0.795 (20.19)
0.725 (18.42)
0.280 (7.11)
0.240 (6.10)
PIN 1
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
14-Lead SOIC
(R-14)
14
8
7
1
0.3444 (8.75)
0.3367 (8.55)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
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