REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8313
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
0.1 GHz2.5 GHz, 70 dB
Logarithmic Detector/Controller
FUNCTIONAL BLOCK DIAGRAM
+
+
+
+
+
AD8313
VOUT
VSET
COMM
PWDN
GAIN
BIAS
BAND-GAP
REFERENCE
SLOPE
CONTROL
INTERCEPT
CONTROL
EIGHT 8dB 3.5GHz AMPLIFIER STAGES
8dB
8dB
VPOS
INHI
INLO
VPOS
8dB
8dB
NINE DETECTOR CELLS
C
INT
LP
I
v
V
V
v
I
FEATURES
Wide Bandwidth: 0.1 GHz to 2.5 GHz Min
High Dynamic Range: 70 dB to 3.0 dB
High Accuracy: 1.0 dB over 65 dB Range (@ 1.9 GHz)
Fast Response: 40 ns Full-Scale Typical
Controller Mode with Error Output
Scaling Stable Over Supply and Temperature
Wide Supply Range: +2.7 V to +5.5 V
Low Power: 40 mW at 3 V
Power-Down Feature: 60 W at 3 V
Complete and Easy to Use
APPLICATIONS
RF Transmitter Power Amplifier Setpoint
Control and Level Monitoring
Logarithmic Amplifier for RSSI Measurement
Cellular Base Stations, Radio Link, Radar
PRODUCT DESCRIPTION
The AD8313 is a complete multistage demodulating logarith-
mic amplifier, capable of accurately converting an RF signal at
its differential input to an equivalent decibel-scaled value at its
dc output. The AD8313 maintains a high degree of log con-
formance for signal frequencies from 0.1 GHz to 2.5 GHz and
is useful over the range of 10 MHz to 3.5 GHz. The nominal
input dynamic range is 65 dBm to 0 dBm (re: 50
), and the
sensitivity can be increased by 6 dB or more with a narrow band
input impedance matching network or balun. Application is
straightforward, requiring only a single supply of 2.7 V5.5 V
and the addition of a suitable input and supply decoupling.
Operating on a 3 V supply, its 13.7 mA consumption (for T
A
=
+25
C) amounts to only 41 mW. A power-down feature is
provided; the input is taken high to initiate a low current
(20
A) sleep mode, with a threshold at half the supply voltage.
The AD8313 uses a cascade of eight amplifier/limiter cells,
each having a nominal gain of 8 dB and a 3 dB bandwidth of
3.5 GHz, for a total midband gain of 64 dB. At each amplifier
output, a detector (rectifier) cell is used to convert the RF signal
to baseband form; a ninth detector cell is placed directly at the
input of the AD8313. The current-mode outputs of these cells
are summed to generate a piecewise linear approximation to the
logarithmic function, and converted to a low impedance voltage-
mode output by a transresistance stage, which also acts as a low-
pass filter.
When used as a log amp, the scaling is determined by a separate
feedback interface (a transconductance stage) that sets the slope
to approximately 18 mV/dB; used as a controller, this stage
accepts the setpoint input. The logarithmic intercept is posi-
tioned to nearly 100 dBm, and the output runs from about
0.45 V dc at 73 dBm input to 1.75 V dc at 0 dBm input. The
scale and intercept are supply and temperature stable.
The AD8313 is fabricated on Analog Devices' advanced
25 GHz silicon bipolar IC process and is available in a 8-lead
SOIC package. The operating temperature range is 40
C to
+85
C. An evaluation board is available.
INPUT AMPLITUDE dBm
2.0
80
OUTPUT VOLTAGE Volts DC
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
70
60
50
40
30
20
10
0
FREQUENCY = 1.9GHz
5
4
3
2
1
0
1
2
3
4
5
OUTPUT ERROR dB
Figure 1. Typical Logarithmic Response and Error vs.
Input Amplitude
2
REV. B
AD8313SPECIFICATIONS
(@ T
A
= +25 C, V
S
= +5.0 V
1
, R
L
10 k
unless otherwise noted)
Parameter
Conditions
Min
2
Typ
Max
2
Units
SIGNAL INPUT INTERFACE
Specified Frequency Range
0.1
2.5
GHz
DC Common-Mode Voltage
V
POS
0.75
V
Input Bias Currents
10
A
Input Impedance
f
RF
< 100 MHz
3
900 1.1
pF
4
LOG (RSSI) MODE
Sinusoidal, input termination configuration shown in Figure 27.
100 MHz
5
Nominal Conditions
3 dB Dynamic Range
6
53.5
65
dB
Range Center
31.5
dBm
1 dB Dynamic Range
56
dB
Slope
17
19
21
mV/dB
Intercept
96
88
80
dBm
+2.7 V
V
S
+5.5 V, 40
C
T
+85
C
3 dB Dynamic Range
51
64
dB
Range Center
31
dBm
1 dB Dynamic Range
55
dB
Slope
16
19
22
mV/dB
Intercept
99
89
75
dBm
Temperature Sensitivity
P
IN
= 10 dBm
0.022
dB/
C
900 MHz
5
Nominal Conditions
3 dB Dynamic Range
60
69
dB
Range Center
32.5
dBm
1 dB Dynamic Range
62
dB
Slope
15.5
18
20.5
mV/dB
Intercept
105
93
81
dBm
+2.7 V
V
S
+5.5 V, 40
C
T
+85
C
3 dB Dynamic Range
55.5
68.5
dB
Range Center
32.75
dBm
1 dB Dynamic Range
61
dB
Slope
15
18
21
mV/dB
Intercept
110
95
80
dBm
Temperature Sensitivity
P
IN
= 10 dBm
0.019
dB/
C
1.9 GHz
7
Nominal Conditions
3 dB Dynamic Range
52
73
dB
Range Center
36.5
dBm
1 dB Dynamic Range
62
dB
Slope
15
17.5
20.5
mV/dB
Intercept
115
100
85
dBm
+2.7 V
V
S
+5.5 V, 40
C
T
+85
C
3 dB Dynamic Range
50
73
dB
Range Center
36.5
dBm
1 dB Dynamic Range
60
dB
Slope
14
17.5
21.5
mV/dB
Intercept
125
101
78
dBm
Temperature Sensitivity
P
IN
= 10 dBm
0.019
dB/
C
2.5 GHz
7
Nominal Conditions
3 dB Dynamic Range
48
66
dB
Range Center
34
dBm
1 dB Dynamic Range
46
dB
Slope
16
20
25
mV/dB
Intercept
111
92
72
dBm
+2.7 V
V
S
+5.5 V, 40
C
T
+85
C
3 dB Dynamic Range
47
68
dB
Range Center
34.5
dBm
1 dB Dynamic Range
46
dB
Slope
14.5
20
25
mV/dB
Intercept
128
92
56
dBm
Temperature Sensitivity
P
IN
= 10 dBm
0.040
dB/
C
3
REV. B
AD8313
Parameter
Conditions
Min
2
Typ
Max
2
Units
3.5 GHz
5
3 dB Dynamic Range
43
dB
1 dB Dynamic Range
35
dB
Slope
24
mV/dB
Intercept
65
dBm
CONTROL MODE
Controller Sensitivity
f = 900 MHz
23
V/dB
Low Frequency Gain
VSET to VOUT
8
84
dB
Open-Loop Corner Frequency
VSET to VOUT
8
700
Hz
Open-Loop Slew Rate
f = 900 MHz
2.5
V/
s
VSET Delay Time
150
ns
VOUT INTERFACE
Current Drive Capability
Source Current
400
A
Sink Current
10
mA
Minimum Output Voltage
Open Loop
50
mV
Maximum Output Voltage
Open Loop
V
POS
0.1
V
Output Noise Spectral Density
P
IN
= 60 dBm, f
SPOT
= 100 Hz
2.0
V/
Hz
P
IN
= 60 dBm, f
SPOT
= 10 MHz
1.3
V/
Hz
Small Signal Response Time
P
IN
= 60 dBm to 57 dBm, 10% to 90%
40
60
ns
Large Signal Response Time
P
IN
= No Signal to 0 dBm, Settled to 0.5 dB
110
160
ns
VSET INTERFACE
Input Voltage Range
0
V
POS
V
Input Impedance
18k 1
pF
POWER-DOWN INTERFACE
PWDN Threshold
V
POS
/2
V
Power-Up Response Time
Time delay following HI to LO transition
until device meets full specifications.
1.8
s
PWDN Input Bias Current
PWDN = 0 V
5
A
PWDN = V
S
<1
A
POWER SUPPLY
Operating Range
+2.7
+5.5
V
Powered Up Current
13.7
15.5
mA
+4.5 V
V
S
+5.5 V, 40
C
T
+85
C
18.5
mA
+2.7 V
V
S
+3.3 V, 40
C
T
+85
C
18.5
mA
Powered Down Current
+4.5 V
V
S
+5.5 V, 40
C
T
+85
C
50
150
A
+2.7 V
V
S
+3.3 V, 40
C
T
+85
C
20
50
A
NOTES
1
Except where otherwise noted, performance at V
S
= +3.0 V is equivalent to +5.0 V operation.
2
Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values.
3
Input impedance shown over frequency range in Figure 24.
4
Double slashes ( ) denote "in parallel with."
5
Linear regression calculation for error curve taken from 40 dBm to 10 dBm for all parameters.
6
Dynamic range refers to range over which the linearity error remains within the stated bound.
7
Linear regression calculation for error curve taken from 60 dBm to 5 dBm for 3 dB dynamic range. All other regressions taken from 40 dBm to 10 dBm.
8
AC response shown in Figure 10.
Specifications subject to change without notice.
AD8313
4
REV. B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8313 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy [>250 V HBM] electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
VOUT, VSET, PWDN . . . . . . . . . . . . . . . . . . . . . . 0 V, VPOS
Input Power Differential (re: 50
, 5.5 V) . . . . . . . . . +25 dBm
Input Power Single-Ended (re: 50
, 5.5 V) . . . . . . . +19 dBm
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 200 mW
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . +125
C
Operating Temperature Range . . . . . . . . . . . . 40
C to +85
C
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150
C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may effect device reliability.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
VPOS
INHI
INLO
VPOS
VOUT
VSET
COMM
PWDN
AD8313
PIN FUNCTION DESCRIPTIONS
Pin
Name
Description
1, 4
VPOS
Positive supply voltage (VPOS), +2.7 V to
+5.5 V.
2
INHI
Noninverting Input. This input should be
ac coupled.
3
INLO
Inverting Input. This input should be ac
coupled.
5
PWDN
Connect pin to ground for normal operat-
ing mode. Connect pin to supply for power-
down mode.
6
COMM
Device Common.
7
VSET
Setpoint input for operation in controller
mode. To operate in RSSI mode, short
VSET and VOUT.
8
VOUT
Logarithmic/Error Output.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Temperature
Package
Package
Brand
Model
Range
Descriptions
Option
Code
AD8313ARM
40
C to +85
C
8-Lead
SOIC
RM-08
J1A
AD8313ARM-REEL
40
C to +85
C
13" Tape and Reel
RM-08
J1A
AD8313ARM-REEL7
40
C to +85
C
7" Tape and Reel
RM-08
J1A
AD8313-EVAL
Evaluation Board
AD8313
5
REV. B
INPUT AMPLITUDE dBm
2.0
70
V
OUT
Volts
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
60
50
40
30
20
10
0
10
V
S
= +5V
INPUT MATCH SHOWN IN FIGURE 27
1.9GHz
2.5GHz
900MHz
100MHz
Figure 2. V
OUT
vs. Input Amplitude
INPUT AMPLITUDE dBm
6
6
70
10
60
ERROR dB
50
40
30
20
10
0
4
2
0
2
4
900MHz
100MHz
100MHz
900MHz
1.9GHz
2.5GHz
2.5GHz
1.9GHz
V
S
= +5V
INPUT MATCH SHOWN IN FIGURE 27
Figure 3. Log Conformance vs. Input Amplitude
INPUT AMPLITUDE dBm
2.0
70
V
OUT
Volts
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
60
50
40
30
20
10
0
10
V
S
= +5V
INPUT MATCH SHOWN IN FIGURE 27
5
4
3
2
1
0
1
2
3
4
5
ERROR dB
40 C
+25 C
+85 C
SLOPE AND INTERCEPT NORMALIZED AT +25 C
AND APPLIED TO 40 C AND +85 C
Figure 4. V
OUT
and Log Conformance vs. Input Amplitude
at 100 MHz; 40
C, +25
C and +85
C
Typical Performance Characteristics
INPUT AMPLITUDE dBm
2.0
70
V
OUT
Volts
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
60
50
40
30
20
10
0
10
V
S
= +5V
INPUT MATCH SHOWN IN FIGURE 27
5
4
3
2
1
0
1
2
3
4
5
ERROR dB
+25 C
+85 C
40 C
SLOPE AND INTERCEPT NORMALIZED AT +25 C
AND APPLIED TO 40 C AND +85 C
Figure 5. V
OUT
and Log Conformance vs. Input Amplitude
at 900 MHz; 40
C, +25
C and +85
C
INPUT AMPLITUDE dBm
2.0
70
V
OUT
Volts
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
60
50
40
30
20
10
0
10
V
S
= +5V
INPUT MATCH SHOWN IN FIGURE 27
5
4
3
2
1
0
1
2
3
4
5
ERROR dB
40 C
+25 C
+85 C
SLOPE AND INTERCEPT NORMALIZED AT +25 C
AND APPLIED TO 40 C AND +85 C
Figure 6. V
OUT
and Log Conformance vs. Input Amplitude
at 1.9 GHz; 40
C, +25
C and +85
C
INPUT AMPLITUDE dBm
2.0
70
V
OUT
Volts
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
60
50
40
30
20
10
0
10
V
S
= +5V
INPUT MATCH SHOWN IN FIGURE 27
5
4
3
2
1
0
1
2
3
4
5
ERROR dB
40 C
+25 C
+85 C
SLOPE AND INTERCEPT
NORMALIZED AT +25 C AND
APPLIED TO 40 C AND +85 C
Figure 7. V
OUT
and Log Conformance vs. Input Amplitude
at 2.5 GHz; 40
C, +25
C and +85
C
AD8313
6
REV. B
FREQUENCY MHz
22
21
16
0
2500
500
SLOPE mV/dB
1000
1500
2000
20
19
18
17
V
PS
= +5V
INPUT MATCH SHOWN IN FIGURE 27
40 C
+25 C
+85 C
Figure 8. V
OUT
Slope vs. Frequency; 40
C, +25
C and
+85
C
SUPPLY VOLTAGE V
24
2.5
SLOPE mV/dB
23
22
21
20
19
18
17
16
15
14
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.9GHz
2.5GHz
900MHz
100MHz
SPECIFIED OPERATING RANGE
Figure 9. V
OUT
Slope vs. Supply Voltage
FREQUENCY Hz
V
SET
TO V
OUT
GAIN dB
100
1k
10k
100k
1M
REF LEVEL = 92dB
SCALE: 10dB/DIV
Figure 10. AC Response from V
SET
to V
OUT
FREQUENCY MHz
110
0
2500
500
INTERCEPT dBm
1000
1500
2000
70
80
90
100
+85 C
40 C
+25 C
V
PS
= +5V
INPUT MATCH SHOWN IN FIGURE 27
Figure 11. V
OUT
Intercept vs. Frequency; 40
C, +25
C and
+85
C
SUPPLY VOLTAGE V
70
2.5
INTERCEPT dBm
75
80
85
90
95
100
105
110
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.9GHz
2.5GHz
900MHz
100MHz
SPECIFIED OPERATING RANGE
Figure 12. V
OUT
Intercept vs. Supply Voltage
FREQUENCY Hz
100
10
0.1
V/ Hz
1
1k
10k
100k
1M
10M
2GHz RF INPUT
V
S
= +5.5V
INPUT MATCH SHOWN
IN FIGURE 27
RF INPUT
70dBm
60dBm
55dBm
50dBm
45dBm
40dBm
35dBm
30dBm
Figure 13. V
OUT
Noise Spectral Density
AD8313
7
REV. B
PWDN VOLTAGE V
0
100.00
SUPPLY CURRENT mA
10.00
1.00
0.10
0.01
1
2
3
4
5
40 A
V
POS
= +5V
V
POS
= +3V
20 A
13.7mA
Figure 14. Typical Supply Current vs. PWDN Voltage
CH. 1 & CH. 2: 1V/DIV
CH. 3: 5V/DIV
HORIZONTAL: 1 s/DIV
V
OUT
@
V
S
= +5.5V
V
OUT
@
V
S
= +2.7V
PWDN
CH. 1 GND
CH. 2 GND
CH. 3 GND
Figure 15. PWDN Response Time
0.1 F
54.9
0.01 F
0.01 F
10
10
0.1 F
+V
S
+V
S
TEK
TDS784C
SCOPE
8
7
6
5
1
2
3
4
VPOS
VOUT
INHI
INLO
VPOS PWDN
COMM
VSET
AD8313
TEK P6205
FET PROBE
TRIG
0603 SIZE SURFACE
MOUNT COMPONENTS ON
A LOW LEAKAGE PC BOARD
EXT TRIG
OUT
HP8112A
PULSE
GENERATOR
PIN = 0dBm
RF OUT
HP8648B
SIGNAL
GENERATOR
10MHz REF OUTPUT
Figure 16. Test Setup for PWDN Response Time
CH. 1
CH. 1 GND
CH. 2 GND
CH. 2
CH. 1 & CH. 2: 200mV/DIV
AVERAGE: 50 SAMPLES
V
S
= +5.5V
V
S
= +2.7V
HORIZONTAL: 50ns/DIV
PULSED RF
100MHz, 45dBm
Figure 17. Response Time, No Signal to 45 dBm
CH. 1 & CH. 2: 500mV/DIV
AVERAGE: 50 SAMPLES
HORIZONTAL: 50ns/DIV
CH. 1 GND
CH. 2 GND
PULSED RF
100MHz, 0dBm
CH. 1
CH. 2
V
S
= +5.5V
V
S
= +2.7V
Figure 18. Response Time, No Signal to +0 dBm
0.1 F
54.9
0.01 F
0.01 F
10
10
0.1 F
+V
S
+V
S
TEK
TDS784C
SCOPE
8
7
6
5
1
2
3
4
VPOS
VOUT
INHI
INLO
VPOS PWDN
COMM
VSET
AD8313
TEK P6205
FET PROBE
TRIG
OUT
0603 SIZE SURFACE
MOUNT COMPONENTS ON
A LOW LEAKAGE PC BOARD
EXT TRIG
HP8112A
PULSE
GENERATOR
RF OUT
10MHz REF OUTPUT
6dB
RF
SPLITTER
6dB
HP8648B
SIGNAL
GENERATOR
PULSE
MODULATION
MODE
PULSE MODE IN
OUT
TRIG
Figure 19. Test Setup for RSSI-Mode Pulse Response
AD8313
8
REV. B
CIRCUIT DESCRIPTION
The AD8313 is essentially an 8-stage logarithmic amplifier,
specifically designed for use in RF measurement and power
amplifier control applications at frequencies up to 2.5 GHz. A
block diagram is shown in Figure 20. (For a full treatment of
log-amp theory and design principles, consult the AD8307
data sheet).
+
+
+
+
+
AD8313
VOUT
VSET
COMM
PWDN
GAIN
BIAS
BAND-GAP
REFERENCE
SLOPE
CONTROL
INTERCEPT
CONTROL
EIGHT 8dB 3.5GHz AMPLIFIER STAGES
8dB
8dB
VPOS
INHI
INLO
VPOS
8dB
8dB
NINE DETECTOR CELLS
C
INT
LP
I
v
V
V
v
I
Figure 20. Block Diagram
A fully-differential design is used, and the inputs INHI and INLO
(Pins 2 and 3) are internally biased to approximately 0.75 V
below the supply voltage, and present a low frequency imped-
ance of nominally 900
in parallel with 1.1 pF. The noise
spectral density referred to the input is 0.6 nV/
Hz, equivalent
to a voltage of 35
V rms in a 3.5 GHz bandwidth, or a noise
power of 76 dBm re: 50
. This sets the lower limit to the
dynamic range; the Applications section shows how to increase
the sensitivity by the use of a matching network or input trans-
former. However, the low end accuracy of the AD8313 is enhanced
by specially shaping the demodulation transfer characteristic to
partially compensate for errors due to internal noise.
Each of the eight cascaded stages has a nominal voltage gain of
8 dB and a bandwidth of 3.5 GHz, and is supported by preci-
sion biasing cells which determine this gain and stabilize it
against supply and temperature variations. Since these stages are
direct-coupled and the dc gain is high, an offset-compensation
loop is included. The first four of these stages, and the biasing
system, are powered from Pin 4, while the later stages and the
output interfaces are powered from Pin 1. The biasing is con-
trolled by a logic interface PWDN (Pin 5); this is grounded for
normal operation, but may be taken high (to V
S
) to disable the
chip. The threshold is at V
POS
/2 and the biasing functions are
enabled and disabled within 1.8
s.
Each amplifier stage has a detector cell associated with its out-
put. These nonlinear cells essentially perform an absolute-value
(full-wave rectification) function on the differential voltages
along this backbone, in a transconductance fashion; their out-
puts are in current-mode form and are thus easily summed. A
ninth detector cell is added at the input of the AD8313. Since
the mid-range response of each of these nine detector stages is
separated by 8 dB, the overall dynamic range is about 72 dB
(Figure 21). The upper end of this range is determined by the
capacity of the first detector cell, and occurs at approximately
0 dBm. The practical dynamic range is over 70 dB, to the
3 dB error points. However, some erosion of this range will
occur at temperature and frequency extremes. Useful operation to
over 3 GHz is possible, and the AD8313 remains serviceable at
10 MHz (see Typical Performance Characteristics), needing
only a small amount of additional ripple filtering.
INPUT AMPLITUDE dBm
2.0
80
V
OUT
Volts
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
70
60
50
40
30
20
10
0
5
4
3
2
1
0
1
2
3
4
5
ERROR dB
90
INTERCEPT = 100dBm
SLOPE = 18mV/dB
Figure 21. Typical RSSI Response and Error vs. Input
Power at 1.9 GHz
The fluctuating current output generated by the detector cells,
with a fundamental component at twice the signal frequency, is
filtered first by a low-pass section inside each cell, and also by
the output stage. The output stage converts these currents to a
voltage, V
OUT
, at pin VOUT (Pin 8), which can swing "rail-to-
rail." The filter exhibits a two-pole response with a corner at
approximately 12 MHz and full-scale rise time (10%90%) of
40 ns. The residual output ripple at an input frequency of
100 MHz has an amplitude of under 1 mV. The output can
drive a small resistive load: it can source currents of up to
400
A, and sink up to 10 mA. The output is stable with any
capacitive load, though settling time may be impaired. The low
frequency incremental output impedance is approximately 0.2
.
In addition to its use as an RF power measurement device (that
is, as a logarithmic amplifier) the AD8313 may also be used in
controller applications, by breaking the feedback path from
VOUT to the VSET (Pin 7), which determines the slope of the
output (nominally 18 mV/dB). This pin becomes the setpoint
input in controller modes. In this mode, the voltage V
OUT
re-
mains close to ground (typically under 50 mV) until the decibel
equivalent of the voltage V
SET
is reached at the input, when
V
OUT
makes a rapid transition to a voltage close to V
POS
(see
controller mode). The logarithmic intercept is nominally posi-
tioned at 100 dBm (re: 50
) and this is effective in both the
log amp mode and the controller mode.
Thus, with Pins 7 and 8 connected (log amp mode) we have:
V
OUT
= V
SLOPE
(P
IN
+ 100 dBm)
where P
IN
is the input power, stated in dBm when the source is
directly terminated in 50
. However, the input impedance of
the AD8313 is much higher than 50
and the sensitivity of this
device may be increased by about 12 dB by using some type of
matching network (see below), which adds a voltage gain and
lowers the intercept by the same amount. This dependence on
the choice of reference impedance can be avoided by restating
the expression as:
V
OUT
= 20
V
SLOPE
log (V
IN
/2.2
V)
where V
IN
is the rms value of a sinusoidal input appearing
across Pins 2 and 3; here, 2.2
V corresponds to the intercept,
expressed in voltage terms. (For a more thorough treatment of
the effect of signal waveform and metrics on the intercept posi-
tioning for a log amp, see the AD8307 data sheet).
AD8313
9
REV. B
With Pins 7 and 8 disconnected (controller mode), the output
may be stated as
V
OUT
v V
S
when V
SLOPE
(P
IN
+ 100) > V
SET
V
OUT
v 0 when V
SLOPE
(P
IN
+ 100) < V
SET
when the input is stated in terms of the power of a sinusoidal
signal across a net termination impedance of 50
. The transi-
tion zone between high and low states is very narrow, since the
output stage behaves essentially as a fast integrator. The above
equations may be restated as
V
OUT
v V
S
when V
SLOPE
log (V
IN
/2.2
V) > V
SET
V
OUT
v 0 when V
SLOPE
log (V
IN
/2.2
V) < V
SET
A further use of the separate VOUT and VSET pins is in raising
the load-driving current capability by the inclusion of an ex-
ternal NPN emitter follower. More complete information about
usage in these various modes is provided in the Applications
section.
INTERFACES
This section describes the signal and control interfaces and their
behavior. On-chip resistances and capacitances exhibit varia-
tions of up to
20%. These resistances are sometimes tempera-
ture dependent and the capacitances may be voltage dependent.
Power-Down Interface, PWDN
The power-down threshold is accurately centered at the midpoint
of the supply as shown in Figure 22. If Pin 5 is left unconnected or
tied to the supply voltage (recommended) the bias enable cur-
rent is shut off, and the current drawn from the supply is pre-
dominately through a nominal 300 k
chain (20
A at 3 V). When
grounded, the bias system is turned on. The threshold level is
accurately at V
POS
/2. The input bias current at the PWDN pin
when operating in the device "ON" state is approximately
5
A for V
POS
= 3 V.
5
PWDN
VPOS
75k
6
COMM
150k
50k
150k
TO BIAS
ENABLE
4
Figure 22. Power-Down Threshold Circuitry
Signal Inputs, INHI, INLO
The simplest low frequency ac model for this interface consists
of just a 900
resistance R
IN
in shunt with a 1.1 pF input ca-
pacitance, C
IN
connected across INHI and INLO. Figure 23
shows these distributed in the context of a more complete sche-
matic. The input bias voltage shown is for the enabled chip;
when disabled, it will rise by a few hundred millivolts. If the
input is coupled via capacitors, this change may cause a low-
level signal transient to be introduced, having a time-constant
formed by these capacitors and R
IN
. For this reason, large-
valued coupling capacitors should be well matched; this is not
necessary when using the small capacitors found in many im-
pedance transforming networks used at high frequencies.
1.25k
COMM
VPOS
INHI
INLO
VPOS
0.5pF
0.5pF
0.7pF
2.5k
2.5k
~
0.75V
(1ST DETECTOR)
250
~
1.4mA
125
125
1.25k
1.24V
GAIN BIAS
TO 2ND
STAGE
TO STAGES
1 THRU 4
1
2
3
4
Figure 23. Input Interface Simplified Schematic
For high frequency use, Figure 24 shows the input impedance
plotted on a Smith chart. This measured result of a typical de-
vice includes a 191 mil 50
trace and a 680 pF capacitor to
ground from the INLO pin.
1.1pF
900
1.9GHz
Frequency
100MHz
900MHz
1.9GHz
2.5GHz
R
650
55
22
23
+j X
j 400
j 135
j 65
j 43
AD8313 MEASURED
2.5GHz
900MHz
100MHz
Figure 24. Typical Input Impedance
Logarithmic/Error Output, VOUT
The rail-to-rail output interface is shown in Figure 25. V
OUT
can run from within about 50 mV of ground, to within about
100 mV of the supply voltage, and is short-circuit safe to either
supply. However, the sourcing load current I
SOURCE
is limited by
that provided by the PNP transistor, to typically 400
A. Larger
load currents can be provided by adding an external NPN tran-
sistor (see Applications). The dc open-loop gain of this amplifier
is high, and it may be regarded essentially as an integrator hav-
ing a capacitance of 2 pF (C
INT
) driven by the current-mode
signals generated by the summed outputs of the nine detector
stages, which is scaled approximately 4.0
A/dB.
COMM
g
m
STAGE
C
INT
LP
LM
10mA
MAX
VOUT
C
L
BIAS
I
SOURCE
400 A
VPOS
FROM
SET-POINT
SUMMED
DETECTOR
OUTPUTS
6
8
1
Figure 25. Output Interface Circuitry
Thus, for a midscale RF input of about 3 mV, which is some
40 dB above the minimum detector output, this current is
160
A and the output changes by 8 V/
s. When VOUT is
connected to VSET, the rise and fall times are approximately
40 ns (for R
L
10 k
). The nominal slew rate is
2.5 V/
s.
The HF compensation technique results in stable operation with
a large capacitive load, C
L
, though the positive-going slew rate
will then be limited by I
SOURCE
/C
L
to 1 V/
s for C
L
= 400 pF.
AD8313
10
REV. B
Setpoint Interface, VSET
The setpoint interface is shown in Figure 26. The voltage V
SET
is divided by a factor of three in a resistive attenuator of total
resistance 18 k
. The signal is converted to a current by the
action of the op amp and the resistor R3 (1.5 k
), which bal-
ances the current generated by the summed output of the nine
detector cells at the input to the previous cell. The logarithmic
slope is nominally 3
4.0
A/dB
1.5 k
18 mV/dB.
VSET
VPOS
R1
12k
COMM
FDBK
TO O/P
STAGE
1
R2
6k
R3
1.5k
25 A
25 A
8
6
LP
Figure 26. Setpoint Interface Circuitry
APPLICATIONS
Basic Connections for Log (RSSI) Mode
Figure 27 shows the AD8313 connected in its basic measure-
ment mode. A power supply of +2.7 V to +5.5 V is required.
The power supply to each of the VPOS pins should be decoupled
with a 0.1
F, surface mount ceramic capacitor and a series
resistor of 10
.
The PWDN pin is shown as grounded. The AD8313 may be
disabled by a logic "HI" at this pin. When disabled, the chip
current is reduced to about 20
A from its normal value of
13.7 mA. The logic threshold is at V
POS
/2 and the enable func-
tion occurs in about 1.8
s; note, however, that further settling
time is generally needed at low input levels. While the input in
this case is terminated with a simple 50
broadband resistive
match, there are a wide variety of ways in which the input termi-
nation can be accomplished. These are discussed in the Input
Coupling section.
VSET is connected to VOUT to establish a feedback path that
controls the overall scaling of the logarithmic amplifier. The
load resistance, R
L
, should not be lower than 5 k
in order that
the full-scale output of 1.75 V can be generated with the limited
available current of 400
A max.
As stated in the Absolute Maximum Ratings, an externally ap-
plied overvoltage on the VOUT pin that is outside the range 0 V
to V
POS
is sufficient to cause permanent damage to the device. If
overvoltages are expected on the VOUT pin, a series resistor
(R
PROT
) should be included as shown. A 500
resistor is suffi-
cient to protect against overvoltage up to
5 V; 1000
should
be used if an overvoltage of up to
15 V is expected. Since the
output stage is meant to drive loads of no more than 400
A,
this resistor will not impact device performance for more high
impedance drive applications (higher output current applications
are discussed in the Increasing Output Current section).
R2
10
R
L
= 1M
0.1 F
53.6
680pF
680pF
R1
10
0.1 F
+V
S
+V
S
8
7
6
5
1
2
3
4
VPOS
VOUT
INHI
INLO
VPOS PWDN
COMM
VSET
AD8313
R
PROT
Figure 27. Basic Connections for Log (RSSI) Mode
Operating in the Controller Mode
Figure 28 shows the basic connections for operation in control-
ler mode. The link between VOUT and VSET is broken and a
"setpoint" is applied to VSET. Any difference between V
SET
and the equivalent input power to the AD8313, will drive V
OUT
either to the supply rail or close to ground. If V
SET
is greater
than the equivalent input power, V
OUT
will be driven towards
ground and vice versa.
V
SETPOINT
INPUT
CONTROLLER
OUTPUT
R3
10
0.1 F
R1
10
0.1 F
+V
S
+V
S
8
7
6
5
1
2
3
4
VPOS
VOUT
INHI
INLO
VPOS PWDN
COMM
VSET
AD8313
R
PROT
Figure 28. Basic Connections for Operation in the
Controller Mode
This mode of operation is useful in applications where the out-
put power of an RF power amplifier (PA) is to be controlled by
an analog AGC loop (Figure 29). In this mode, a setpoint
voltage, proportional in dB to the desired output power, is ap-
plied to the VSET pin. A sample of the output power from the
PA, via a directional coupler or other means, is fed to the input
of the AD8313.
SETPOINT
CONTROL DAC
RFIN
VOUT
VSET
AD8313
DIRECTIONAL
COUPLER
POWER
AMPLIFIER
RF IN
ENVELOPE OF
TRANSMITTED
SIGNAL
Figure 29. Setpoint Controller Operation
V
OUT
is applied to the gain control terminal of the power ampli-
fier. The gain control transfer function of the power amplifier
should be an inverse relationship, i.e., increasing voltage de-
creases gain.
AD8313
11
REV. B
A positive input step on V
SET
(indicating a demand for in-
creased power from the PA) will drive V
OUT
towards ground.
This should be arranged to increase the gain of the PA. The
loop will settle when V
OUT
settles to a voltage that sets the input
power to the AD8313 to the dB equivalent of V
SET
.
Input Coupling
The signal may be coupled to the AD8313 in a variety of ways.
In all cases, there must not be a dc path from the input pins to
ground. Some of the possibilities include: dual input coupling
capacitors, a flux-linked transformer, a printed-circuit balun,
direct drive from a directional coupler, or a narrow-band imped-
ance matching network.
Figure 30 shows a simple broadband resistive match. A termina-
tion resistor of 53.6
combines with the internal input imped-
ance of the AD8313 to give an overall resistive input impedance
of approximately 50
. The termination resistor should prefer-
ably be placed directly across the input pins, INHI to INLO,
where it serves to lower the possible deleterious effects of dc
offset voltages on the low end of the dynamic range. At low
frequencies, this may not be quite as attractive, since it necessi-
tates the use of larger coupling capacitors. The two 680 pF
input coupling capacitors set the high-pass corner frequency of
the network at 9.4 MHz.
R
MATCH
53.6
C1
680pF
C2
680pF
C
IN
R
IN
AD8313
50
50
SOURCE
Figure 30. A Simple Broadband Resistive Input Termination
The high pass corner frequency can be set higher according to
the equation:
f
C
dB
3
1
2
50
=
where:
C
C
C
C
C
=
+
1
2
1
2
In high frequency applications, the use of a transformer, balun
or matching network is advantageous. The impedance match-
ing characteristics of these networks provide what is essentially a
gain stage before the AD8313 that increases the device sensitiv-
ity. This gain effect is further explored in the following match-
ing example.
Figures 31 and 32 show device performance under these three
input conditions at 900 MHz and 1900 MHz.
While the 900 MHz case clearly shows the effect of input
matching by realigning the intercept as expected, little improve-
ment is seen at 1.9 GHz. Clearly, if no improvement in sensitiv-
ity is required, a simple 50
termination may be the best choice
for a given design based on ease of use and cost of components.
INPUT AMPLITUDE dBm
80
70
60
50
40
30
20
10
3
2
1
0
1
2
3
ERROR dB
TERMINATED
DR = 66dB
90
10
0
BALANCED
MATCHED
BALANCED
DR = 71dB
MATCHED
DR = 69dB
Figure 31. Comparison of Terminated, Matched and
Balanced Input Drive at 900 MHz
INPUT AMPLITUDE dBm
80
70
60
50
40
30
20
10
0
3
2
1
0
1
2
3
ERROR dB
90
10
TERMINATED
DR = 75dB
BALANCED
BALANCED
DR = 75dB
MATCHED
DR = 73dB
MATCHED
TERMINATED
Figure 32. Comparison of Terminated, Matched and
Balanced Input Drive at 1900 MHz
A Narrow-Band LC Matching Example at 100 MHz
While numerous software programs are available that allow the
values of matching components to be easily calculated, a clear
understanding of the calculations involved is valuable. A low
frequency (100 MHz) value has been used for this exercise
because of the deleterious board effects at higher frequencies.
RF layout simulation software is useful when board design at
higher frequencies is required.
A narrow-band LC match can be implemented either as a
series-inductance/shunt-capacitance or as a series-capacitance/
shunt-inductance. However, the concurrent requirement that the
AD8313 inputs, INHI and INLO, be ac-coupled, makes a
series-capacitance/shunt-inductance type match more appropri-
ate (see Figure 33).
L
MATCH
C1
C2
C
IN
R
IN
AD8313
50
50
SOURCE
Figure 33. Narrow-Band Reactive Match
AD8313
12
REV. B
Typically, the AD8313 will need to be matched to 50
. The
input impedance of the AD8313 at 100 MHz can be read from
the Smith Chart (Figure 24) and corresponds to a resistive input
impedance of 900
in parallel with a capacitance of 1.1 pF.
To make the matching process simpler, the input capacitance of
the AD8313, C
IN
, can be temporarily removed from the calcula-
tion by adding a virtual shunt inductor (L
2
), which will resonate
away C
IN
(Figure 34). This inductor will be factored back into
the calculation later. This allows the main calculation to be
based on a simple resistive-to-resistive match (i.e., 50
to
900
).
The resonant frequency is defined by the equation
=
1
2
L C
IN
therefore: L
2
=
1
2
C
IN
= 2.3
H
C
MATCH
=
(C1
C2)
(C1 +
C2)
L
MATCH
=
(L
1
L
2
)
(L
1
+
L
2
)
C1
C2
C
IN
R
IN
AD8313
50
50
SOURCE
L
1
L
2
TEMPORARY
INDUCTANCE
Figure 34. Input Matching Example
With C
IN
and L
2
temporarily out of the picture, the focus is now
on matching a 50
source resistance to a (purely resistive) load
of 900
and calculating values for C
MATCH
and L
1
.
When
R R
L
C
S
IN
MATCH
=
1
the input will look purely resistive at a frequency given by
f
L C
O
MATCH
=
1
2
1
= 100 MHz
Solving for C
MATCH
gives
C
R R
f
pF
MATCH
S
IN
O
=
=
1
1
2
7 5
.
Solving for L
1
gives
L
R R
f
S
IN
O
1
2
=
= 337.6 nH
Because L
1
and L
2
are in parallel, they can be combined to give
the final value for L
MATCH
(i.e.)
L
L L
L
L
MATCH
=
+
1
2
1
2
= 294 nH
C1 and C2 can be chosen in a number of ways. First C2 can be
set to a large value such as 1000 pF, so that it appears as an RF
short. C1 would then be set equal to the calculated value of
C
MATCH
. Alternatively, C1 and C2 can each be set to twice
C
MATCH
so that the total series capacitance is equal to C
MATCH
.
By making C1 and C2 slightly unequal (i.e., select C2 to be
about 10% less than C1) but keeping their series value the
same, the amplitude of the signals on INHI and INLO can be
equalized so that the AD8313 is driven in a more balanced
manner. Any one of the three options detailed above can be
used as long as the combined series value of C1 and C2 (i.e.,
C1
C2/(C1 + C2)) is equal to C
MATCH
.
In all cases, the values of C
MATCH
and L
MATCH
must be chosen
from standard values. At this point, these values need now be
installed on the board and measured for performance at 100 MHz.
Because of board and layout parasitics, the component values
from the above example had to be tuned to the final values of
C
MATCH
= 8.9 pF and L
MATCH
= 270 nH shown in Table I.
Assuming a lossless matching network and noting conservation
of power, the impedance transformation from R
S
to R
IN
(50
to 900
) has an associated voltage gain given by
Gain
R
R
dB
IN
S
=
20 log
= 12.6 dB
Because the AD8313 input responds to voltage and not true
power, the voltage gain of the matching network will increase
the effective input low-end power sensitivity by this amount.
Thus, in this case, the dynamic range will be shifted down-
wards, that is, the 12.6 dB voltage gain will shift the 0 dBm to
65 dBm input range downwards to 12.6 dBm to 77.6 dBm.
However, because of network losses this gain will not be fully
realized in practice. Reference Figures 31 and 32 for an example
of practical attainable voltage gains.
Table I shows recommended values for the inductor and capaci-
tors in Figure 32 for some selected RF frequencies along with the
associated theoretical voltage gain. These values for a reactive
match are optimal for the board layout detailed as Figure 45.
As previously discussed, a modification of the board layout will
produce networks that may not perform as specified. At 2.5 GHz, a
shunt inductor is sufficient to achieve match. Consequently, C1
and C2 are set sufficiently high that they appear as RF shorts.
Table I. Recommended Values for C1, C2 and L
MATCH
in
Figure 33
F
req.
C
MATCH
C1
C2
L
MATCH
Voltage
(MHz)
(pF)
(pF)
(pF)
(nH)
Gain (dB)
100
8.9
22
15
270
12.6
9
1000
270
900
1.5
3
3
8.2
9.0
1.5
1000
8.2
1900
1.5
3
3
2.2
6.2
1.5
1000
2.2
2500
Large
390
390
2.2
3.2
Figure 35 shows the voltage response of the 100 MHz matching
network; note the high attenuation at lower frequencies typical
of a high-pass network.
AD8313
13
REV. B
FREQUENCY MHz
15
50
VOLTAGE GAIN dB
10
5
0
5
100
200
Figure 35. Voltage Response of 100 MHz Narrow-Band
Matching Network
Adjusting the Log Slope
Figure 36 shows how the log slope may be adjusted to an exact
value. The idea is simple: the output at pin VOUT is attenuated
by the variable resistor R2 working against the internal 18 k
of input resistance at the VSET pin. When R2 is zero, the
attenuation it introduces is zero, and thus the slope is the basic
18 mV/dB (note that this value varies with frequency, see
Figure 8). When R2 is set to its maximum value of 10 k
, the
attenuation from VOUT to VSET is the ratio 18/(18+10), and
the slope is raised to (28/18)
18 mV, or 28 mV/dB. At about
the midpoint, the nominal scale will be 23 mV/dB. Thus, a
70 dB input range will change the output by 70
23 mV, or
1.6 V.
18-30mV/dB
R2
10k
R3
10
0.1 F
R1
10
0.1 F
+V
S
+V
S
8
7
6
5
1
2
3
4
VPOS
VOUT
INHI
INLO
VPOS PWDN
COMM
VSET
AD8313
Figure 36. Adjusting the Log Slope
As already stated, the unadjusted log slope varies with frequency
from 17 mV/dB to 20 mV/dB, as shown in Figure 8. By placing
a resistor between VOUT and VSET, the slope can be adjusted
to a convenient 20 mV/dB as shown in Figure 37. Table II
shows the recommended values for this resistor R
EXT
. Also
shown are values for R
EXT
that increase the slope to approxi-
mately 50 mV/dB. The corresponding voltage swings for a
65 dBm to 0 dBm input range are also shown in Table II.
20mV/dB
R
EXT
R3
10
0.1 F
R1
10
0.1 F
+V
S
+V
S
8
7
6
5
1
2
3
4
VPOS
VOUT
INHI
INLO
VPOS PWDN
COMM
VSET
AD8313
Figure 37. Adjusting the Log Slope to a Fixed Value
Table II. Values for R
EXT
in Figure 37
Frequency
R
EXT
Slope
V
OUT
Swing for Pin
MHz
k
mV/dB
65 dBm to 0 dBm V
100
0.953
20
0.44 to 1.74
900
2.00
20
0.58 to 1.88
1900
2.55
20
0.70 to 2.00
2500
0
20
0.54 to 1.84
100
29.4
50
1.10 to 4.35
900
32.4
50.4
1.46 to 4.74
1900
33.2
49.8
1.74 to 4.98
2500
26.7
49.7
1.34 to 4.57
The value for R
EXT
is calculated using the equation:
R
New Slope
Original Slope
Original Slope
EXT
=
(
)
18 k
The value for the Original Slope, at a particular frequency, can
be read from Figure 8. The resulting output swing is calculated
by simply inserting the New Slope value and the intercept at that
frequency (Figures 8 and 11) into the general equation for the
AD8313's output voltage:
V
OUT
= Slope (P
IN
Intercept)
Increasing Output Current
Where it is necessary to drive a more substantial load, one of
two methods can be used. In Figure 38, a 1 k
pull-up resistor
is added at the output which provides the load current necessary
to drive a 1 k
load to +1.7 V for V
S
= 2.7 V. The pull-up resis-
tor will slightly lower the intercept and the slope. As a result, the
transfer function of the AD8313 will be shifted upwards (inter-
cept shifts downward).
R2
10
0.1 F
R1
10
0.1 F
+V
S
+V
S
1
2
3
4
VPOS
VOUT
INHI
INLO
VPOS PWDN
COMM
VSET
8
7
6
5
AD8313
R
L
= 1k
20mV/dB
1k
+V
S
Figure 38. Increasing AD8313 Output Current Capability
In Figure 39, an emitter-follower is used to provide current
gain, when a 100
load can readily be driven to full-scale out-
put. While a high
transistor such as the BC848BLT1 (min
=
200) is recommended, a 2 k
pull-up resistor between VOUT
and +V
S
can provide additional base current to the transistor.
R3
10
0.1 F
R1
10
0.1 F
+V
S
+V
S
8
7
6
5
1
2
3
4
VPOS
VOUT
INHI
INLO
VPOS PWDN
COMM
VSET
AD8313
OUTPUT
+V
S
13k
R
L
100
10k
BC848BLT1
MIN
= 200
Figure 39. Output Current Drive Boost Connection
AD8313
14
REV. B
In addition to providing current gain, the resistor/potentiometer
combination between VSET and the emitter of the transistor
increases the log slope to as much as 45 mV/dB, at maximum
resistance. This will give an output voltage of 4 V for a 0 dBm
input. If no increase in the log slope is required, VSET can be
connected directly to the emitter of the transistor.
Effect of Waveform Type On Intercept
Although it is specified for input levels in dBm (dB relative to
1 mW), the AD8313 fundamentally responds to voltage and not
to power. A direct consequence of this characteristic is that
input signals of equal rms power but differing crest factors will
produce different results at the log amp's output.
The effect of different signal waveforms is to vary the effec-
tive value of the log amp's intercept upwards or downwards.
Graphically, this looks like a vertical shift in the log amp's trans-
fer function. The device's logarithmic slope, however, is in
principle not affected. For example, consider the case of the
AD8313 being alternately fed from a continuous wave and a
single CDMA channel of the same rms power. The AD8313's
output voltage will differ by the equivalent of 3.55 dB (64 mV)
over the complete dynamic range of the device (the output for a
CDMA input being lower).
Table III shows the correction factors that should be applied to
measure the rms signal strength of a various signal types. A
continuous wave input is used as a reference. To measure the
rms power of a square-wave, for example, the mV equivalent
of the dB value given in the table (18 mV/dB times 3.01 dB)
should be subtracted from the output voltage of the AD8313.
Table III. Shift in AD8313 Output for Signals with Differing
Crest Factors
Correction Factor
Signal Type
(Add to Output Reading)
CW Sine Wave
0 dB
Square Wave or DC
3.01 dB
Triangular Wave
+0.9 dB
GSM Channel (All Time Slots On)
+0.55 dB
CDMA Channel
+3.55 dB
PDC Channel (All Time Slots On)
+0.58 dB
Gaussian Noise
+2.51 dB
EVALUATION BOARD
Schematic and Layout
Figure 44 shows the schematic of the evaluation board that was
used to characterize the AD8313. Note that uninstalled compo-
nents are drawn in as dashed.
This is a 3-layer board (signal, ground and power), with a Duroid
dielectric (RT 5880, h = 5 mil,
R
= 2.2). FR4 can also be used,
but microstrip dimensions must be recalculated because of the
different dielectric constant and board height. The trace layout
and silkscreen of the signal and power layers are shown in Fig-
ures 40 to 43. A detail of the PCB footprint for the
SOIC
package and the pads for the matching components are shown
in Figure 45.
The vacant portions of the signal and power layers are filled out
with ground plane for general noise suppression. To ensure a
low impedance connection between the planes, there are mul-
tiple through-hole connections to the RF ground plane. While
the ground planes on the power and signal planes are used as
general purpose ground returns, any RF grounds related to the
input matching network (e.g., C2) are returned directly to the
RF internal ground plane.
General Operation
The board should be powered by a single supply in the range,
+2.7 V to +5.5 V. The power supply to each of the VPOS pins
is decoupled by a 10
resistor and a 0.1
F capacitor.
The two signal inputs are ac-coupled using 680 pF high quality
RF capacitors (C1, C2). A 53.6
resistor across the differential
signal inputs (INHI, INLO) combines with the internal 900
input impedance to give a broadband input impedance of 50.6
.
This termination is not optimal from a noise perspective due to
the Johnson noise of the 53.6
resistor. Neither does it take
account for the AD8313's reactive input impedance or of the
decrease over frequency of the resistive component of the input
impedance. However, it does allow evaluation of the AD8313
over its complete frequency range without having to design
multiple matching networks.
For optimum performance, a narrowband match can be imple-
mented by replacing the 53.6
resistor (labeled L/R) with an
RF inductor and replacing the 680 pF capacitors with appropri-
ate values. The section on Input Matching includes a table of
recommended values for selected frequencies and explains the
method of calculation.
Switch 1 is used to select between power-up and power-down
modes. Connecting the PWDN pin to ground enables normal
operation of the AD8313. In the opposite position, the PWDN
pin can either be driven externally (SMA connector labeled
EXT ENABLE) to either device state or allowed to float to a
disabled device state.
The evaluation board ships with the AD8313 configured to
operate in RSSI measurement mode, the logarithmic output
appearing on the SMA connector labeled VOUT. This mode is
set by the 0
resistor (R11), which shorts the VOUT and
VSET pins to each other.
Varying the Logarithmic Slope
The slope of the AD8313 can be increased from its nominal
value of 18 mV/dB to a maximum of 40 mV/dB by removing
R11, the 0
resistor, which shorts VSET to VOUT. VSET and
VOUT are now connected through a 20 k
potentiometer.
Operating in Controller Mode
To put the AD8313 into controller mode, R7 and R11 should
be removed, breaking the link between VOUT and VSET. The
VSET pin can then be driven externally via the SMA connector
labeled EXT VSET IN ADJ.
Increasing Output Current
To increase the output current of V
OUT
, set both R3 and R11 to
0
and install potentiometer R4 (1 k
to 5 k
).
AD8313
15
REV. B
Figure 40. Layout of Signal Layer
Figure 41. Layout of Power Layer
Figure 42. Signal Layer Silkscreen
Figure 43. Power Layer Silkscreen
AD8313
16
REV. B
C3390b08/99
PRINTED IN U.S.A.
8-Lead SOIC Package
(RM-08)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33
27
0.120 (3.05)
0.112 (2.84)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C2
680pF
C1
680pF
R2
10
C3
0.1 F
R1
10
+V
S
+V
S
1
2
3
4
VPOS
VOUT
INHI
INLO
VPOS PWDN
COMM
VSET
AD8313
8
7
6
5
L/R
53.6
C4
0.1 F
SIG IN
R11
0
R7
0
R8
20k
R3
R4
+V
S
R5
0
R6
C6
VOUT
EXT VSET
EXT ENABLE
SW1
Figure 44. Evaluation Board Schematic
48
54.4
90.6
28
20
27.5
75
50
20
19
50
35
41
22
46
48
51.7
91.3
51
10
16
126
TRACE WIDTH
15.4
NOT CRITICAL DIMENSIONS
UNIT = MILS
Figure 45. Detail of PCB Footprint for Package and Pads for Matching Network
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