Document Outline
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- GENERAL DESCRIPTION
- TABLE OF CONTENTS
-
-
-
-
-
-
-
-
-
Active Receive Mixer
400 MHz to 1.2 GHz
AD8344
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
Broadband RF port: 400 MHz to 1.2 GHz
Conversion gain: 4.5 dB
Noise figure: 10.5 dB
Input IP3: 24 dBm
Input P1dB: 8.5 dBm
LO drive: 0 dBm
External control of mixer bias for low power operation
Single-ended, 50 RF and LO input ports
Single-supply operation: 5 V @ 84 mA
Power-down mode
Exposed paddle LFCSP: 3 mm 3 mm
APPLICATIONS
Cellular base station receivers
ISM receivers
Radio links
RF Instrumentation
FUNCTIONAL BLOCK DIAGRAM
VPLO
1
LOCM
2
LOIN
3
COMM
4
VPD
C
12
PW
D
N
11
EXR
B
10
COMM
9
COMM
8
IFOP
7
IFOM
6
COMM
5
COMM
13
RFCM
14
RFIN
15
VPMX
16
BIAS
04826-0-001
Figure 1.
GENERAL DESCRIPTION
The AD8344 is a high performance, broadband active mixer. It
is well suited for demanding receive-channel applications that
require wide bandwidth on all ports and very low intermodula-
tion distortion and noise figure.
The AD8344 provides a typical conversion gain of 4.5 dB at
890 MHz. The integrated LO driver supports a 50 input
impedance with a low LO drive level, helping to minimize
external component count.
The single-ended 50 broadband RF port allows for easy
interfacing to both active devices and passive filters. The RF
input accepts input signals as large as 1.7 V p-p or 8.5 dBm
(re: 50 ) at P1dB.
The open-collector differential outputs provide excellent
balance and can be used with a differential filter or IF amplifier,
such as the AD8369 or AD8351. These outputs may also be con-
verted to a single-ended signal through the use of a matching
network or a transformer (balun). When centered on the VPOS
supply voltage, each of the differential outputs may swing
2.5 V p-p.
The AD8344 is fabricated on an Analog Devices proprietary,
high performance SiGe IC process. The AD8344 is available
in a 16-lead LFCSP package. It operates over a -40C to +85C
temperature range. An evaluation board is also available.
AD8344
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
AC Performance ............................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Circuit Description......................................................................... 13
AC Interfaces................................................................................... 14
IF Port .......................................................................................... 14
LO Considerations ..................................................................... 15
Bias Resistor Selection ............................................................... 16
Conversion Gain and IF Loading............................................. 16
Low IF Frequency Operation.................................................... 17
Evaluation Board ............................................................................ 18
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
6/04--Revision 0: Initial Version
AD8344
Rev. 0 | Page 3 of 20
SPECIFICATIONS
V
S
= 5 V, T
A
= 25C, f
RF
= 890 MHz, f
LO
= 1090 MHz, LO power = 0 dBm, Z
O
= 50 , R
BIAS
= 2.43 k, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
RF INPUT INTERFACE
(Pin 15, RFIN and Pin 14, RFCM)
Return Loss
10
dB
DC Bias Level
Internally generated; port must be ac-coupled
2.6
V
OUTPUT INTERFACE
Output Impedance
Differential impedance, f = 200 MHz
9||1
k||pF
DC Bias Voltage
Externally generated
4.75
V
S
5.25
V
Power Range
Via a 4:1 balun
13
dBm
LO INTERFACE
LO Power
-10
0
+4
dBm
Return Loss
10
dB
DC Bias Voltage
Internally generated; port must be ac-coupled
V
S
- 1.6
V
POWER-DOWN INTERFACE
PWDN Threshold
V
S
- 1.4
V
PWDN Response Time
Device enabled, IF output to 90% of its final level
0.4
s
Device disabled, supply current < 5 mA
0.01
s
PWDN Input Bias Current
Device enabled
-80
A
Device disabled
100
A
POWER SUPPLY
Positive Supply Voltage
4.75
V
S
5.25
V
Quiescent Current
VPDC
Supply current for bias cells
5
mA
VPMX, IFOP, IFOM
Supply current for mixer, R
BIAS
= 2.43 k
44
mA
VPLO
Supply current for LO limiting amplifier
35
mA
Total Quiescent Current
73
84
95
mA
Power-Down Current
Device disabled
500
A
AD8344
Rev. 0 | Page 4 of 20
AC PERFORMANCE
V
S
= 5 V, T
A
= 25C, LO power = 0 dBm, Z
O
= 50 , R
BIAS
= 2.43 k, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
RF Frequency Range
400
1200
MHz
LO Frequency Range
High Side LO
470
1600
MHz
IF Frequency Range
70
400
MHz
Conversion Gain
f
RF
= 450 MHz, f
LO
= 550 MHz, f
IF
= 100 MHz
9.25
dB
f
RF
= 890 MHz, f
LO
= 1090 MHz, f
IF
= 200 MHz
4.5
dB
SSB Noise Figure
f
RF
= 450 MHz, f
LO
= 550 MHz, f
IF
= 100 MHz
7.75
dB
f
RF
= 890 MHz, f
LO
= 1090 MHz, f
IF
= 200 MHz
10.5
dB
Input Third-Order Intercept
f
RF1
= 450 MHz, f
RF2
= 451 MHz, f
LO
= 550 MHz,
f
IF
= 100 MHz, each RF tone = -10 dBm
14
dBm
f
RF1
= 890 MHz, f
RF2
= 891 MHz, f
LO
= 1090 MHz,
f
IF
= 200 MHz, each RF tone = -10 dBm
24
dBm
Input Second-Order Intercept
f
RF1
= 450 MHz, f
RF2
= 500 MHz, f
LO
= 550 MHz, f
IF
= 100 MHz
36
dBm
f
RF1
= 890 MHz, f
RF2
= 940 MHz, f
LO
= 1090 MHz, f
IF
= 200 MHz
51
dBm
Input 1 dB Compression Point
f
RF
= 450 MHz, f
LO
= 550 MHz, f
IF
= 100 MHz
2.5
dBm
f
RF
= 890 MHz, f
LO
= 1090 MHz, f
IF
= 200 MHz
8.5
dBm
LO to IF Output Feedthrough
LO Power = 0 dBm, f
RF
= 890 MHz, f
LO
= 1090 MHz
-23
dBc
LO to RF Input Leakage
LO Power = 0 dBm, f
RF
= 890 MHz, f
LO
= 1090 MHz
-48
dBc
RF to IF Output Feedthrough
RF Power = -10 dBm, f
RF
= 890 MHz, f
LO
= 1090 MHz
-32
dBc
IF/2 Spurious
RF Power = -10 dBm, f
RF
= 890 MHz, f
LO
= 1090 MHz
-66
dBm
AD8344
Rev. 0 | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage, V
S
5.5 V
RF Input Level
12 dBm
LO Input Level
12 dBm
PWDN Pin
V
S
+ 0.5 V
IFOP, IFOM Bias Voltage
5.5 V
Minimum Resistor from EXRB to COMM
2.4 k
Internal Power Dissipation
580 mW
JA
77C/W
Maximum Junction Temperature
125C
Operating Temperature Range
-40C to +85C
Storage Temperature Range
-65C to +150C
Lead Temperature Range (Soldering 60 sec)
300C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only; functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8344
Rev. 0 | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPLO
1
LOCM
2
LOIN
3
COMM
4
VPD
C
12
PW
D
N
11
EXR
B
10
COMM
9
COMM
8
IFOP
7
IFOM
6
COMM
5
COMM
13
RFCM
14
RFIN
15
VPMX
16
04826-0-002
Figure 2. 16-Lead LFCSP
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Function
1
VPLO
Positive Supply Voltage for the LO Buffer: 4.75 V to 5.25 V.
2
LOCM
AC Ground for Limiting LO Amplifier, AC-Coupled to Ground.
3
LOIN
LO Input. Nominal input level 0 dBm, input level range -10 dBm to +4 dBm, re: 50 , ac-coupled.
4, 5, 8, 9, 13
COMM
Device Common (DC Ground).
6, 7
IFOM, IFOP
Differential IF Outputs; Open Collectors, Each Requires DC Bias of 5.00 V (Nominal).
10 EXRB
Mixer Bias Voltage, Connect Resistor from EXRB to Ground, Typical Value of 2.43 k
Sets Mixer Current to Nominal Value. Minimum resistor value from EXRB to ground = 2.4 k.
11
PWDN
Connect to Ground for Normal Operation. Connect pin to V
S
for disable mode.
12
VPDC
Positive Supply Voltage for the DC Bias Cell: 4.75 V to 5.25 V.
14
RFCM
AC Ground for RF Input, AC-Coupled to Ground.
15
RFIN
RF Input. Must be ac-coupled.
16
VPMX
Positive Supply Voltage for the Mixer: 4.75 V to 5.25 V.
AD8344
Rev. 0 | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
12
2
0
2
4
6
8
10
400
500
600
700
800
900
1000
1100
1200
04826-0-010
RF FREQUENCY (MHz)
GAIN (
d
B)
IF = 100MHz
IF = 200MHz
IF = 400MHz
IF = 70MHz
Figure 3. Conversion Gain vs. RF Frequency
6.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
10 9 8 7 6 5 4 3 2 1
0
1
2
3
4
04826-0-022
LO LEVEL (dBm)
GAIN (
d
B)
Figure 4. Conversion Gain vs. LO Power, F
RF
= 890 MHz, F
IF
= 200 MHz
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
40
80
70
60
50
40
30
20
10
0
10
20
30
04826-0-018
TEMPERATURE (
C)
GAIN (
d
B)
V
S
= 4.75V
V
S
= 5.0V
V
S
= 5.25V
Figure 5. Conversion Gain vs. Temperature, F
RF
= 890 MHz, F
LO
= 1090 MHz
10
0
1
2
3
4
5
6
7
8
9
80
120
160
200
240
280
320
360
400
04826-0-011
IF FREQUENCY (MHz)
GAIN (
d
B)
RF = 450MHz
RF = 890MHz
Figure 6. Conversion Gain vs. IF Frequency
45
0
5
10
15
20
25
35
40
30
3.6
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
04826-0-031
GAIN (dB)
P
E
RCE
NTAGE
GAIN PERCENTAGE
NORMAL (MEAN = 4.47,
STD DEV = 0.18)
Figure 7. Conversion Gain Distribution, F
RF
= 890 MHz, F
IF
= 200 MHz
AD8344
Rev. 0 | Page 8 of 20
28
26
24
22
20
18
16
14
12
10
400
500
600
700
800
900
1000
1100
1200
04826-0-012
RF FREQUENCY (MHz)
INPUT IP3 (
d
Bm)
IF = 100MHz
IF = 200MHz
IF = 400MHz
IF = 70MHz
Figure 8. Input IP3 vs. RF Frequency (RF Tone Spacing = 1 MHz)
25.0
20.0
20.5
21.0
21.5
22.0
22.5
23.0
23.5
24.0
24.5
10 9 8 7 6 5 4 3 2 1
0
1
2
3
4
04826-0-023
LO LEVEL (dBm)
INPUT IP3 (
d
Bm)
Figure 9. Input IP3 vs. LO Power,
F
RF1
= 890 MHz, F
RF2
= 891 MHz, F
LO
= 1090 MHz
30
29
28
27
26
25
24
23
22
21
20
40
80
70
60
50
40
30
20
10
0
10
20
30
04826-0-019
TEMPERATURE (
C)
INPUT IP3 (
d
Bm)
V
S
= 4.75V
V
S
= 5.0V
V
S
= 5.25V
Figure 10. Input IP3 vs. Temperature,
F
RF1
= 890 MHz, F
RF2
= 891 MHz, F
LO
= 1090 MHz
30
10
12
14
16
18
20
22
24
26
28
80
120
160
200
240
280
320
360
400
04826-0-013
IF FREQUENCY (MHz)
INPUT IP3 (
d
Bm)
RF = 890MHz
RF = 450MHz
Figure 11. Input IP3 vs. IF Frequency (RF Tone Spacing = 1 MHz)
35
0
5
10
15
20
25
30
23.0 23.2 23.4 23.6 23.8 24.0 24.2 24.4 24.6
25.0
24.8
04826-0-032
INPUT IP3 (dBm)
P
E
RCE
NTAGE
IP3 PERCENTAGE
NORMAL (MEAN = 24.023,
STD DEV = 0.24)
Figure 12. Input IP3 Distribution,
F
RF1
= 890 MHz, F
RF2
= 891 MHz, F
LO
= 1090 MHz
AD8344
Rev. 0 | Page 9 of 20
50
48
46
44
42
40
38
36
34
32
30
400
500
600
700
800
900
1000
1100
1200
04826-0-033
RF FREQUENCY (MHz)
INPUT IP2 (
d
Bm)
IF = 200
IF = 100
IF = 400
IF = 70
Figure 13. Input IP2 vs. RF Frequency (RF Tone Spacing = 50 MHz)
60
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
10 9 8 7 6 5 4 3 2 1
0
1
2
3
4
04826-0-034
LO LEVEL (dBm)
INPUT IP2 (
d
Bm)
Figure 14. Input IP2 vs. LO Power,
F
RF
= 890 MHz, F
LO
= 1090 MHz (RF Tone Spacing = 50 MHz)
40
42
44
46
48
50
52
54
40 30 20 10
0
10
20
30
40
50
60
70
80
04826-0-037
TEMPERATURE (
C)
INPUT IP2 (
d
Bm)
4.75V
5.0V
5.25V
Figure 15. Input IP2 vs. Temperature, F
RF
= 890 MHz,
F
LO
= 1090 MHz (RF Tone Spacing = 50 MHz)
50
52
54
56
58
60
30
32
34
36
38
40
42
44
46
48
80
120
160
200
240
280
320
360
400
04826-0-015
IF FREQUENCY (MHz)
INPUT IP2 (
d
Bm)
RF = 450MHz
RF = 890MHz
Figure 16. Input IP2 vs. IF Frequency (RF Tone Spacing = 50 MHz)
35
0
5
10
15
20
25
30
44
45
46
47
48
49
50
51
52
55
54
53
04826-0-035
INPUT IP2 (dBm)
P
E
RCE
NTAGE
IIP2 PERCENTAGE
NORMAL (MEAN = 48.96,
STD DEV = 01.17)
Figure 17. Input IP2 Distribution, F
RF
= 890 MHz,
F
LO
= 1090 MHz (RF Tone Spacing = 50 MHz)
AD8344
Rev. 0 | Page 10 of 20
12
0
2
4
6
8
10
400
500
600
700
800
900
1000
1100
1200
04826-0-016
RF FREQUENCY (MHz)
IN
PU
T P1dB
(
d
B
m
)
IF = 100MHz
IF = 200MHz
IF = 400MHz
IF = 70MHz
Figure 18. Input P1dB vs. RF Frequency
9.0
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
10 9 8 7 6 5 4 3 2 1
0
1
2
3
4
04826-0-024
LO LEVEL (dBm)
IN
PU
T P1dB
(
d
B
m
)
Figure 19. Input P1dB vs. LO Power, F
RF
= 890 MHz, F
LO
= 1090 MHz
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
40
80
70
60
50
40
30
20
10
0
10
20
30
04826-0-020
TEMPERATURE (
C)
IN
PU
T P1dB
(
d
B
m
)
V
S
= 4.75V
V
S
= 5.0V
V
S
= 5.25V
Figure 20. Input P1dB vs. Temperature, F
RF
= 890 MHz, F
LO
= 1090 MHz
10
9
8
7
6
5
4
3
2
1
0
80
120
160
200
240
280
320
360
400
04826-0-017
IF FREQUENCY (MHz)
IN
PU
T P1dB
(
d
B
m
)
RF = 450MHz
RF = 890MHz
Figure 21. Input P1dB vs. IF Frequency
60
55
50
45
40
35
30
25
20
15
10
5
0
7.0
7.5
8.0
8.5
9.0
9.5
10.0
04826-0-036
INPUT P1dB (dBm)
P
E
RCE
NTAGE
INPUT P1dB PERCENTAGE
NORMAL (MEAN = 8.50,
STD DEV = 0.38)
Figure 22. Input P1dB Distribution, F
RF
= 890 MHz, F
LO
= 1090 MHz
AD8344
Rev. 0 | Page 11 of 20
25
20
15
10
5
0
100
95
90
85
80
75
70
65
60
55
50
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
04826-0-026
R
BIAS
(k
)
NF AND IP
3
(dBm)
S
U
P
P
L
Y
CURRE
NT (mA)
NOISE FIGURE
INPUT IP3
CURRENT
Figure 23. Noise Figure, Input IP3 and Supply Current vs. R
BIAS
, F
RF1
= 890 MHz,
F
RF2
= 891 MHz, F
LO
= 1090 MHz
14
13
12
11
10
9
8
7
6
400
500
600
700
800
900
1000
1100
1200
04826-0-027
RF FREQUENCY (MHz)
NOIS
E
FIGURE
S
S
B
(dBm)
IF = 70
IF = 100
IF = 200
IF = 400
Figure 24. Noise Figure vs. RF Frequency
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
15
13
11
9
7
5
3
1
1
3
5
04826-0-029
LO POWER (dBm)
NOIS
E
FIGURE
S
S
B
(dBm)
Figure 25. Noise Figure vs. LO Power, F
RF
= 890 MHz, F
LO
= 1090 MHz
14
2
0
2
4
6
8
10
12
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
04826-0-025
R
BIAS
(k
)
IN
PU
T P1dB
(
d
B
m
)
Figure 26. Input P1dB vs. R
BIAS,
F
RF
= 890 MHz, F
LO
= 1090 MHz
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
70
100
150
200
250
300
350
400
04826-0-028
IF FREQUENCY (MHz)
NOIS
E
FIGURE
S
S
B
(dBm)
890MHz
450MHz
Figure 27. Noise Figure vs. IF Frequency
100
95
90
85
80
75
70
65
60
40
80
70
60
50
40
30
20
10
0
10
20
30
04826-0-021
TEMPERATURE (
C)
CURRE
NT (mA)
V
S
= 4.75V
V
S
= 5.0V
V
S
= 5.25V
Figure 28. Total Supply Current vs. Temperature
AD8344
Rev. 0 | Page 12 of 20
04826-0-051
0
180
30
330
60
90
270
300
120
240
150
210
1.2GHz
400MHz
Figure 29. RFIN Return Loss vs. RF Frequency
0
45
40
35
30
25
20
15
10
5
400
500
600
700
800
900
1000
1100
1200
04826-0-053
RF FREQUENCY (MHz)
FE
E
D
THROUGH (dBc
)
Figure 30. RF to IF Feedthrough vs. RF Frequency,
F
LO
= 1090 MHz, RF Power = -10 dBm
0
80
70
60
50
40
30
20
10
400
600
800
1000
1200
1400
1600
04826-0-055
LO FREQUENCY (MHz)
LE
AKAGE
(dBc
)
Figure 31. LO to RF Leakage vs. LO Frequency, LO Power = 0 dBm
04826-0-052
0
180
30
330
60
90
270
300
120
240
150
210
400MHz
1.6GHz
Figure 32. LOIN Return Loss vs. LO Frequency
0
40
35
30
25
20
15
10
5
400
600
800
1000
1200
1400
1600
04826-0-054
LO FREQUENCY (MHz)
FE
E
D
THROUGH (dBc
)
Figure 33. LO to IF Feedthrough vs. LO Frequency, LO Power = 0 dBm
14000
12000
10000
8000
6000
4000
2000
3.0
2.5
2.0
1.5
1.0
0.5
0
70
370
320
270
220
170
120
04826-0-030
FREQUENCY (MHz)
RE
S
I
S
T
ANCE
(
)
CAP
ACITANCE
(pF)
Figure 34. IF Port Output Resistance and Capacitance vs. IF Frequency
AD8344
Rev. 0 | Page 13 of 20
e
CIRCUIT DESCRIPTION
The AD8344 is a down converting mixer optimized for opera-
tion within the input frequency range of 400 MHz to 1.2 GHz. It
has a single-ended, 50 RF input, as well as a single-ended,
50 local oscillator (LO) input. The IF outputs are differential
open collectors. The mixer current can be adjusted by the value
of an external resistor to optimize performance for gain com-
pression and intermodulation or for low power operation.
Figure 35 shows the basic blocks of the mixer, which includes
the LO buffer, RF voltage-to-current converter, bias cell, and
mixing core.
The RF voltage to RF current conversion is done via an
inductively degenerated differential pair. When one side of the
differential pair is ac grounded, the other input can be driven
single-ended. The RF inputs can also be driven differentially.
The voltage-to-current converter then drives the emitters of a
four-transistor switching core. This switching core is driven by
an amplified version of the local oscillator signal connected to
the LO input. There are three limiting gain stages between the
external LO signal and the switching core. The first stage con-
verts the single-ended LO drive to a well balanced differential
drive. The differential drive then passes through two more gain
stages, which ensures a limited signal drives the switching core.
This affords the user a lower LO drive requirement, while
maintaining excellent distortion and compression performance.
The output signal of these three LO gain stages drives the four
transistors within the mixer core to commutate at the rate of th
local oscillator frequency. The output of the mixer core is taken
directly from these open collectors. The open collector outputs
present a high impedance at the IF frequency. The conversion
gain of the mixer depends directly on the impedance presented
to these open collectors. In characterization, a 200 load was
presented to the part via a 4:1 impedance transformer.
The AD8344 also features a power-down function.
Application of a logic low at the PWDN pin allows normal
operation. A high logic level at the PWDN pin shuts down the
AD8344. Power consumption when the part is disabled is less
than 10 mW.
The bias for the mixer is set with an external resistor from the
EXRB pin to ground. The value of this resistor directly affects
the dynamic range of the mixer. The external resistor should not
be lower than 2.4 k. Permanent damage to the part will result
if values below 2.4 k are used.
04826-0-003
LO
INPUT
VPLO
IFOP
IFOM
RFIN
VPMX
RFCM
BIAS
EXTERNAL
BIAS
RESISTOR
VPDC
PWDN
SE
TO
DIFF
Figure 35. AD8344 Simplified Schematic
As shown in Figure 36, the IF output pins, IFOP and IFOM, are
directly connected to the open collectors of the NPN transistors
in the mixer core so the differential and single-ended imped-
ances looking into this port are relatively high, on the order of
several k. A connection between the supply voltage and these
output pins is required for proper mixer core operation.
04826-0-003
IFOP IFOM
LOIN
RFCM
RFIN
COMM
Figure 36. Mixer Core Simplified Schematic
The AD8344 has three pins for the supply voltage: VPDC,
VPMX, and VPLO. These pins are separated to minimize or
eliminate possible parasitic coupling paths within the AD8344
that could cause spurious signals or reduced interport isolation.
Consequently, each of these pins should be well bypassed and
decoupled as close to the AD8344 as possible.
AD8344
Rev. 0 | Page 14 of 20
AC INTERFACES
The AD8344 is a high-side downconverter. It is designed to
downconvert radio frequencies (RF) to lower intermediate
frequencies (IF) using a high-side local oscillator (LO). The LO
is injected into the mixer core at a frequency greater than the
desired input RF frequency. The difference between the LO and
RF frequencies, f
LO
- f
RF,
is the IF frequency, f
IF
. In addition to
the desired RF signal, an RF image will be downconverted to the
same IF frequency. The image frequency is at f
LO
+ f
IF
. The con-
version gain of the AD8344 decreases with increasing input
frequency. By choosing to use a high-side LO the image fre-
quency at f
LO
+ f
IF
is translated with less conversion gain than
the desired RF signal at f
LO
- f
IF
. Additionally, any wideband
noise present at the image frequency will be downconverted
with less conversion gain than would be the case if a low-side
LO was applied. In general, a high-side LO should be used with
the AD8344 to ensure optimal noise performance and image
rejection.
The AD8344 is designed to operate using RF frequencies in the
400 MHz to 1200 MHz frequency range, with high-side LO
injection within the 470 MHz to 1600 MHz range. It is essential
to ac-couple RF and LO ports to prevent dc offsets from skew-
ing the mixer core in an asymmetrical manner, potentially
degrading linear input swing and impacting distortion and
input compression characteristics.
The AD8344 RFIN port presents a 50 impedance relative to
RFCM. In order to ensure a good impedance match, the RFIN
ac-coupling capacitor should be large enough in value so that
the presented reactance is negligible at the intended RF fre-
quency. Additionally, the RFCM bypassing capacitor should be
sufficiently large to provide a low impedance return path to
board ground. Low inductance ceramic grade capacitors of no
more than 330 pF are sufficient for most applications.
Similarly the LOIN port provides a 50 load impedance with
common-mode decoupling on LOCM. Again, common grade
ceramic capacitors will provide sufficient signal coupling and
bypassing of the LO interface.
04826-0-040
0
180
30
330
10MHz
500MHz
60
90
270
300
120
240
150
210
Figure 37. IF Port Reflection Coefficient from 10 MHz to 500 MHz
IF PORT
The IF port uses an open collector differential output interface.
The NPN open collectors can be modeled as high impedance
current sources. The stray capacitance associated with the IC
package presents a slightly capacitive source impedance as in
Figure 37. In general, the IFOP and IFOM output ports can be
modeled as current sources with an impedance of ~10 k in
parallel with ~1 pF of shunt capacitance. Circuit board traces
connecting the IF outputs to the load should be narrow and
short to prevent excessive capacitive loading. In order to main-
tain the specified conversion gain of the mixer, the IF output
ports should be loaded into 200 . It is not necessary to attempt
to provide a conjugate match to the IF port output source
impedance. If the IF signal needs to be delivered to a remote
load, more than a few centimeters away, it may be necessary to
use an appropriate buffer amplifier to present a real 200 load-
ing impedance at the IF output interface. The buffer amplifier
should have the appropriate source impedance to match the
characteristic impedance of the selected transmission line. An
example is provided in Figure 38, where the AD8351 differential
amplifier is used to drive a pair of 75 transmission lines. The
gain of the buffer can be independently set by choosing an
appropriate gain resistor, R
G
.
04826-0-041
COMM
8
IFOP
7
IFOM
6
COMM
5
AD8344
AD8351
+
RFC
+V
S
RFC
Z
L
= 200
+V
S
+V
S
200
R
G
Z
L
Tx LINE Z
O
= 75
Tx LINE Z
O
= 75
Figure 38. AD8351 Used as Transmission Line Driver and Impedance Buffer
AD8344
Rev. 0 | Page 15 of 20
The high input impedance of the AD8351 allows for a shunt
differential termination to provide the desired 200 load to the
AD8344 IF output port.
It is necessary to bias the open collector outputs using one of
the schemes presented in Figure 39 and Figure 40. Figure 39
illustrates the application of a center-tapped impedance trans-
former. The turns ratio of the transformer should be selected to
provide the desired impedance transformation. In the case of a
50 load impedance, a 4-to-1 impedance ratio transformer
should be used to transform the 50 load into a 200
differential load at the IF output pins. Figure 40 illustrates a
differential IF interface where pull-up choke inductors are used
to bias the open-collector outputs. The shunting impedance of
the choke inductors used to couple dc current into the mixer
core should be large enough at the IF frequency of operation as
to not load down the output current before reaching the
intended load. Additionally, the dc current handling capability
of the selected choke inductors needs to be at least 45 mA. The
self resonant frequency of the selected choke should be higher
than the intended IF frequency. A variety of suitable choke
inductors are commercially available from manufacturers such
as Murata and Coilcraft. An impedance transforming network
may be required to transform the final load impedance to 200
at the IF outputs. There are several good reference books that
explain general impedance matching procedures, including:
Chris Bowick, RF Circuit Design, Newnes, Reprint Edition,
1997.
David M. Pozar, Microwave Engineering, Wiley Text Books,
Second Edition, 1997.
Guillermo Gonzalez, Microwave Transistor Amplifiers: Analy-
sis and Design, Prentice Hall, Second Edition, 1996.
04826-0-042
COMM
8
IFOP
7
IFOM
6
COMM
5
AD8344
Z
L
= 200
IF OUT
Z
O
= 50
+V
S
4:1
Figure 39. Biasing the IF Port Open Collector Outputs
Using a Center-Tapped Impedance Transformer
04826-0-043
COMM
8
IFOP
7
IFOM
6
COMM
5
AD8344
RFC
+V
S
RFC
Z
L
= 200
IF OUT+
IF OUT
+V
S
Z
L
IMPEDANCE
TRANSFORMING
NETWORK
Figure 40. Biasing the IF Port Open Collector Outputs
Using Pull-Up Choke Inductors
04826-0-044
0
180
30
330
50MHz
50MHz
500MHz
500MHz
60
90
270
300
120
240
150
210
REAL
CHOKES
IDEAL
CHOKES
Figure 41. IF Port Loading Effects due to Finite-Q Pull-Up Inductors
(Murata BLM18HD601SN1D Chokes)
LO CONSIDERATIONS
The LO signal needs to have adequate phase noise characteris-
tics and reasonable low second harmonic content to prevent
degradation of the noise figure performance of the AD8344. A
LO plagued with poor phase noise can result in reciprocal
mixing, a mechanism that causes spectral spreading of the
downconverted signal, limiting the sensitivity of the mixer at
frequencies close-in to any large input signals. The internal LO
buffer provides enough gain to hard limit the input LO and
provide fast switching of the mixer core. Odd harmonic content
present on the LO drive signal should not impact mixer
performance; however, even-order harmonics cause the mixer
core to commutate in an unbalanced manner, potentially
degrading noise performance. Simple lumped element low-pass
filtering can be applied to help reject the harmonic content of a
given local oscillator, as illustrated in Figure 42. The filter
depicted is a common 3-pole Chebyshev, designed to maintain a
1-to-1 source-to-load impedance ratio with no more than
0.5 dB of ripple in the pass band. Other filter structures can be
effective as long as the second harmonic of the LO is filtered to
negligible levels, e.g., ~30 dB below the fundamental. The meas-
ured frequency response of the Chebyshev filter for a 1200 MHz
-3 dB cutoff frequency is presented in Figure 43.
04826-0-045
AD8344
LOIN
3
COMM
4
LOCM
2
R
L
FOR R
S
= R
L
f
C
- FILTER CUTOFF FREQUENCY
R
S
C1
C3
LO
SOURCE
L2
C1 =
1.864
2
f
cR
L
C3 =
1.834
2
f
cR
L
L2 =
1.28R
L
2
f
c
Figure 42. Using a Low-Pass Filter to Reduce LO Second Harmonic
AD8344
Rev. 0 | Page 16 of 20
0
50
45
40
35
30
25
20
15
10
5
0.1
1
10
04826-0-046
FREQUENCY (GHz)
R
ESPON
SE (
d
B
)
IDEAL LPF
REAL LPF
4.7pF
4.7pF
6.8nH
Figure 43. Measured and Ideal LO Filter Frequency Response
BIAS RESISTOR SELECTION
An external bias resistor is used to set the dc current in the
mixer core. This provides the ability to reduce power consump-
tion at the expense of decreased dynamic range. Figure 44
shows the spurious-free dynamic range (SFDR) of the mixer for
a 1 Hz noise bandwidth versus the R
BIAS
resistor value. SFDR
was calculated using NF and IIP3 data collected at 900 MHz.
By definition,
(
)
)
(
10log
3
2
B
kT
NF
IIP3
SFDR
-
-
-
=
where IIP3 is the input third-order intercept in dBm. NF is the
noise figure in dB. kT is the thermal noise power density and is
-173.86 dBm/Hz at 298K. B is the noise bandwidth in Hz.
In order to calculate the anticipated SFDR for a given applica-
tion, it is necessary to factor in the actual noise bandwidth. For
instance, if the IF noise bandwidth was 5 MHz, the anticipated
SFDR using a 2.43 k R
BIAS
would be 6.66 log10 (5 MHz) less
than the 1 Hz data in Figure 44 or ~80 dBc. Using a 2.43 k bias
resistor will set the quiescent power dissipation to ~415 mW for
a 5 V supply. If the R
BIAS
resistor value was raised to 3.9 k, the
SFDR for the same 5 MHz bandwidth would be reduced to
~77.5 dBc and the power dissipation would be reduced to
~335 mW. In low power portable applications it may be advanta-
geous to reduce power consumption by using a larger value of R
BIAS
,
assuming reduced dynamic range performance is acceptable.
125
120
85
81
77
73
69
65
121
122
123
124
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
04826-0-047
R
BIAS
(k
)
S
F
DR (dBc
)
S
U
P
P
L
Y
CURRE
NT (mA)
AD8344
COMM
9
EXRB
10
PWDN
11
VPDC
12
+V
S
R
BIAS
Figure 44. Impact of R
BIAS
Resistor Selection vs. Spurious-Free
Dynamic Range and Power Consumption,
F
RF
= 890 MHz and F
LO
= 1090 MHz
CONVERSION GAIN AND IF LOADING
The AD8344 is optimized for driving a 200 differential load.
Although the device is capable of driving a wide variety of
loads, in order to maintain optimum distortion and noise
performance, it is advised that the presented load at the IF
outputs is reasonably close to 200 . Figure 45 illustrates the
effect of IF loading on conversion gain. The mixer outputs
behave like Norton equivalent sources, where the conversion
gain is the effective transconductance of the mixer multiplied
by the loading impedance. The linear differential voltage
conversion gain of the mixer can be modeled as
RF
m
m
LOAD
f
g
j
g
R
Av
+
-
=
37.70
1
0.46
where R
LOAD
is the differential loading impedance. g
m
is the
mixer transconductance and is equal to 4070/R
BIAS
. f
RF
is the
frequency of the signal applied to the RF port in GHz.
Large impedance loads cause the conversion gain to increase,
resulting in a decrease in input linearity and allowable signal
swing. In order to maintain positive conversion gain and pre-
serve spurious-free dynamic range performance, the differential
load presented at the IF port should remain within a range of
~100 to 250 .
AD8344
Rev. 0 | Page 17 of 20
25
5
0
5
10
15
20
10
100
1000
04826-0-048
IF LOADING (
)
20LOG
CONVERSION
GAIN (
d
B)
MEASURED
MODELED
15
0
15
12
9
6
3
0
3
6
9
12
10
15
20
25
30
35
40
45
50
04826-0-049
IF FREQUENCY (MHz)
C
O
N
VER
SION
GA
IN
(
d
B
)
INP
U
T IP
3
AND P
1
dB (dBm)
Figure 45. Conversion Gain vs. IF Loading
Figure 46. Conversion Gain, Input IP3, and P1dB vs.
IF Frequency, F
RF
= 450 MHz
LOW IF FREQUENCY OPERATION
8
7
2
28.0
24.5
21.0
17.5
14.0
10.5
7.0
3
4
5
6
10
15
20
25
30
35
40
45
50
04826-0-050
IF FREQUENCY (MHz)
C
O
N
VER
SION
GA
IN
(
d
B
)
INP
U
T IP
3
AND P
1
dB (dBm)
The AD8344 may be used down to arbitrarily low IF frequen-
cies. The conversion gain, noise, and linearity characteristics
remain quite flat as IF frequency is reduced, as indicated in
Figure 46 and Figure 47. Larger value pull-up inductors need to
be used at the lower IF frequencies. A 1 H choke inductor
would present a common-mode loading impedance of 63 at
an IF frequency of 10 MHz, severely loading down the mixer
outputs, reducing conversion gain, and sacrificing output power.
At low IF frequencies, choke inductors of several hundred H
should be used for biasing the IF outputs.
Figure 47. Conversion Gain, Input IP3, and P1dB vs.
IF Frequency, F
RF
= 890 MHz
AD8344
Rev. 0 | Page 18 of 20
EVALUATION BOARD
An evaluation board is available for the AD8344. The evaluation
board is configured for single-ended signaling at the IF output
port via a balun transformer. The schematic for the evaluation
board is presented in Figure 48.
Table 5. Evaluation Boards Configuration Options
Component
Function
Default Conditions
R1, R2, R7,
C2, C4, C5, C6,
C12, C13, C14,
C15
Supply Decoupling.
Jumpers or power supply decoupling resistors and filter capacitors.
R1, R2, R7 = 0 (Size 0603)
C4, C6, C13, C14 = 100 pF
(Size 0603)
C2, C5, C12, C15 = 0.1 F
(Size 0603)
R3, R4
Jumpers in Single-Ended IF Output Circuit.
0 (Size 0603)
R6, C11
R
BIAS
resistor that sets the bias current for the mixer core.
The capacitor provides ac bypass for R6.
R6 = 2.43 k (Size 0603)
C11 = 100 pF (Size 0603)
R8
Jumper for pull down of the PWDN pin.
R8 = 10 k (Size 0603)
R9
Jumper.
R9 = 0 (Size 0603)
C3
RF Input AC Coupling. Provides dc block for RF input.
C3 = 100 pF (Size 0402)
C1
RF Common AC Coupling. Provides dc block for RF input common connection.
C1 = 100 pF (Size 0402)
C8
LO Input AC Coupling. Provides dc block for the LO input.
C8 = 100 pF (Size 0402)
C7
LO Common AC Coupling. Provides dc block for LO input common connection.
C7 = 100 pF (Size 0402)
SW1
Power Down. The part is on when the PWDN is connected to ground via SW1.
The part is disabled when PWDN is connected to the positive supply (V
S
) via SW1.
T1
IF Output Balun Transformer. Converts differential, high impedance IF output
to single-ended. When loaded with 50 , this balun presents a 200 load to the
mixers collectors. The center tap of the primary is used to supply the bias voltage
(V
S
) to the IF output pins.
T1 = TC4-1W, 4:1 (Mini-Circuits)
R11, Z3, Z4
R12, Z1, Z2
IF Output Interface--IFOP, IFOM. These positions can be used to modify the
impedance presented to the IF outputs.
R11 = 0 (Size 0603)
Z3, Z4 = Open
R12 = 0 (Size 0603)
Z1, Z2 = Open
AD8344
Rev. 0 | Page 19 of 20
04826-0-005
VPLO
LOCM
LOIN
COMM
VPD
C
PW
D
N
EXR
B
COMM
COMM
IFOP
IFOM
COMM
COMM
RFCM
RFIN
VPMX
AD8344
C1
100pF
C3
100pF
C6
100pF
C7
100pF
C8
100pF
C5
0.1
F
C4
100pF
C2
0.1
F
R2
0
R1
0
R7
0
R6
2.43k
C11
100pF
R10
0
R9
0
R3
0
R11
0
VPOS
VPOS
COMMON
POWER
DOWN
RF INPUT
LO
INPUT
Z1
OPEN
Z2
OPEN
R8
10k
Z3
OPEN
Z4
OPEN
R4
0
T1
TC4-1W
IF
OUTPUT
C14
100pF
C15
0.1
F
VPOS
SW1
C13
100pF
C12
0.1
F
Figure 48. Evaluation Board Schematic--Single-Ended IF Output
04826-0-007
Figure 49. Single-Ended Evaluation Board, Component Side Layout
04826-0-008
Figure 50. Single-Ended Evaluation Board, Component Side Silkscreen
AD8344
Rev. 0 | Page 20 of 20
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1 INDICATOR
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP VIEW
12 MAX
0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
1.65
1.50 SQ*
1.35
BOTTOM
VIEW
16
5
13
8
9
12
4
* COMPLIANTTO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm 3 mm Body (CP-16-3)
Dimensions in millimeters
ORDERING GUIDE
Models
Temperature Range
Package Description
Package Option
Branding
AD8344ACPZ-REEL7
1
-40C to +85C
16-Lead Lead Frame Chip Scale Package (LFCSP)
CP-16-3
JHA
AD8344ACPZ-WP
1, 2
-40C to +85C
16-Lead Lead Frame Chip Scale Package (LFCSP)
CP-16-3
JHA
AD8344-EVAL
Evaluation Board
1
Z = Pb-free part.
2
WP = Waffle pack.
2004 Analog Devices, Inc. All rights reserved. Trademarks and
regis-
tered trademarks are the property of their respective owners.
D0482606/04(0)
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