Document Outline
- Specifications
- Pinout
- Package drawings
- Ordering Guide
- Features
- Applications
- Product Description
- Absolute Maximum Ratings
- Functional Block Diagram
- Pin Function Description
- Circuit Description
- Typical Characteristics
- EQUIVALENT CIRCUITS
- CIRCUIT DESCRIPTION
- BASIC CONNECTIONS
- CDMA IS95
- GSM
- WCDMA 3GPP
- DIAGRAMS
- Equivalent Circuits
- AD8345 Block Diagram
- Basic Connections
- Single-Ended IQ Drive Circuit
- AD8345/TxDAC Interface
- Evaluation Board Schematic
- Evaluation Board Silkscreen
- Layout of Evaluation Board, Top Layer
- Layout of Evaluation Board, Bottom Layer
- Characterization Board SSB Test Setup
- Test Setup for Evaluating AD8345 with Modulated Waveforms
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD8345
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
250 MHz1000 MHz
Quadrature Modulator
FUNCTIONAL BLOCK DIAGRAM
16
QBBP
QBBN
15
COM3
14
COM3
13
VPS2
12
VOUT
11
COM2
10
COM3
9
1
IBBP
2
IBBN
3
COM3
4
COM1
5
LOIN
6
LOIP
7
VPS1
8
ENBL
BIAS
+
PHASE
SPLITTER
AD8345
FEATURES
250 MHz1000 MHz Operating Frequency
+2.5 dBm P1 dB @ 800 MHz
155 dBm/Hz Noise Floor
0.5 Degree RMS Phase Error (IS95)
0.2 dB Amplitude Balance
Single 2.7 V5.5 V Supply
Pin-Compatible with AD8346
16-Lead Exposed Paddle TSSOP Package
APPLICATIONS
Cellular Communication Systems
W-CDMA/CDMA/GSM/PCS/ISM Transceivers
Fixed Broadband Access Systems LMDS/MMDS
Wireless LAN
Wireless Local Loop
Digital TV/CATV Modulators
Single Sideband Upconverter
PRODUCT DESCRIPTION
The AD8345 is a silicon RFIC quadrature modulator, designed
for use from 250 MHz to 1000 MHz. Its excellent phase accu-
racy and amplitude balance enable the high performance direct
modulation of an IF carrier.
The AD8345 accurately splits the external LO signal into two
quadrature components through the polyphase phase-splitter
network. The two I and Q LO components are mixed with the
baseband I and Q differential input signals. Finally, the outputs
of the two mixers are combined in the output stage to provide a
single-ended 50
drive at VOUT.
APPLICATIONS
The AD8345 Modulator can be used as the IF transmit modu-
lator in digital communication systems such as GSM and PCS
transceivers. It can also directly modulate an LO signal to
produce QPSK and various QAM formats for 900 MHz com-
munication systems as well as digital TV and CATV systems.
Additionally, this quadrature modulator can be used with direct
digital synthesizers in hybrid phase-locked loops to generate
signals over a wide frequency range with millihertz resolution.
The AD8345 Modulator is supplied in a 16-lead TSSOP pack-
age with exposed paddle. Its performance is specified over a
40
C to +85C temperature range. This device is fabricated on
Analog Devices' advanced silicon bipolar process.
REV. 0
2
AD8345SPECIFICATIONS
(V
S
= 5 V; LO= 2 dBm @ 800 MHz, 50
source and load impedances, I and Q inputs
0.7 V 0.3 V on each side for a 1.2 V p-p differential input, I and Q inputs driven in quadrature @ 1 MHz Baseband Frequency.
T
A
= 25 C, unless otherwise noted.)
Parameters
Conditions
Min
Typ
Max
Unit
RF OUTPUT
Operating Frequency
1
250
1000
MHz
Output Power
3
1
+2
dBm
Output P1 dB
2.5
dBm
Noise Floor
20 MHz Offset from LO, All BB
155
dBm/Hz
Inputs at 0.7 V
Quadrature Error
(CDMA IS95 Setup, Refer to Figure 13)
0.5
Degree rms
I/Q Amplitude Balance
(CDMA IS95 Setup, Refer to Figure 13)
0.2
dB
LO Leakage
42
33
dBm
Sideband Rejection
42
34
dBc
Third Order Distortion
52
dBc
Second
Order Distortion
60
dBc
Equivalent Output IP3
25
dBm
Equivalent Output IP2
59
dBm
Output Return Loss (S22)
20
dB
RESPONSE TO CDMA IS95
(Refer to Figure 13)
BASEBAND SIGNALS
ACPR
72
dBc
EVM
1.3
%
Rho
0.9995
LO INPUT
LO Drive level
10
2
0
dBm
LOIP Input Return Loss (S11)
2
No Termination on LOIP, LOIN at
5
dB
AC Ground
50
Terminating Resistor, Differential
9
dB
Drive via Balun
BASEBAND INPUTS
Input Bias Current
10
A
Input Capacitance
2
pF
DC Common Level
0.6
0.7
0.8
V
Bandwidth (3 dB)
Full Power (0.7 V
0.3 V on Each
80
MHz
Input, Refer to TPC 2)
ENABLE
Turn-On
Enable High to Output within 0.5 dB of
2.5
s
Final Value
Turn-Off
Enable Low to Supply Current Dropping
1.5
s
below 2 mA
ENBL High Threshold (Logic 1)
+V
S
/2
V
ENBL Low Threshold (Logic 0)
+V
S
/2
V
POWER SUPPLIES
Voltage
2.7
5.5
V
Current Active
50
65
78
mA
Current Standby
70
A
NOTES
1
For information on operation below 250 MHz, see Figure 4.
2
See LO Drive section for more details on input matching.
Specifications subject to change without notice.
REV. 0
AD8345
3
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8345 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage VPS1, VPS2 . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input Power LOIP, LOIN (re 50
) . . . . . . . . . . . . . 10 dBm
IBBP, IBBN, QBBP, QBBN . . . . . . . . . . . . . . . . . 0 V, 2.5 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 500 mW
JA
(Exposed Paddle Soldered Down) . . . . . . . . . . . . 30
C/W
JA
(Exposed Paddle not Soldered Down) . . . . . . . . . 95
C/W
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150
C
Operating Temperature Range . . . . . . . . . . . 40
C to +85C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATION
16
15
14
13
12
11
10
9
QBBP
QBBN
COM3
COM3
VPS2
VOUT
COM2
COM3
1
2
3
4
5
6
7
8
IBBP
IBBN
COM3
COM1
LOIN
LOIP
VPS1
ENBL
AD8345
TOP VIEW
(Not to Scale)
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8345ARE
40
C to +85C
Tube (16-Lead TSSOP with Exposed Pad)
RE-16
AD8345ARE-REEL
13" Tape and Reel
AD8345ARE-REEL7
7" Tape and Reel
AD8345-EVAL
Evaluation Board
REV. 0
AD8345
4
PIN FUNCTION DESCRIPTIONS
Equivalent
Pin No.
Mnemonic
Function
Circuit
1, 2
IBBP, IBBN
I Channel Baseband Differential Input Pins. These high impedance inputs should
Circuit A
be dc biased to approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p
on each pin (0.4 V to 1 V). This gives a differential drive of 1.2 V p-p. Inputs are
not self-biasing so external biasing circuitry must be used in ac-coupled applications.
3, 9, 13, 14
COM3
Ground Pin for Input V-to-I Converters and Mixer Core.
4
COM1
Ground Pin for the LO Phase-Splitter and LO Buffers.
5, 6
LOIN, LOIP
Differential LO Drive Pins. Internal dc bias (approximately 1.8 V @ V
S
= 5 V)
Circuit B
is supplied. Pins must be ac-coupled. Single-ended or differential drive is permissible.
7
VPS1
Power Supply Pin for the Bias Cell and LO Buffers. This pin should be decoupled
using local 1000 pF and 0.01
F capacitors.
8
ENBL
Enable Pin. A high level enables the device; a low level puts the device in sleep mode. Circuit C
10
COM2
Ground Pin for the Output Stage of Output Amplifier.
11
VOUT
50
DC-Coupled RF Output. Pin should be ac-coupled.
Circuit D
12
VPS2
Power supply pin for baseband input voltage to current converters and mixer core.
This pin should be decoupled using local 1000 pF and 0.01
F capacitors.
15, 16
QBBN, QBBP
Q Channel Baseband Differential Input Pins. Inputs should be dc biased to
Circuit A
approximately 0.7 V. Nominal characterized ac swing is 0.6 V p-p on each pin
(0.4 V to 1 V). This gives a differential drive level of 1.2 V p-p. Inputs are not
self-biasing so external biasing circuitry must be used in ac-coupled applications.
EQUIVALENT CIRCUITS
INPUT
CURRENT
MIRROR
TO MIXER
CORE
BUFFER
VPS2
Circuit A
PHASE
SPLITTER
CONTINUES
LOIN
VPS1
LOIP
Circuit B
ENBL
100k
VPS2
100k
100k
TO BIAS FOR
STARTUP/
SHUTDOWN
Circuit C
40
40
VPS2
VOUT
Circuit D
Figure 1. Equivalent Circuits
REV. 0
AD8345
5
Typical Performance Characteristics
LO FREQUENCY MHz
0
250
SSB PO
WER dBm
2
4
6
8
10
12
14
16
18
20
300 350 400 450 500 550 600 650 700 750 800 850 900 9501000
V
S
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
TPC 1. Single Sideband (SSB) Output Power (P
OUT
) vs. LO
Frequency (F
LO
). (I and Q Inputs Driven in Quadrature at
Baseband Frequency (F
BB
) = 1 MHz; T
A
= 25
C)
BASEBAND FREQUENCY MHz
0.1
OUTPUT PO
WER
V
ARIA
TION
dB
5.5
1
10
100
V
S
= 2.7V, 5V DIFFERENTIAL INPUT = 200mV p-p
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.5
1.0
TPC 2. I and Q Input Bandwidth. (T
A
= 25
C, F
LO
= 800 MHz,
LO Level = 2 dBm, I and Q Inputs Driven in Quadrature)
TEMPERATURE C
40
SSB PO
WER
dBm
26
0
40
80
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
V
S
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
24
22
20
18
16
14
12
10
8
6
4
2
0
20
20
60
TPC 3. SSB P
OUT
vs. Temperature. (F
LO
= 800 MHz, LO
Level = 2 dBm, F
BB
= 1 MHz, I and Q Inputs Driven in
Quadrature)
LO FREQUENCY MHz
250
SSB OUTPUT P1dB
dBm
500
800
T
A
= +85 C
16
14
12
10
8
6
4
2
0
350
650
950
300
400 450
550 600
700 750
850 900
1000
T
A
= 40 C
T
A
= +25 C
TPC 4. SSB Output 1 dB Compression Point (OP 1 dB) vs.
F
LO
. (V
S
= 2.7 V, LO Level = 2 dBm, I and Q Inputs Driven
in Quadrature, F
BB
= 1 MHz)
LO FREQUENCY MHz
250
SSB OUTPUT P1dB
dBm
500
800
T
A
= +85 C
0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
350
650
950
300
400 450
550 600
700 750
850 900
1000
T
A
= 40 C
T
A
= +25 C
4.0
TPC 5. SSB Output 1 dB Compression Point (OP 1 dB) vs.
F
LO
. (V
S
= 5 V, LO Level = 2 dBm, I and Q Inputs Driven in
Quadrature, F
BB
= 1 MHz)
LO FREQUENCY MHz
250
CARRIER FEEDTHR
OUGH
dBm
500
800
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
50
350
650
950
300
400 450
550 600
700 750
850 900
1000
49
48
47
46
45
44
43
42
41
40
V
S
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
TPC 6. Carrier Feedthrough vs. F
LO
. (LO Level = 2 dBm,
T
A
= 25
C)
REV. 0
AD8345
6
TEMPERATURE C
40
CARRIER FEEDTHR
OUGH
dBm
0
50
20
20
40
60
80
48
46
44
42
40
38
36
34
32
30
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
V
S
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
TPC 7. Carrier Feedthrough vs. Temperature.
(F
LO
= 800 MHz, LO Level = 2 dBm)
CARRIER FEEDTHROUGH dBm
AFTER NULLING TO 65dBm AT +25 C
86
PERCENT
A
G
E
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
82
78
74
70
66
62
58
54
50
T = +85
T = 40
TPC 8. Carrier Feedthrough Distribution at Temperature
Extremes. After Feedthrough Nulled to <65 dBm at T
A
=
25
C. (F
LO
= 800 MHz, LO Level = 2 dBm)
LO FREQUENCY MHz
SIDEB
AND SUPPRESSION
dBc
30
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
V
S
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
1000
32
34
36
38
40
42
44
46
48
50
950
900
850
800
750
700
650
600
550
500
450
400
350
300
250
TPC 9. Sideband Suppression vs. F
LO
. (T
A
= 25
C,
LO Level = 2 dBm, F
BB
= 1 MHz, I and Q Inputs
Driven in Quadrature)
BASEBAND FREQUENCY MHz
SIDEB
AND SUPPRESSION
dBc
26
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
V
S
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
50
28
30
32
34
36
38
40
42
44
45
40
35
30
25
20
15
10
5
0
TPC 10. Sideband Suppression vs. F
BB
. (T
A
= 25
C,
F
LO
= 800 MHz, LO Level = 2 dBm, I and Q Inputs
Driven in Quadrature)
TEMPERATURE C
SIDEB
AND SUPPRESSION
dBc
35
80
37
38
39
40
41
42
43
44
45
60
40
20
0
20
40
36
V
S
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
TPC 11. Sideband Suppression vs. Temperature.
(F
LO
= 800 MHz, LO Level = 2 dBm, F
BB
=1 MHz,
I and Q Inputs Driven in Quadrature)
BASEBAND FREQUENCY MHz
THIRD ORDER DIST
O
R
T
ION
dBc
V
S
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
65
0
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
60
55
50
45
40
35
30
25
20
5
10
15
20
25
30
35
40
45
50
TPC 12. Third Order Distortion vs. F
BB
. (T
A
= 25
C,
F
LO
= 800 MHz, LO Level = 2 dBm, I and Q Inputs
Driven in Quadrature)
REV. 0
AD8345
7
TEMPERATURE C
THIRD ORDER DIST
O
R
T
ION
dBc
45
80
55
65
70
75
80
60
40
20
0
20
40
50
60
V
S
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
TPC 13. Third Order Distortion vs. Temperature.
(F
LO
= 800 MHz, LO Level = 2 dBm, F
BB
=1 MHz,
I and Q Inputs Driven in Quadrature)
BASEBAND DIFFERENTIAL INPUT VOLTAGE V p-p
THIRD ORDER DIST
O
R
T
ION
dBc
10
SSB P
OUT
3.0
2.5
2.0
1.5
1.0
0.5
0.0
THIRD ORDER DISTORTION
15
20
25
30
35
40
45
50
55
70
60
SSB OUTPUT PO
WER
dBm
6
2
4
8
10
12
14
16
18
20
26
65
22
24
TPC 14. Third Order Distortion and SSB P
OUT
vs. Base-
band Differential Input Level. (T
A
= 25
C, F
LO
= 800 MHz,
LO Level = 2 dBm, F
BB
= 1 MHz, V
S
= 2.7 V)
BASEBAND DIFFERENTIAL INPUT VOLTAGE V p-p
THIRD ORDER DIST
O
R
T
ION
dBc
5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
10
15
25
30
35
40
45
50
55
65
60
SSB OUTPUT PO
WER
dBm
6
2
4
8
10
12
14
16
18
20
22
20
70
0
2
4
THIRD ORDER DISTORTION
SSB P
OUT
TPC 15. Third Order Distortion and SSB P
OUT
vs. Base-
band Differential Input Level. (T
A
= 25
C, F
LO
= 800 MHz,
LO level = 2 dBm, F
BB
= 1 MHz, V
S
= 5 V)
TEMPERATURE C
40
SUPPL
Y CURRENT
mA
0
40
20
20
40
60
80
45
50
55
60
65
70
75
80
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V p-p
V
S
= 2.7V, DIFFERENTIAL INPUT = 200mV p-p
TPC 16. Power Supply Current vs. Temperature
WITH 50
WITH 100
LOIN NO BALUN
OR TERMINATION
SMITH CHART
NORMALIZED
TO 50
1GHz
1GHz
250MHz
TPC 17. Smith Chart of LOIN Port S11 (LOIP Pin AC-
Coupled to Ground). Curves with Balun and External
Termination Resistors Also Shown. (V
S
= 5 V,
T
A
= 25
C)
FREQUENCY MHz
RETURN LOSS
dB
0
250
10
30
5
15
20
25
300 350 400 450 500 550 600 650 700 750 800 850 900 9501000
V
S
= 5V
V
S
= 2.7V
TPC 18. Return Loss (S22) of VOUT Output (T
A
= 25
C)
REV. 0
AD8345
8
CIRCUIT DESCRIPTION
Overview
The AD8345 can be divided into the following sections: Local
Oscillator (LO) Interface, Mixer, Differential Voltage-to-Cur-
rent (V-to-I) Converter, Differential-to-Single-Ended (D-to-S)
Converter, and Bias. A block diagram of the part is shown in
Figure 2.
OUT
LOIP
LOIN
IBBP
IBBN
QBBP
QBBN
PHASE
SPLITTER
Figure 2. AD8345 Block Diagram
The LO Interface generates two LO signals at 90 degrees of
phase difference with each other, to drive two mixers in quadra-
ture. Baseband signals are converted into current form in the
Differential V-to-I Converters, feeding into the two mixers. The
outputs of the mixers are combined to feed the Differential-to-
Single-Ended Converter, which provides a 50
output interface.
Bias currents to each section are controlled by the Enable
(ENBL) signal. Detailed description of each section follows.
LO Interface
The LO Interface consists of interleaved stages of polyphase
phase-splitters and buffer amplifiers. The polyphase phase-splitter
contains resistors and capacitors connected in a circular manner
to split the LO signal into I and Q paths in precise quadra-
ture with each other. The signal on each path goes through a
buffer amplifier to make up for the loss and high frequency
roll-off. The two signals then go through another polyphase
network to enhance the quadrature accuracy. The broad oper-
ating frequency range (250 MHz to 1000 MHz) is achieved
by staggering the RC time constants of each stage of the phase-
splitters. The outputs of the second phase-splitter are fed into
the driver amplifiers for the mixers' LO inputs.
Differential V-to-I Converter
In this circuit, each baseband input pin is connected to an op amp
driving a transistor connected as an emitter follower. A resistor
between the two emitters maintains a varying current propor-
tional to the differential input voltage through the transistor. These
currents are fed to the two mixers in differential form.
Mixers
There are two double-balanced mixers, one for the In-phase
Channel (I-Channel) and one for the Quadrature Channel (Q-
Channel). Each mixer uses the Gilbert-cell design with four
cross-connected transistors. The bases of the transistors are
driven by the LO signal of the corresponding channel. The
output currents from the two mixers are summed together in
two load resistors. The signal developed across the load resistors
is sent to the D-to-S stage.
Differential to Single-Ended Converter
The differential-to-single-ended converter consists of two emit-
ter followers driving a totem-pole output stage whose output
impedance is established by the emitter resistors in the output
transistors. The output of this stage is connected to the output
(VOUT) pin.
Bias
A bandgap reference circuit based on the
-VBE principle gen-
erates the Proportional-To-Absolute-Temperature (PTAT) as
well as temperature-stable currents used by the different sec-
tions as references. When the bandgap reference is disabled by
pulling down the voltage at the ENBL pin, all other sections are
shut off accordingly.
LO LEVEL dBm
NOISE FLOOR
dBm/Hz
150
10
152
160
151
153
154
155
V
S
= 5V
156
157
158
159
9
8
7
6
5
4
3
2
1
0
1
2
TPC 19. Noise Floor vs. LO Input Power. (T
A
= 25
C, F
LO
=
800 MHz, V
S
= 5 V, All I and Q Inputs are DC-Biased to
0.7 V) Noise Measured at 20 MHz Offset from Carrier
LO LEVEL dBm
CARRIER FEEDTHR
OUGH
dBm
36
10
V
S
= 5.5V
40
50
38
42
44
46
48
9
8
7
6
5
4
3
2
1
0
1
2
TPC 20. LO Feedthrough vs. LO Input Power. (T
A
= 25
C,
LO = 800 MHz, V
S
= 5.5 V)
REV. 0
AD8345
9
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
AD8345
QBBP
QBBN
COM3
COM3
VPS2
VOUT
COM2
COM3
IBBP
IBBN
COM3
COM1
LOIN
LOIP
VPS1
ENBL
IP
1
T1
ETC1-1-13
2
3
4
5
LO
R1
50
C6
1000pF
C7
1000pF
IN
C3
1000pF
C4
0.01 F
+V
S
QP
QN
C1
1000pF
C2
0.01 F
+V
S
VOUT
C5
1000pF
Figure 3. Basic Connections
LO FREQUENCY MHz
40
SIDEB
AND SUPPRESSION
dBc
60
60
80
100 120 140 160 180 200 220 240 260 280 300
55
50
45
40
35
30
25
20
15
10
5
V
S
= 5V, DIFFERENTIAL INPUT = 1.2V
Figure 4. Typical Lower Frequency Sideband Suppression
Performance
Baseband I and Q Channel Drive
The I and Q channel baseband inputs should be driven differen-
tially. This is convenient as most modern high-speed DACs
have differential outputs. For optimal performance at V
S
= 5 V,
the drive signal should be a 1.2 V p-p differential signal with a
bias level of 0.7 V; that is, each input should swing from 0.4 V
to 1 V. If the AD8345 is being run on a lower supply voltage,
the peak-to-peak voltage on the I and Q channel inputs must be
reduced to avoid input clipping. For example, at a supply volt-
age of 2.7 V, a 200 mV p-p differential drive is recommended.
This will result in a corresponding reduction in output power
(see TPC 1). The I and Q inputs have a large input bandwidth
of approximately 80 MHz. At lower baseband input levels, the
input bandwidth increases (see TPC 2).
If the baseband signal has a high peak-to-average ratio (e.g.,
CDMA or WCDMA), the rms signal strength will have to be
backed off from this peak level in order to prevent clipping of
the signal peaks. Clipping of signal peaks will tend to increase
signal leakage into adjacent channels. Backing off the I and Q
signal strength in the manner recommended will reduce the output
power by a corresponding amount. This also applies to multicarrier
applications where the per-carrier output power will be lower by
3 dB for each doubling of the number of output carriers.
BASIC CONNECTIONS
The basic connections for operating the AD8345 are shown in
Figure 3. A single power supply of between 2.7 V and 5.5 V is
applied to pins VPS1 and VPS2. A pair of ESD protection diodes
are connected internally between VPS1 and VPS2 so these must
be tied to the same potential. Both pins should be individually
decoupled using 1000 pF and 0.01
F capacitors, located as
close as possible to the device. For normal operation, the enable
pin, ENBL, must be pulled high. The turn-on threshold for
ENBL is V
S
/2. Pins COM1 to COM3 should all be tied to the
same low impedance ground plane.
LO Drive
In Figure 3, a 50
resistor to ground combines with the device's
high input impedance to provide an overall input impedance of
approximately 50
(see TPC 17 for a plot of LO port input
impedance). For maximum LO suppression at the output, a
differential LO drive is recommended. In Figure 3, this is
achieved using a balun (M/A-COM Part Number ETC1-1-13).
The output of the balun is ac coupled to the LO inputs which
have a bias level about 1.8 V dc. An LO drive level of 2 dBm is
recommended for lowest output noise. Higher levels will degrade
linearity while lower levels will tend to increase the noise floor
slightly. For example, reducing the LO power from 2 dBm to
10 dBm will increase the noise floor by approximately 0.3 dB
(see TPC 19).
The LO terminal can be driven single-ended at the expense of
slightly higher LO leakage. LOIN is ac coupled to ground using
a capacitor and LOIP is driven through a coupling capacitor
from a (single-ended) 50
source (this scheme could also be
reversed with the drive signal being applied to LOIN).
LO Frequency Range
The frequency range on the LO input is limited by the internal
quadrature phase splitter. The phase splitter generates drive
signals for the internal mixers which are 90
out of phase relative
to one another. Outside of the specified LO frequency range of
250 MHz to 1 GHz, this quadrature accuracy degrades, result-
ing in decreased sideband suppression. See TPC 9 for a plot of
sideband suppression vs. LO frequency from 250 MHz to 1 GHz.
Figure 4 shows the sideband suppression of a typical device
from 50 MHz to 300 MHz. The level of sideband suppression
degradation below 250 MHz will be subject to manufacturing
process variations.
REV. 0
AD8345
10
The I and Q inputs have high input impedances because they
connect directly to the bases of pnp transistors. If a (dc-coupled)
filter is being used between a DAC and the modulator inputs,
this filter will need to be terminated with the appropriate resis-
tance. If the filter is differential, the termination resistor should
be connected across the I and Q differential inputs.
Reduction of LO Leakage
Because the I and Q signals are being effectively multiplied with
the LO, any internal offset voltages on these inputs will result in
leakage of the LO. The nominal LO leakage of 42 dBm which
results from these internal offset voltages, can be reduced further
by applying offset compensation voltages on the I and Q inputs.
(Note that LO feedthrough is reduced by varying the differential
offset voltages on the I and Q inputs, not by varying the nominal
bias level of 0.7 V.) This is easily accomplished by programming
(and then storing) the appropriate DAC offset code to reduce
the LO leakage. This does, however, require the path from the
DAC to the I and Q inputs to be dc-coupled. (DC-coupling is
also advantageous from the perspective of I and Q input bias-
ing if the DAC is capable of delivering a bias level of 0.7 V).
The procedure for reducing the LO feedthrough is simple. In
order to isolate the LO in the output spectrum, a single side-
band configuration is recommended (set I and Q signals to sine
and cosine waves at, say, 100 kHz, set LO to F
RF
100 kHz).
An offset voltage is applied from the I DAC until the LO leakage
reaches a trough. With this offset level held, an offset voltage is
applied to the Q DAC until a (lower) trough is reached.
LO leakage compensation holds up well over temperature. TPC
8 shows the effect of temperature on LO leakage after compen-
sation at ambient.
Compensated LO leakage will degrade somewhat as the frequency
is moved away from the frequency at which the compensation
was performed. This is due to the effects of LO to RF output
leakage which are not a result of offsets on the I and Q inputs.
Single-Ended I and Q Drive
Where only single-ended I and Q signals are available, a differ-
ential amplifier such as the AD8132 or AD8138 can be used to
generate the required differential drive signal for the AD8345.
Even though most DACs have differential outputs, using a
single-ended low-pass filter between the dual DAC and the I
and Q inputs, may be more desirable from the perspective of
component count and cost. As a result, the output signal from
the filter must be converted back to differential mode and possi-
bly be rebiased to 0.7 V common mode.
Figure 5 shows a circuit which converts a ground-referenced,
single-ended signal to a differential signal and adds the required
0.7 V bias voltage. Two AD8132 differential op amps, config-
ured for a gain of unity, are used. With a 50
input impedance,
this circuit is configured to accept a signal from a 50
source
(e.g., a low-pass filter). The input impedance can be easily changed
by replacing the 49.9
shunt resistor (and the corresponding
24.9
resistor on the inverting input) with the appropriate value.
The required dc-bias level is conveniently added to the signal by
applying 0.7 V to the V
OCM
pins of the differential amplifiers.
Differential amplifiers such as the AD8132 and AD8138 can
also be used to implement active filters. For more information
on this topic, consult the data sheets of these devices.
0.1 F
10 F
+5V
348
0.1 F
348
49.9
348
24.9
10k
1.5k
348
AD8132
PHASE
SPLITTER
VOUT
IBBP
IBBN
QBBP
QBBN
AD8345
LOIP
LOIN
VPS1 VPS2
0.01 F
1000pF
0.01 F
1000pF
0.1 F
10 F
+5V
348
0.1 F
348
49.9
348
24.9
348
AD8132
Q
IN
I
IN
0.1 F
10 F
5V
0.1 F
10 F
COM1 COM2 COM3
5V
Figure 5. Single-Ended IQ Drive Circuit
REV. 0
AD8345
11
Note that this circuit assumes that the single-ended I and Q signals
are ground referenced. Any differential dc-offsets will result
in increased LO Leakage at the output of the AD8345.
It is possible to drive the baseband inputs with a single-ended
signal biased to 0.7 V, with the unused inputs being biased to a
dc level of 0.7 V. However, this mode of operation is not recom-
mended because any dc level difference between the bias level of
the drive signal and the dc level on the unused input (including
the effect of temperature drift) will result in increased LO
leakage. In addition, the maximum output power will be reduced
by 6 dB.
RF Output
The RF output is designed to drive a 50
load but should be ac
coupled as shown in Figure 3. If the I and Q inputs are driven in
quadrature by 1.2 V p-p signals, the resulting output power will
be approximately 1 dBm (see TPC 1).
The RF output impedance is very close to 50
. As a result, no
additional matching circuitry is required if the output is driving
a 50
load.
Application with TxDAC
Figure 6 shows the AD8345 driven by the AD9761 TxDAC
(any of the devices in ADI's TxDAC family can also be used in
this application). The signal from the DAC is being filtered by a
differential 51 MHz low-pass filter.
The I and Q DACs generate differential output currents of 0 mA
to 20 mA and 20 mA to 0 mA, respectively. When loaded with
50
ground-referenced resistors, this would produce a 2 V p-p
differential signal (i.e., 1 V p-p on each output) with a common-
mode level of 0.5 V. In the configuration shown, each DAC output
sees a composite load of 48
(10 + 51 (100 + 51 )) in
the passband. So, for example, when IOUTA is driven to its
positive full scale, IBBP will be equal to 0.96 V. With IOUTB
at 0 mA, the voltage at IBBN will be equal to 0.456 V. This
results in a full-scale differential signal of approximately 1 V p-p
which will have a common-mode level of 0.7 V.
Soldering Information
The AD8345 is packaged in a 16-lead TSSOP package with
exposed pad. For optimum thermal conductivity, the exposed
pad can be soldered to the exposed metal of a ground plane.
This results in a junction-to-air thermal impedance (
JA
) of
30
C/W. However, soldering is not necessary for safe operation.
If exposed pad is not soldered down, the
JA
is equal to 95
C/W.
Evaluation Board
Figure 7. Shows the schematic of the AD8345 evaluation board.
Note that uninstalled components are marked as open. This is a
4-layer board, with the two center layers used as ground plane
and top and bottom layers used as signal and power planes.
The board is powered by a single supply (V
S
) in the range, 2.7 V to
5.5 V. The power supply is decoupled by a 0.01
F and 1000 pF
capacitors. The circuit closely follows the basic connection
schematic with SW1 in B Position. If SW1 is in Position A, the
Enable pin will be pulled to ground by a 10 k
resistor and the
device will be in its power-down mode.
All connectors are SMA-type. The I and Q inputs are dc-coupled
to allow a direct connection to a dual DAC with differential
outputs. Resistor pads are provided in case termination at the
I and Q inputs is required. The local oscillator input (LO) is
terminated to approximately 50
with an external 50 resistor
to ground. A 1:1 wide-band transformer (ETC1-1-13) provides
a differential drive to the AD8345's differential LO input. The
device can also be driven single-ended by shorting out T1.
33pF
100
310nH
33pF
310nH
51
10
51
33pF
100
310nH
33pF
310nH
51
10
51
PHASE
SPLITTER
VOUT
IBBP
IBBN
QBBP
QBBN
AD8345
LOIP
LOIN
VPS1
VPS2
IOUTB
IOUTA
"I"
DAC
2
LATCH
"I"
"Q"
DAC
2
LATCH
"Q"
QOUTA
0.1 F
R
SET
2k
REFIO
FS ADJ
SLEEP
SELECT
WRITE
CLOCK
AD9761
MUX
CONTROL
AVDD
DVDD
DCOM
QOUTB
DAC
DATA
INPUTS
Figure 6. AD8345/TxDAC Interface
REV. 0
AD8345
12
-
Figure 10. Layout of Evaluation Board, Bottom Layer
16
1
IBBP
QBBP
15
2
IBBN
QBBN
14
3
COM3
COM3
13
4
COM1
COM3
12
5
LOIN
VPS2
11
6
LOIP
VOUT
10
7
VPS1
COM2
9
8
ENBL
COM3
AD8345
IP
IN
1
T1
ETC1-1-13
2
3
4
5
LO
R6
50
C1
1000pF
C2
1000pF
C3
0.01 F
C4
1000pF
VPOS
QP
QN
C5
1000pF
C6
0.01 F
VPOS
VOUT
C7
1000pF
R2
(OPEN)
R1
(OPEN)
R7
0
SW1
A
VPOS
B
R8
10k
ENBL
R12
0
R14
(OPEN)
R15
(OPEN)
R11
0
R10
(OPEN)
R9
(OPEN)
Figure 7. Evaluation Board Schematic
ENBL
L0
IN
TP 4
IP
QP
QN
R 6
C 4
R 8
R 2
R 1
R 9
R 10
R 14
R 15
TP 3
TP 1
R 12
TP 2
T 1 C 1
C 2
DUT
VOUT
08-007084
REV A
AD8345 EVAL BOARD
COMPONENT
SIDE
C 5
C 7
SW 1
A
B
a
Figure 8. Evaluation Board Silkscreen
Figure 9. Layout of Evaluation Board, Top Layer
REV. 0
AD8345
13
IEEE
HP34970A
D1
D2
D3
34901
34907
34907
D1
D2
D3
INTERFACE
BOARD
I_IN
Q_IN
OUTPUT_1
OUTPUT_2
ARB FUNCTION GEN
IEEE
TEKAFG2020
VPS1
VN
GND
VP
+15V MAX
COM
+25V MAX
25V MAX
HP3631
IEEE
AD8345
CHARACTERIZATION
BOARD
P1
IN
IP
QP
QN
ENBL
VOUT
P1
IN
IP
QP QN
RFOUT
IEEE
HP8648C
LO
IEEE
PC CONTROLLER
SPECTRUM
ANALYZER
RF I/P
SWEEP OUT
IEEE
28V
HP8593E
Figure 11. Characterization Board SSB Test Setup
CHARACTERIZATION SETUPS
SSB Setup
Essentially, two primary setups were used to characterize the
AD8345. These setups are shown in Figures 11 and 13. Figure
11 shows the setup used to evaluate the product as a Single
Sideband modulator. The interface board converts the single-
ended I and Q inputs from the arbitrary function generator to
differential inputs with a dc bias of approximately 0.7 V. The
interface board also provides connections for power supply
routing. The HP34970A and its associated plug-in 34901 were
used to monitor power supply currents and voltages being
supplied to the AD8345 characterization board. Two HP34907
plug-ins were used to provide additional miscellaneous dc and
control signals to the interface board. The LO input was driven
directly by an RF signal generator and the output was measured
directly with a spectrum analyzer. With the I Channel driven
with a sine wave and the Q Channel driven with a cosine wave,
the lower sideband is the single sideband output. The typical
SSB output spectrum is shown in Figure 12.
90
80
70
60
50
40
30
20
10
0
100
AMPLITUDE
dBm
CENTER = 900MHz
SPAN = 1MHz
Figure 12. Typical SSB Output Spectrum
Modulated Waveform Setup
For evaluating the AD8345 with modulated waveforms, the
setup shown in Figure 13 was used. A Rohde & Schwarz
AMIQ signal generator with differential outputs was used to
generate the baseband signals. For all measurements the input
level on each baseband input pin was 0.7 V
0.3 V peak. The
output was measured with a Rohde & Schwarz FSIQ spec-
trum/vector analyzer.
+15V MAX
COM
+25V MAX
25V MAX
HP3631
IEEE
AD8345
CHARACTERIZATION
BOARD
P1
IN
IP
QP
QN
ENBL
VOUT
LO
RFOUT
IEEE
HP8648C
IEEE
PC CONTROLLER
SPECTRUM
ANALYZER
RF I/P
IEEE
FSIQ
PC CONTROL
AMIQ
IN
IP
QP
QN
Figure 13. Test Setup for Evaluating AD8345 with Modulated
Waveforms
REV. 0
AD8345
14
CDMA IS95
For measuring ACPR, the I and Q input signals used were
generated with Pilot (Walsh Code 00), Sync (WC 32), Paging
(WC 01), and 6 Traffic (WC 08, 09, 10, 11, 12, 13) channels
active. Figure 14 shows the typical output spectrum for this
configuration.
For performing EVM, Rho, phase, and amplitude balance mea-
surements, the I and Q input signals used were generated with
only the Pilot Channel (Walsh Code 00) active.
90
80
70
60
50
40
30
20
10
100
110
AMPLITUDE
dBm
CENTER = 880MHz
SPAN = 7.5MHz
CH PWR = 12.41dBm
ACP UP = 72.8dB
ACP LOW = 72.8dB
Figure 14. Typical IS95 Output Spectrum
WCDMA 3GPP
For evaluating the AD8345 for WCDMA, the 3GPP standard
was used with a Chip Rate of 3.84 MHz. The plot in Figure 15
is an ACPR plot of the AD8345 using "Test Model 1" from the
3GPP specification with 64 channels active.
90
80
70
60
50
40
30
20
10
100
110
AMPLITUDE
dBm
CENTER = 380MHz
SPAN = 14.7MHz
CH PWR = 10.95dBm
ACP UP = 52.51dB
ACP LOW = 52.41dB
Figure 15. Typical AD8345 WCDMA 3GPP Output Spectrum
GSM
For comparing the AD8345 output to the GSM transmit mask I
and Q signals were generated using MSK modulation, GSM
differential coding, a Gaussian filter and a symbol rate of
270.833 kHz. The transmit mask was manually generated on
the FSIQ using the GSM BTS specification for reference. The
plot in Figure 16 shows that the AD8345 meets the GSM trans-
mit mask requirements.
90
80
70
60
50
40
30
20
10
100
0
AMPLITUDE
dBm
CENTER = 900MHz
SPAN = 1MHz
Figure 16. Typical AD8345 GSM Output Spectrum
REV. 0
AD8345
15
16-Lead HTSSOP with Exposed Pad
(RE-16)
16
9
8
1
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
0.201 (5.10)
0.193 (4.90)
0.118 (3.0)
SQ
EXPOSED
PAD
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433 (1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16
C009321.57/01(0)
PRINTED IN U.S.A.
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