Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- PIN CONFIGURATIONS
- TABLE OF CONTENTS
-
-
-
-
-
-
Low Power, High Output Current, Quad Op Amp,
Dual-Channel ADSL/ADSL2+ Line Driver
AD8392
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
Four current feedback, high current amplifiers
Ideal for use as ADSL/ADSL2+ dual-channel Central Office
(CO) line drivers
Low power operation
Power supply operation from 5 V (+10 V) up to 12 V (+24 V)
Less than 3 mA/Amp quiescent supply current for full
power ADSL/ADSL2+ CO applications (20.4 dBm line
power, 5.5 CF)
Three active power modes plus shutdown
High output voltage and current drive
400 mA peak output drive current
44 V p-p differential output voltage
Low distortion
-72 dBc @1 MHz second harmonic
-82 dBc @ 1 MHz third harmonic
High speed: 900 V/s differential slew rate
Additional functionality of AD8392ACP
On-chip common-mode voltage generation
APPLICATIONS
ADSL/ADSL2+ CO line drivers
XDSL line drives
High output current, low distortion amplifiers
DAC output buffer
GENERAL DESCRIPTION
The AD8392 is comprised of four high output current, low
power consumption, operational amplifiers. It is particularly
well suited for the CO driver interface in digital subscriber line
systems, such as ADSL and ADSL2+. The driver is capable of
providing enough power to deliver 20.4 dBm to a line, while
compensating for losses due to hybrid insertion and back
termination resistors. In addition, the low distortion, fast slew
rate, and high output current capability make the AD8392 ideal
for many other applications, including medical, instrumenta-
tion, DAC output drivers, and other high peak current circuits.
The AD8392 is available in two thermally enhanced packages, a
28-lead TSSOP EP (AD8392ARE) and a 5 mm 5 mm 32-lead
LFCSP (AD8392ACP). Four bias modes are available via the use
of two digital bits (PD1, PD0).
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC = NO CONNECT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AD8392
PD0 1, 2
PD1 1, 2
+V
IN
1
NC
V
OUT
1
V
IN
1
V
EE
1, 2
NC
NC
+V
IN
2
NC
V
OUT
2
V
IN
2
V
OUT
3
V
IN
3
+V
IN
3
GND
NC
NC
V
CC
3, 4
V
IN
4
+V
IN
4
V
EE
3, 4
PD0 3, 4
PD1 3, 4
GND
V
CC
1, 2
V
OUT
4
04802-0-001
1
3
2
4
Figure 1. AD8392ARE, 28-Lead TSSOP/EP
1
2
3
4
5
6
7
8
9
10 11 12 13 14
24
23
22
21
20
19
18
17
16
15
32 31 30 29 28 27
25
26
AD8392
+V
IN
1
NC
V
OUT
1
V
IN
1
V
EE
1, 2
NC
+V
IN
2
NC
V
OUT
2
V
IN
2
V
OUT
3
V
IN
3
+V
IN
3
GND
NC
V
CC
3, 4
V
IN
4
+V
IN
4
V
EE
3, 4
PD
0 3, 4
GND
V
CC
1, 2
V
OUT
4
NC
NC
NC
NC
V
COM
3, 4
PD
1 3, 4
V
COM
1, 2
PD
1 1, 2
PD
0 1, 2
04802-0-002
1
3
2
4
Figure 2. AD8392ACP, 32-Lead LFCSP 5 mm 5 mm
Additionally, the AD8392ACP provides V
COM
pins for on-chip
common mode voltage generation.
The low power consumption, high output current, high output
voltage swing, and robust thermal packaging enable the AD8392
to be used as the CO line drivers in ADSL and other xDSL sys-
tems, as well as other high current, single-ended or differential
amplifier applications.
AD8392
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 11
Applications..................................................................................... 12
Supplies, Grounding, and Layout ............................................. 12
Resistor Selection........................................................................ 12
Power Management ................................................................... 12
Driving Capacitive Loads.......................................................... 12
Thermal Considerations............................................................ 13
Typical ADSL/ADSL2+ Application ........................................ 13
Multitone Power Ratio............................................................... 14
Lightning and AC Power Fault ................................................. 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
7/04--Revision 0: Initial Version
AD8392
Rev. 0 | Page 3 of 16
SPECIFICATIONS
V
S
= 12 V or +24 V, R
L
= 100 , G = +5, PD = (0, 0), T = 25C, unless otherwise noted.
Table 1.
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
DYNAMIC
PERFORMANCE
-3 dB Small Signal Bandwidth
30
40
MHz
V
OUT
= 0.1 V p-p, R
F
= 2 k
-3 dB Large Signal Bandwidth
20
25
MHz
V
OUT
= 4 V p-p, R
F
= 2 k
Peaking
0.05
dB
V
OUT
= 0.1 V p-p, R
F
= 2 k
Slew
Rate
850 900
V/s
V
OUT
= 20 V p-p, R
F
= 2 k
NOISE/DISTORTION
PERFORMANCE
Second Harmonic Distortion
-72
dBc
f
C
= 1 MHz, V
OUT
= 2 V p-p
Third Harmonic Distortion
-82
dBc
f
C
= 1 MHz, V
OUT
= 2 V p-p
Multitone Input Power Ratio
-70
dBc
26 kHz to 2.2 MHz, Z
LINE
= 100 Differential Load
Voltage Noise (RTI)
4.3
nV/Hz
f = 10 kHz
+Input Current Noise
10
pA/Hz
f = 10 kHz
-Input Current Noise
13
pA/Hz
f = 10 kHz
INPUT
CHARACTERISTICS
RTI Offset Voltage
-5.0
3.0
+5.0
mV
V
+IN
- V
-IN
+Input Bias Current
5.0
10.0
A
-Input Bias Current
10.0
15.0
A
Input Resistance
400
k
Input Capacitance
2.0
pF
Common-Mode Rejection Ratio
64
68
dB
(V
OS, DM (RTI)
)/(V
IN, CM
)
OUTPUT
CHARACTERISTICS
Differential Output Voltage Swing
42.0
44.0
46.0
V
V
OUT
Single-Ended Output Voltage Swing
21.0
22.0
23.0
V
V
OUT
Linear Output Current
400
mA
R
L
= 10 , f
C
= 100 kHz
POWER
SUPPLY
Operating Range (Dual Supply)
5
12
V
Operating Range (Single Supply)
10
24
V
Total
Quiescent
Current
PD1, PD0 = (0, 0)
6.0
7.0
mA/Amp
PD1, PD0 = (0, 1)
3.6
4.0
mA/Amp
PD1, PD0 = (1, 0)
2.8
3.3
mA/Amp
PD1, PD0 = (1, 1) (Shutdown State)
0.4
1.2
mA/Amp
PD = 0 Threshold
0.8
V
PD = 1 Threshold
1.8
V
+Power Supply Rejection Ratio
64
68
dB
V
OS, DM (RTI)
/V
CC
, V
CC
= 1 V
-Power Supply Rejection Ratio
76
79
dB
V
OS, DM (RTI)
/V
EE
, V
EE
= 1 V
AD8392
Rev. 0 | Page 4 of 16
V
S
= 5 V or +10 V, R
L
= 100 , G = +5, PD = (0, 0), T = 25C, unless otherwise noted.
Table 2.
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
DYNAMIC
PERFORMANCE
-3 dB Small Signal Bandwidth
30
40
MHz
V
OUT
= 0.1 V p-p, R
F
= 2 k
-3 dB Large signal Bandwidth
20
25
MHz
V
OUT
= 4 V p-p, R
F
= 2 k
Peaking
0.05
dB
V
OUT
= 0.1 V p-p, R
F
= 2 k
Slew Rate (Rise)
300
350
V/s
V
OUT
= 7 V p-p, R
F
= 2 k
Slew Rate (Fall)
400
450
V/s
V
OUT
= 7 V p-p, R
F
= 2 k
NOISE/DISTORTION
PERFORMANCE
Second Harmonic Distortion
-72
dBc
f
C
= 1 MHz, V
OUT
= 2 V p-p
Third Harmonic Distortion
-82
dBc
f
C
= 1 MHz, V
OUT
= 2 V p-p
Voltage Noise (RTI)
4.3
nV/Hz
f = 10 kHz
+Input Current Noise
10
pA/Hz
f = 10 kHz
-Input Current Noise
13
pA/Hz
f = 10 kHz
INPUT
CHARACTERISTICS
RTI Offset Voltage
-5.0
3.0
+5.0
mV
V
+IN
- V
-IN
+Input Bias Current
5.0
10.0
A
-Input Bias Current
10.0
15.0
A
Input Resistance
400
k
Input Capacitance
2.0
pF
Common-Mode Rejection Ratio
62
66
dB
(V
OS, DM (RTI)
)/(V
IN, CM
)
OUTPUT
CHARACTERISTICS
Differential Output Voltage Swing
14.0
16.0
18.0
V
V
OUT
Single-Ended Output Voltage Swing
7.0
8.0
9.0
V
V
OUT
Linear Output Current
400
mA
R
L
= 10 , f
C
= 100 kHz
POWER
SUPPLY
Operating Range (Dual Supply)
5
12
V
Operating Range (Single Supply)
+10
+24
V
Total
Quiescent
Current
PD1, PD0 = (0, 0)
5.4
6.0
mA/Amp
PD1, PD0 = (0, 1)
3.5
4.0
mA/Amp
PD1, PD0 = (1, 0)
2.6
3.0
mA/Amp
PD1, PD0 = (1, 1) (Shutdown State)
0.4
1.0
mA/Amp
PD = 0 Threshold
0.8
V
PD = 1 Threshold
1.8
V
+Power Supply Rejection Ratio
72
76
dB
V
OS, DM (RTI)
/V
CC
, V
CC
= 1 V
-Power Supply Rejection Ratio
64
68
dB
V
OS, DM (RTI)
/V
EE
, V
EE
= 1 V
AD8392
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage
13 V (+26 V)
Power Dissipation
See Figure 3
Storage Temperature
-65C to +150C
Operating Temperature Range
-40C to +85C
Lead Temperature Range (Soldering 10 sec)
300C
Junction Temperature
150C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
JA
is specified for the worst-case conditions, i.e.,
JA
is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
JA
Unit
LFCSP-32 (CP)
27.27
C/W
TSSOP-28/EP (RE)
35.33
C/W
Maximum Power Dissipation
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). Assuming that the load (R
L
) is midsupply,
the total drive power is V
S
/2 I
OUT
, some of which is
dissipated in the package and some in the load (V
OUT
I
OUT
).
RMS output voltages should be considered. If R
L
is referenced
to V
S-
as in single-supply operation, the total power is V
S
I
OUT
.
In single supply with R
L
to V
S-
, worst case is V
OUT
= V
S
/2.
Airflow increases heat dissipation, effectively reducing
JA
. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the
JA
.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the LFCSP-32 and
TSSOP-28/EP packages on a JEDEC standard 4-layer board.
JA
values are approximations.
0
1
2
3
4
5
6
7
40 30 20 10
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (
C)
M
A
XIM
U
M
POW
E
R
D
I
SSIPA
TION
(
W
)
T
J
= 150
C
04802-0-003
LFCSP-32
TSSOP-28/EP
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
See the Thermal Considerations section for additional thermal
design guidance.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
AD8392
Rev. 0 | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
PD (0, 0)
PD (0, 1)
OUTPUT POWER (dBm)
MULTITONE
P
O
WE
R RATIO (dBc
)
15
70
55
50
45
16
18
21
65
60
20
19
17
PD (1, 0)
CREST FACTOR = 5.45
04802-0-004
Figure 4. MTPR vs. Output Power (1.75 MHz Empty Bin)
ADSL/ADSL2+ Circuit (Figure 32)
V
S
= 12 V, R
LOAD
= 100 , CF = 5.45
04802-0-005
100
90
80
70
60
50
0.1
1
10
FREQUENCY (MHz)
HARMONIC DIS
T
ORTION (dBc
)
HD3 PD (0, 1)
HD2 PD (0, 0)
HD2 PD (0, 1)
HD3 PD (0, 0)
HD3 PD (1, 0)
HD2 PD (1, 0)
Figure 5. Harmonic Distortion vs. Frequency
Dual Differential Driver Circuit (Figure 30)
V
S
= 12 V, R
LOAD
= 100 , G = +5, V
OUT
= 2 V p-p
FREQUENCY (MHz)
HARMONIC DIS
T
ORTION (dBc
)
0.1
120
80
70
50
1
1
110
90
04802-0-006
100
60
0
HD2 PD (1, 0)
HD2 PD (0, 1)
HD3 PD (0, 0)
HD3 PD (0, 1)
HD2 PD (0, 0)
HD3 PD (1, 0)
Figure 6. Harmonic Distortion vs. Frequency
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, R
LOAD
= 100 , G = +5, V
OUT
= 2 V p-p
OUTPUT POWER (dBm)
P
O
WE
R CONS
UMP
T
ION (mW)
04802-0-007
550
600
650
700
750
800
850
900
950
15
16
17
18
19
20
21
PD (0, 0)
PD (1, 0)
PD (0, 1)
CREST FACTOR = 5.45
Figure 7. Power Consumption vs. Output Power (26 kHz to 2.2 MHz)
ADSL/ADSL2+ Circuit (Figure 32)
V
S
= 12 V, R
LOAD
= 100 , CF = 5.45
04802-0-008
100
90
80
70
60
50
0.1
1
10
FREQUENCY (MHz)
HARMONIC DIS
T
ORTION (dBc
)
HD3 PD (0, 0)
HD2 PD (0, 0)
HD2 PD (0, 1)
HD2 PD (1, 0)
HD3 PD (1, 0)
HD3 PD (0, 1)
Figure 8. Harmonic Distortion vs. Frequency
Dual Differential Driver Circuit (Figure 30)
V
S
= 5 V, R
LOAD
= 100 , G = +5, V
OUT
= 2 V p-p
FREQUENCY (MHz)
HARMONIC DIS
T
ORTION (dBc
)
0.1
120
80
70
50
1
1
110
90
04802-0-009
100
60
0
HD2 PD (1, 0)
HD2 PD (0, 1)
HD3 PD (0, 0)
HD3 PD (0, 1)
HD2 PD (0, 0)
HD3 PD (1, 0)
Figure 9. Harmonic Distortion vs. Frequency
Quad Op Amp Circuit (Figure 29)
V
S
= 5 V, R
LOAD
= 100 , G = +5, V
OUT
= 2 V p-p
AD8392
Rev. 0 | Page 7 of 16
04802-0-010
PD (0, 1)
PD (0, 0)
PD (1, 0)
20
15
10
5
5
10
15
0.1
1
10
100
1000
FREQUENCY (MHz)
GAIN (
d
B)
0
Figure 10. Small Signal Frequency Response
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, R
LOAD
= 100 , G = +5, V
OUT
= 100 mV p-p
20
15
10
5
0
5
10
15
0.1
1
10
100
1000
FREQUENCY (MHz)
04802-0-011
GAIN (
d
B)
100
75
50
25
1
4.7
10
Figure 11. Small Signal Frequency Response vs. Load
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, G = +5, V
OUT
= 100 mV p-p
04802-0-012
PD (0, 1)
PD (0, 0)
20
15
10
5
5
10
15
0.1
1
10
100
1000
FREQUENCY (MHz)
GAIN (
d
B)
0
PD (1, 0)
Figure 12. Large Signal Frequency Response
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, R
LOAD
= 100 , G = +5, V
OUT
= 4 V p-p
04802-0-013
PD (0, 1)
PD (0, 0)
PD (1, 0)
20
15
10
5
5
10
15
0.1
1
10
100
1000
FREQUENCY (MHz)
GA
IN
(
d
B
)
0
Figure 13. Small Signal Frequency Response
Quad Op Amp Circuit (Figure 29)
V
S
= 5 V, R
LOAD
= 100 , G = +5, V
OUT
= 100 mV p-p
FREQUENCY (MHz)
S
I
GNAL FE
E
D
THROUGH (dB)
0.1
1
1000
04802-0-014
100
90
80
70
60
50
40
30
20
10
0
10
100
Figure 14. Signal Feedthrough vs. Frequency
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, G = +5, V
IN
= 800 mV p-p, PD (1, 1)
04802-0-015
PD (0, 1)
PD (0, 0)
20
15
10
5
5
10
15
0.1
1
10
100
1000
FREQUENCY (MHz)
GAIN (
d
B)
0
PD (1, 0)
Figure 15. Large Signal Frequency Response
Quad Op Amp Circuit (Figure 29)
V
S
= 5 V, R
LOAD
= 100 , G = +5, V
OUT
= 4 V p-p
AD8392
Rev. 0 | Page 8 of 16
10
8
6
4
2
0
2
4
6
8
10
TIME (
s)
04802-0-016
0.06
0.04
0.02
0
0.02
0.04
0.06
OUTPUT VOLTAGE (V)
Figure 16. Small Signal Pulse Response
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, R
LOAD
= 100 , G = +5, 100 mV Step
004802-0-017
CH1
200mV
CH2 1.00mV
M 50.0ns
A CH2 2.38V
2
1
B
W
B
W
OUTPUT
PD PINS
Figure 17. Power-Up Time: PD (1, 1) to PD (0, 0)
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, R
LOAD
= 100 , G = +5, V
OUT
= 1 V p-p
004802-0-018
CH1
5.00V
CH2 5.00V
M1.00
s
CH1 700mV
2
1
OUTPUT
INPUT
: 460ns
@: 1.32
s
C2 p-p
21.4V
C1 p-p
27.0V
Figure 18. Input Overdrive Recovery
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, R
LOAD
= 100 , G = +1, V
IN
= 27 V p-p
10
8
6
4
2
0
2
4
6
8
10
TIME (
s)
04802-0-019
OUTPUT VOLTAGE (V)
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
Figure 19. Large Signal Pulse Response
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, R
LOAD
= 100 , G = +5, 4 V Step
004802-0-020
CH1
200mV
B
W
CH2 1.00V
B
W
M 400ns
CH2 2.38V
2
1
OUTPUT
PD PINS
Figure 20. Power-Down Time: PD (0, 0) to PD (1, 1)
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, R
LOAD
= 100 , G = +5, V
OUT
= 1 V p-p
004802-0-021
CH1
1.00V
CH2 5.00V
M1.00
s
CH1 800mV
2
1
OUTPUT
INPUT
: 420ns
@: 2.84
s
C2 p-p
21.8V
C1 p-p
6.00V
Figure 21. Output Overdrive Recovery
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, R
LOAD
= 100 , G = +5, V
IN
= 6 V p-p
AD8392
Rev. 0 | Page 9 of 16
70
60
50
40
30
20
10
FREQUENCY (MHz)
CROS
S
T
ALK (dB)
0.1
90
0
10
100
1
04802-0-022
80
ADSL CHANNEL 3, 4
ADSL CHANNEL 1, 2
Figure 22. Crosstalk vs. Frequency
ADSL/ADSL2+ Circuit (Figure 32)
V
S
= 12 V, G = +11, R
LOAD
= 100 , V
IN
= 200 mV p-p
70
60
50
40
30
20
10
FREQUENCY (MHz)
CROS
S
T
ALK (dB)
0.1
90
0
10
100
1
04802-0-023
80
CHANNEL 1
CHANNEL 4
CHANNEL 2
CHANNEL 3
Figure 23. Crosstalk vs. Frequency
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, G = +5, R
LOAD
= 100 , V
IN
=
200 mV p-p
04802-0-024
VOLTA
G
E N
O
ISE (
n
V/ H
z
)
1
10
100
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
Figure 24. Voltage Noise vs. Frequency
70
60
50
40
30
20
10
FREQUENCY (MHz)
CROS
S
T
ALK (dB)
0.1
90
0
10
100
1
04802-0-025
80
DIFF CHANNEL 3, 4
DIFF CHANNEL 1, 2
Figure 25. Crosstalk vs. Frequency
Dual Differential Driver Circuit (Figure 30)
V
S
= 12 V, G = +5, R
LOAD
= 100 , V
IN
= 200 mV p-p
10
15
20
25
30
35
40
45
90
10
20
30
40
50
60
70
80
100
RESISTIVE LOAD (
)
DIFFE
RE
NTIAL OUTP
UT S
W
ING (V
)
04802-0-026
V
S
= 12V
V
S
= 5V
Figure 26. Differential Output Swing vs. R
LOAD
ADSL/ADSL2+ Circuit (Figure 32)
G = +11
04802-0-027
CURRE
NT NOIS
E
(pA/ Hz)
1
100
10
1000
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
I
NOISE
+I
NOISE
Figure 27. Current Noise vs. Frequency
AD8392
Rev. 0 | Page 10 of 16
04802-0-028
1G
0.0001
100M
10M
1M
100k
10k
1k
100
10
1
0.1
0.01
0.001
TRANSIMPEDANCE
PHASE
FREQUENCY (Hz)
100
1G
100M
10M
1M
100k
10k
1k
TRANS
IMP
E
DANCE
(
)
180
80
160
140
120
100
80
60
40
20
0
20
40
60
PH
A
SE (
D
egrees)
Figure 28. Open-Loop Transimpedance and Phase
04802-0-033
100nF
49.9
2k
100
499
Figure 29. Quad Op Amp Circuit
04802-0-030
100nF
49.9
100nF
49.9
1k
2k
2k
100
Figure 30. Dual Differential Driver Circuit
04802-0-031
100
0.01
10
1
0.1
FREQUENCY (MHz)
0.01
1000
100
10
0.1
PD (1, 0)
PD (0, 1)
PD (0, 0)
OUTP
UT IMP
E
DANCE
(
)
1
Figure 31. Output Impedance vs. Frequency
Quad Op Amp Circuit (Figure 29)
V
S
= 12 V, G = +5, PD (0, 0)
04802-0-032
100nF
866
100nF
866
162
162
280k
280k
6.19
2k
100nF
226
2k
6.19
100
V
CM
Figure 32. ADSL/ADSL2+ Circuit
AD8392
Rev. 0 | Page 11 of 16
THEORY OF OPERATION
The AD8392 is a current feedback amplifier with high (400 mA)
output current capability. With a current feedback amplifier, the
current into the inverting input is the feedback signal, and the
open-loop behavior is that of a transimpedance, dV
O
/dI
IN
or T
Z
.
The open-loop transimpedance is analogous to the open-loop
voltage gain of a voltage feedback amplifier. Figure 33 shows a
simplified model of a current feedback amplifier. Since R
IN
is
proportional to 1/g
m
, the equivalent voltage gain is just T
Z
g
m
,
where g
m
is the transconductance of the input stage. Basic
analysis of the follower with gain circuit yields
( )
( )
F
IN
Z
Z
IN
O
R
R
G
S
T
S
T
G
V
V
+
+
=
where:
G
F
R
R
G
+
= 1
50
1
=
m
IN
g
R
Since G R
IN
<< R
F
for low gains, a current feedback amplifier
has relatively constant bandwidth versus gain, the 3 dB point
being set when |T
Z
| = R
F
.
Of course, for a real amplifier there are additional poles that
contribute excess phase, and there is a value for R
F
below which
the amplifier is unstable. Tolerance for peaking and desired
flatness determines the optimum R
F
in each application.
04802-0-034
R
F
V
OUT
R
G
R
N
V
IN
R
IN
I
IN
T
Z
Figure 33. Simplified Block Diagram
The AD8392 is capable of delivering 400 mA of output current
while swinging to within 2 V of either power supply rail. The
AD8392 also has a power management system included on-chip.
It features four user-programmable power levels (three active
power modes as well as the provision for complete shutdown).
AD8392
Rev. 0 | Page 12 of 16
APPLICATIONS
SUPPLIES, GROUNDING, AND LAYOUT
The AD8392 can be powered from either single or dual supplies,
with the total supply voltage ranging from 10 V to 24 V. For
optimum performance, a well regulated low ripple supply
should be used.
As with all high speed amplifiers, close attention should be paid
to supply decoupling, grounding, and overall board layout. Low
frequency supply decoupling should be provided with 10 F
tantalum capacitors from each supply to ground. In addition, all
supply pins should be decoupled with 0.1 F quality ceramic
chip capacitors placed as close as possible to the driver. An
internal low impedance ground plane should be used to provide
a common ground point for all driver and decoupling capacitor
ground requirements. Whenever possible, separate ground
planes should be used for analog and digital circuitry.
High speed layout techniques should be followed to minimize
parasitic capacitance around the inverting inputs. Some practi-
cal examples of these techniques are keeping feedback traces as
short as possible and clearing away ground plane in the area of
the inverting inputs. Input and output traces should be kept
short and as far apart from each other as practical to avoid
crosstalk. When used as a differential driver, all differential
signal traces should be kept as symmetrical as possible.
RESISTOR SELECTION
In current feedback amplifiers, selection of feedback and gain
resistors can impact harmonic distortion performance, band-
width, and gain flatness. Care should be exercised in the selec-
tion of these resistors so that optimum performance is achieved.
Table 5 shows some suggested resistor values for use in a variety
of gain settings. These values are suggested as a good starting
point when designing for any application.
Table 5. Resistor Selection Guide
Gain R
F
R
G
1 2.0k
Open
2 1.5k
1.5k
5 1.0k
249
10 750
82.5
POWER MANAGEMENT
The AD8392 can be configured in any of three active bias states
as well as a shutdown state via the use of two sets of digitally
programmable logic pins. Pins PD(0, 1) 1, 2 control Amplifiers 1
and 2, while PD(0, 1) 3, 4 control Amplifiers 3 and 4. These pins
can be controlled directly with either 3.3 V or 5 V CMOS logic
by using the GND pins as a reference. If left unconnected, the
PD pins float low, placing the amplifier in the full bias mode.
Refer to the Specifications for the per amplifier quiescent cur-
rent for each of the available bias states.
The AD8392 exhibits low output impedance for the three active
states. However, the output impedance in the shutdown state
(PD1, 0 = 1, 1) is undefined.
DRIVING CAPACITIVE LOADS
When driving a capacitive load, most op amps exhibit peaking
in their frequency response. In general, to minimize peaking or
to ensure device stability for larger values of capacitive loads, a
small series resistor can be added between the op amp output
and the load capacitor. Figure 34 shows the frequency response
of the AD8392 for various capacitive loads without any series
resistance. In this condition, the maximum recommended
capacitive load is around 20 pF. As shown in Figure 35, the
addition of a 5.1 series resistor limits peaking to approxi-
mately 3 dB when driving capacitive loads up to 100 pF.
04802-0-034
GAIN (
d
B)
15
10
20
0.1
1
10
100
1000
FREQUENCY (MHz)
10
5
0
5
15
2k
V
IN
499
50
1k
C
L
10pF
15pF
20pF
Figure 34. AD8392 Capacitive Load Frequency Response
without Series Resistance
04802-0-035
GAIN (
d
B)
15
10
20
0.1
1
10
100
1000
FREQUENCY (MHz)
10
5
0
5
15
2k
V
IN
499
50
1k
C
L
22pF
47pF
100pF
5.1
Figure 35. AD8392 Capacitive Load Frequency Response
with Series Resistance
AD8392
Rev. 0 | Page 13 of 16
THERMAL CONSIDERATIONS
When using a quad, high output current amplifier, such as the
AD8392, special consideration should be given to system level
thermal design. In applications such as ADSL/ADSL2+, the
AD8392 could be required to dissipate as much as 1.4 W or
more on chip. Under these conditions, particular attention
should be paid to the thermal design in order to maintain safe
operating temperatures on the die. To aid in the thermal design,
the thermal information in the Thermal Resistance section can
be combined with what follows here.
The information in Table 4 and Figure 3 is based on a standard
JEDEC 4-layer board and a maximum die temperature of
150C. To provide additional guidance and design suggestions, a
thermal study was performed under a set of conditions more
closely aligned with an actual ADSL/ADSL2+ application.
In a typical ADSL/ADSL2+ line card, component density usu-
ally dictates that most of the copper plane used for thermal
dissipation be internal. Additionally, each ADSL/ADSL2+ port
may be allotted only 1 square inch, or even less, of board space.
For these reasons, a special thermal test board was constructed
for this study. The 4-layer board measured approximately
4 inches 4 inches and contained two internal 1 oz copper
ground planes, each measuring 2 inches 3 inches. The top
layer contained signal traces and an exposed copper strip
inch 3 inches to accommodate heat sinking, with no other
copper on the top or bottom of the board.
Three 28-lead TSSOPs were placed on the board representing
six ADSL channels, or one channel per square inch of copper,
with each channel dissipating 700 mW on-chip (1.4 W per
package). The die temperature is then measured in still air and
in a wind tunnel with calibrated airflow of 100 LFM, 200 LFM,
and 400 LFM. Figure 36 shows the power dissipation versus the
ambient temperature for each airflow condition. The figure
assumes a maximum die temperature of 135C. No heat sink
was used.
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5
15
25
35
45
55
65
75
85
AMBIENT TEMPERATURE (
C)
POWER
D
I
SSIPA
TION
(
W
)
T
J
= 135
C
04802-0-036
STILL AIR
100LFM
200LFM
400LFM
Figure 36. Power Dissipation vs. Ambient
Temperature and Air Flow 28-Lead TSSOP/EP
This data is only provided as guidance to assist in the thermal
design process. Due diligence should be performed with regards
to power dissipation because there are many factors that can
affect thermal performance.
TYPICAL ADSL/ADSL2+ APPLICATION
In a typical ADSL/ADSL2+ application, a differential line driver
is used to take the signal from the analog front end (AFE) and
drive it onto the twisted pair telephone line. Referring to the
typical circuit representation in Figure 37, the differential input
appears at V
IN+
and V
IN-
from the AFE, while the differential
output is transformer coupled to the telephone line at tip and
ring. The common-mode operating point, generally midway
between the supplies, is set through V
COM
.
04802-0-037
R4
R4
R3
R3
R
m
R2
R1
R2
V
COM
1:N
TIP
RING
R
OUT
R
IN
R
m
V
OA
V
OA
V
P
V
P
R
BIAS
R
BIAS
V
IN
V
IN+
Figure 37. Typical ADSL/ADSL2+ Application Circuit
In ADSL/ADSL2+ applications, it is common practice to
conserve power by using positive feedback to synthesize the
output resistance, thereby lowering the required ohmic value of
the line matching resistors, R
m
. The circuit in Figure 37 is
somewhat unique in that the positive feedback introduced via
R3 has the effect of synthesizing the input resistance as well.
The following definitions and equations can be used to calculate
the resistor values necessary to obtain the desired gain, input
resistance, and output resistance for a given application. For
simplicity the following calculations assume a lossless
transformer.
The following values are used in the design equations and are
assumed already known or chosen by the designer.
V
IN
Differential input voltage
R
IN
Desired differential input resistance
N
Transformer turns ratio
V
LINE
Differential output voltage at tip and ring
R
m
Each is typically 5% to 15% of the transformer reflected
line impedance
R2
Recommended in the amplifier data sheet
V
P
Voltage at the + inputs to the amplifier, approximately
V
IN
(must be less than V
IN
for positive input resistance)
R
L
Transformer reflected line impedance
AD8392
Rev. 0 | Page 14 of 16
Additional definitions for calculating resistor values include:
V
OA
Voltage at the amplifier outputs
k
Matching resistance reduction factor
A
V
Gain from V
IN
to transformer primary
Negative feedback factor
Positive feedback factor
Note: R1 must be calculated before
and .
(
)
N
k
V
V
LINE
OA
+
=
1
L
m
R
R
k
2
=
IN
LINE
V
V
N
V
A =
R2
R1
R1
2
+
=
(
)
k
-
= 1
With the above known quantities and definitions, the remaining
resistors can readily be calculated.
P
OA
P
V
V
R
V
R1
-
=
2
2
(
)
IN
P
IN
IN
V
2
V
V
R
R4
-
=
(
)
(
)
R2
R1
R
R
R2
R
R1
R
R1
R
R1
R4
A
R3
L
L
L
L
m
V
2
2
2
+
-
-
+
=
(
)
R4
R3
R4
R4
R3
R
BIAS
+
-
=
After building the circuit with the closest 1% resistor values,
the actual gain, input resistance, and output resistance can be
verified with the following equations.
(
)
(
)
R3
R4
R
R4
R3
R4
k
N
GAIN
BIAS
LINE
to
V
IN
-
+
+
+
=
1
1
+
-
=
L
L
m
V
IN
R
R4
R
R
A
R4
R
2
1
2
(
)
+
+
+
+
-
=
BIAS
BIAS
BIAS
BIAS
m
OUT
R
R4
R
R4
R3
R2
R1
R
R4
R1
R
R4
N
R
R
2
1
2
2
MULTITONE POWER RATIO
The DMT signal used in ADSL/ADSL2+ systems carries data in
discrete tones or bins, which appear in the frequency domain in
evenly spaced 4.3125 kHz intervals. In applications using this
type of waveform, multitone power ratio (MTPR) is a com-
monly used measure of linearity. Generally, there are two types
of MTPR that designers are typically concerned with: in-band
and out-of-band MTPR. In-band MTPR is defined as the
measured difference from the peak of one tone that is loaded
with data to the peak of an adjacent tone that is intentionally
left empty. Out-of-band MTPR is more loosely defined as the
spurious emissions that occur in the receive band located
between 25.875 kHz and the first downstream tone at 138 kHz.
Figure 38 and Figure 39 show the AD8392 in-band MTPR for a
5.5 crest factor waveform for empty bins in the ADSL and
extended ADSL2+ bandwidths. Figure 40 shows the AD8392
out-of-band MTPR for the same waveform.
CENTER 647kHz
04802-0-038
120
110
100
90
80
70
60
50
40
30
20
SPAN 10kHz
1kHz/
72.2dB
Figure 38. In-Band MTPR at 647 kHz
CENTER 1.75MHz
04802-0-039
120
110
100
90
80
70
60
50
40
30
20
SPAN 10kHz
1kHz/
64.4dB
Figure 39. In-Band MTPR at 1.751 MHz
AD8392
Rev. 0 | Page 15 of 16
START 3kHz
04802-
0-
040
120
110
100
90
80
70
60
50
40
30
20
STOP 145kHz
14.2kHz/
LIGHTNING AND AC POWER FAULT
The AD8392 can be used is as an ADSL/ADSL2+ line driver. In
this application, the line driver is transformer-coupled to the
twisted pair telephone line and could be subjected to large line
transients resulting from events such as lightning strikes or
downed power lines. In this type of environment, additional
circuitry may be required to protect the AD8392 from damage
that may occur as a result of these events. Using a minimal
amount of external protection, the AD8392 has successfully
passed overvoltage and overcurrent compliance testing per the
ITU K-20 specification. For details on the external protection
circuitry, contact the high current driver product line at
high_current_drivers.com@analog.com
.
Figure 40. Out-of-Band MTPR
AD8392
Rev. 0 | Page 16 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153AET
1.05
1.00
0.80
SEATING
PLANE
1.20
MAX
0.15
0.00
0.30
0.19
4.50
4.40
4.30
28
15
14
1
9.80
9.70
9.60
PIN 1
6.40
BSC
0.65
BSC
0.20
0.09
8
0
EXPOSED
PAD
(Pins Down)
3.00
BSC
3.50
BSC
BOTTOM VIEW
0.75
0.60
0.45
Figure 41. 28-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP/EP]
(RE-28-1)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12 MAX
1.00
0.85
0.80
SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
BOTTOM
VIEW
0.50
0.40
0.30
3.50 REF
0.50
BSC
3.25
3.10 SQ
2.95
0.60 MAX
0.60 MAX
0.25 MIN
TOP
VIEW
PIN 1
INDICATOR
PIN 1
INDICATOR
5.00
BSC SQ
4.75
BSC SQ
Figure 42. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm 5 mm Body (CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Outline
AD8392ARE
-40C to +85C
28-Lead Thin Shrink Small Outline Package (TSSOP)
RE-28-1
AD8392ARE-REEL
-40C to +85C
28-Lead Thin Shrink Small Outline Package (TSSOP)
RE-28-1
AD8392ARE-REEL7
-40C to +85C
28-Lead Thin Shrink Small Outline Package (TSSOP)
RE-28-1
AD8392ACP-R2
-40C to +85C
32-Lead Lead Frame Chip Scale Package (LFCSP)
CP-32-2
AD8392ACP-REEL
-40C to +85C
32-Lead Lead Frame Chip Scale Package (LFCSP)
CP-32-2
AD8392ACP-REEL7
-40C to +85C
32-Lead Lead Frame Chip Scale Package (LFCSP)
CP-32-2
2004 Analog Devices, Inc. All rights reserved. Trademarks and
regis-
tered trademarks are the property of their respective owners.
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