REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD842*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
Wideband, High Output Current,
Fast Settling Op Amp
PRODUCT DESCRIPTION
The AD842 is a member of the Analog Devices family of wide
bandwidth operational amplifiers. This device is fabricated using
Analog Devices' junction isolated complementary bipolar (CB)
process. This process permits a combination of dc precision and
wideband ac performance previously unobtainable in a mono-
lithic op amp. In addition to its 80 MHz gain bandwidth, the
AD842 offers extremely fast settling characteristics, typically
settling to within 0.01% of final value in less than 100 ns for a
10 volt step.
The AD842 also offers a low quiescent current of 13 mA, a high
output current drive capability (100 mA minimum), a low input
voltage noise of 9 nV
Hz and a low input offset voltage (1 mV
maximum).
The 375 V/
s slew rate of the AD842, along with its 80 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is ideally suited for
use in high frequency signal conditioning circuits and wide
bandwidth active filters. The extremely rapid settling time of
the AD842 makes this amplifier the preferred choice for data
acquisition applications which require 12-bit accuracy. The
AD842 is also appropriate for other applications such as high
speed DAC and ADC buffer amplifiers and other wide band-
width circuitry.
APPLICATION HIGHLIGHTS
1. The high slew rate and fast settling time of the AD842 make
it ideal for DAC and ADC buffers amplifiers, lines drivers
and all types of video instrumentation circuitry.
2. The AD842 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth; performance previously
available only in hybrids.
3. Laser-wafer trimming reduces the input offset voltage of
1 mV max, thus eliminating the need for external offset
nulling in many applications.
4. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where the
circuit gain will be 2 or greater.
5. The AD842 is an enhanced replacement for the HA2542.
FEATURES
AC PERFORMANCE
Gain Bandwidth Product: 80 MHz (Gain = 2)
Fast Settling: 100 ns to 0.01% for a 10 V Step
Slew Rate: 375 V/ s
Stable at Gains of 2 or Greater
Full Power Bandwidth: 6.0 MHz for 20 V p-p
DC PERFORMANCE
Input Offset Voltage: 1 mV max
Input Offset Drift: 14 V/ C
Input Voltage Noise: 9 nV/
Hz typ
Open-Loop Gain: 90 V/mV into a 500 Load
Output Current: 100 mA min
Quiescent Supply Current: 14 mA max
APPLICATIONS
Line Drivers
DAC and ADC Buffers
Video and Pulse Amplifiers
Available in Plastic DIP, Hermetic Metal Can,
Hermetic Cerdip, SOIC and LCC Packages and in
Chip Form
MIL-STD-883B Parts Available
Available in Tape and Reel in Accordance with
EIA-481A Standard
CONNECTION DIAGRAMS
Plastic DIP (N) Package
and
Cerdip (Q) Package
TOP VIEW
14
13
12
11
10
9
8
1
2
3
4
5
6
7
NC
NC
BALANCE
INPUT
+INPUT
V
NC
NC
BALANCE
NC
V+
OUTPUT
NC
NC
NC = NO CONNECT
AD842
+
LCC (E) Package
NC
BALANCE
NC
BALANCE
NC
NC
IN
NC
+IN
NC
NC
V
S
NC
NC
NC
NC
NC
+V
S
OUTPUT
+
AD842
18
17
16
15
14
4
5
6
7
8
3
2
1
20
19
9
10
11
12
13
NC
NC = NO CONNECT
TO-8 (H) Package
NC
NC
NC
NC
NC = NO CONNECT
NC
BALANCE
INPUT
+INPUT
V
V+
OUTPUT
BALANCE
TOP VIEW
+
AD842
NOTE: CAN BE TIED TO V+
SOIC (R-16) Package
TOP VIEW
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
BALANCE
INPUT
NC
+INPUT
NC
V
S
NC
BALANCE
+V
S
NC
OUTPUT
NC
NC
NC
+
NC = NO CONNECT
AD842
NC
NC
*Covered by U.S. Patent Nos. 4,969,823 and 5,141,898.
2
REV. E
AD842SPECIFICATIONS
Model
AD842J/JR
1
AD842K
AD842S
2
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
INPUT OFFSET VOLTAGE
3
0.5
1.5
0.3
1.0
0.5
1.5
mV
T
MIN
T
MAX
2.5/3
1.5
3.5
mV
Offset Drift
14
14
14
V/C
INPUT BIAS CURRENT
4.2
8
3.5
5
4.2
8
A
T
MIN
T
MAX
10
6
12
A
Input Offset Current
0.1
0.4
0.05
0.2
0.1
0.4
A
T
MIN
T
MAX
0.5
0.3
0.6
A
INPUT CHARACTERISTICS
Differential Mode
Input Resistance
100
100
100
k
Input Capacitance
2.0
2.0
2.0
pF
INPUT VOLTAGE RANGE
Common Mode
10
10
10
V
Common-Mode Rejection
V
CM
=
10 V
86
115
90
115
86
115
dB
T
MIN
T
MAX
80
86
80
dB
INPUT VOLTAGE NOISE
f = 1 kHz
9
9
9
nV/
Hz
Wideband Noise
10 Hz to 10 MHz
28
28
28
V rms
OPEN-LOOP GAIN
V
O
=
10 V
R
LOAD
500
40/30
90
50
90
40
90
V/mV
T
MIN
T
MAX
20/15
25
20
V/mV
OUTPUT CHARACTERISTICS
Voltage
R
LOAD
500
10
10
10
V
Current
V
OUT
=
10 V
100
100
100
mA
Open Loop
5
5
5
FREQUENCY RESPONSE
Gain Bandwidth Product
V
OUT
= 90 mV
80
80
80
MHz
Full Power Bandwidth
4
V
O
= 20 V p-p
R
LOAD
500
4.7
6
4.7
6
4.7
6
MHz
Rise Time
5
A
VCL
= 2
10
10
10
ns
Overshoot
5
A
VCL
= 2
20
20
20
%
Slew Rate
5
A
VCL
= 2
300
375
300
375
300
375
V/
s
Settling Time
5
10 V Step
to 0.1%
80
80
80
ns
to 0.01%
100
100
100
ns
Differential Gain
f = 4.4 MHz
0.015
0.015
0.015
%
Differential Phase
f = 4.4 MHz
0.035
0.035
0.035
Degree
POWER SUPPLY
Rated Performance
15
15
15
V
Operating Range
5
18
5
18
5
18
V
Quiescent Current
13/14
14/16
13
14
13
14
mA
T
MIN
T
MAX
16/19.5
16
19
mA
Power Supply Rejection Ratio
V
S
=
5 V to 18 V
86
100
90
105
86
100
dB
T
MIN
T
MAX
80
86
80
dB
TEMPERATURE RANGE
Rated Performance
6
0
+75
0
+75
55
+125
C
PACKAGE OPTIONS
Plastic (N-14)
AD842JN
AD842KN
Cerdip (Q-14)
AD842JQ
AD842KQ
AD842SQ, AD842SQ/883B
SOIC (R-16)
AD842JR-16
Tape and Reel
AD842JR-16-REEL
AD842JR-16-REEL7
TO-8 (H-12A)
AD842JH
AD842KH
AD842SH
LCC (E-20A)
AD842SE/883B
Chips
AD842JCHIPS
AD842SCHIPS
NOTES
1
AD842JR specifications differ from those of the AD842JN, JQ and JH due to the thermal characteristics of the SOIC package.
2
Standard Military Drawing available 5962-8964201xx
2A (SE/883B); XA (SH/883B); CA (SQ/883B).
3
Input offset voltage specifications are guaranteed after 5 minutes at T
A
= +25
C.
4
Full power bandwidth = slew rate/2
V
PEAK
.
5
Refer to Figures 22 and 23.
6
"S" grade T
MIN
T
MAX
specifications are tested with automatic test equipment at T
A
= 55
C and T
A
= +125
C.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units.
Specifications subject to change without notice.
(@ +25 C and 15 V dc, unless otherwise noted)
AD842
3
REV. E
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Internal Power Dissipation
2
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W
TO-8 (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
LCC (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .
6 V
Storage Temperature Range
Q, H, E . . . . . . . . . . . . . . . . . . . . . . . . . . 65
C to +150C
N, R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
C to +125C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175
C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Maximum internal power dissipation is specified so that T
J
does not exceed
+150
C at an ambient temperature of +25C.
Thermal Characteristics:
JC
JA
SA
Plastic Package
30
C/W
100
C/W
Cerdip Package
30
C/W
110
C/W
38
C/W
TO-8 Package
30
C/W
100
C/W
27
C/W
16-Lead SOIC Package 30
C/W
100
C/W
20-Lead LCC Package 35
C/W
150
C/W
Recommended Heat Sink: Aavid Engineering #602B
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
AD842
4
REV. E
SUPPLY VOLTAGE Volts
INPUT COMMON-MODE RANGE
Volts
20
15
0
0
5
20
10
15
10
5
V
IN
Figure 1. Input Common-Mode
Range vs. Supply Voltage
SUPPLY VOLTAGE Volts
QUIESCENT CURRENT
mA
18
16
10
0
5
20
10
15
14
12
Figure 4. Quiescent Current vs.
Supply Voltage
TEMPERATURE C
QUIESCENT CURRENT
mA
18
15
10
60 40
140
20
0
20
40
60
80 100 120
17
16
13
11
14
12
Figure 7. Quiescent Current vs.
Temperature
Typical Characteristics
(at +25 C and V
S
= 15 V, unless otherwise noted)
SUPPLY VOLTAGE
Volts
OUTPUT VOLTAGE SWING
Volts
20
15
0
0
5
20
10
15
10
5
V
OUT
Figure 2. Output Voltage Swing
vs. Supply Voltage
TEMPERATURE C
INPUT BIAS CURRENT
A
5
4
2
60 40
140
20
0
20
40
60
80 100 120
3
Figure 5. Input Bias Current vs.
Temperature
AMBIENT TEMPERATURE C
SHORT CIRCUIT CURRENT LIMIT
mA
300
225
100
60 40
140
20
0
20
40
60
80 100 120
275
250
175
125
200
150
OUTPUT CURRENT
+ OUTPUT CURRENT
Figure 8. Short-Circuit Current
Limit vs. Temperature
LOAD RESISTANCE
OUTPUT VOLTAGE SWING
Volts p-p
30
25
0
10
100
10k
1k
20
15
5
10
15V SUPPLIES
Figure 3. Output Voltage Swing
vs. Load Resistance
FREQUENCY Hz
OUTPUT IMPEDANCE
100
10
0.01
10k
100k
100M
1M
10M
1
0.1
Figure 6. Output Impedance vs.
Frequency
TEMPERATURE C
GAIN BANDWIDTH
MHz
85
80
65
60 40
140
20
0
20
40
60
80 100 120
75
70
Figure 9. Gain Bandwidth Product
vs. Temperature
AD842
5
REV. E
FREQUENCY Hz
OPEN-LOOP GAIN
dB
120
0
100
1k
100M
10k
100k
1M
10M
100
80
60
40
20
100
80
60
40
20
0
PHASE MARGIN
Degrees
500 LOAD
Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency
FREQUENCY Hz
CMR
dB
120
100
20
1k
10k
100M
100k
1M
10M
80
60
40
V
S
= 15V
V
CM
= 1V p-p
+ 25 C
Figure 13. Common-Mode
Rejection vs. Frequency
3V RMS
R
L
= 1k
FREQUENCY Hz
HARMONIC DISTORTION
dB
80
90
140
100
1k
100k
10k
100
110
130
120
3RD HARMONIC
2ND HARMONIC
Figure 16. Harmonic Distortion vs.
Frequency
SUPPLY VOLTAGE V
OPEN-LOOP GAIN
dB
110
105
90
0
5
20
10
15
100
95
500 LOAD
Figure 11. Open-Loop Gain vs.
Supply Voltage
FREQUENCY Hz
OUTPUT VOLTAGE
Volts p-p
30
25
0
1M
10M
100M
20
15
10
5
R
L
= 1kV
+25 C
V
S
= 15V
Figure 14. Large Signal Frequency
Response
FREQUENCY Hz
INPUT VOLTAGE
nV
Hz
50
40
0
10
100
10M
1k
10k
100k
1M
30
20
10
Figure 17. Input Voltage vs.
Frequency
FREQUENCY Hz
POWER SUPPLY REJECTION
dB
120
0
100
1k
100M
10k
100k
1M
10M
100
80
60
40
20
+ SUPPLY
SUPPLY
Figure 12. Power Supply Rejection
vs. Frequency
SETTLING TIME ns
OUTPUT SWING FROM 0 TO
V
10
10
30
40
110
50
60
70
80
90
100
8
2
0
4
8
6
4
2
6
0.1%
0.1%
0.01%
0.01%
Figure 15. Output Swing and
Error vs. Settling Time
TEMPERATURE C
SLEW RATE
V
s
550
400
250
60 40
140
20
0
20 40
60
80 100 120
500
450
350
300
Figure 18.
Slew Rate vs.
Temperature
AD842
6
REV. E
2.2 F
0.1 F
+V
S
+
AD842
V
OUT
499
332
2.2 F
0.1 F
V
S
HP3314A
FUNCTION
GENERATOR
OR
EQUIVALENT
49.9
R
IN
=
499
R
F
= 1k
Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)
2.2 F
0.1 F
+V
S
+
AD842
V
OUT
499
2.2 F
0.1 F
V
S
HP3314A
FUNCTION
GENERATOR
OR
EQUIVALENT
49.9
100
R
F
= 205
V
IN
R1 = 205
Figure 20a. Noninverting Amplifier
Configuration (DIP Pinout)
Figure 19b. Inverter Large Signal
Pulse Response
Figure 20b. Noninverting Large
Signal Pulse Response
Figure 19c. Inverter Small Signal
Pulse Response
Figure 20c. Noninverting Small
Signal Pulse Response
AD842
7
REV. E
OFFSET NULLING
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
AD842 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD842
in the test circuit shown in Figure 23.
Settling time is defined as:
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
This definition encompasses the major components which com-
prise settling time. They include (1) propagation delay through
the amplifier; (2) slewing time to approach the final output value;
(3) the time of recovery from the overload associated with slew-
ing and (4) linear settling to within the specified error band.
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for the
application.
+
AD842
R
L
2.2 F
0.1 F
V
S
OUTPUT
2.2 F
0.1 F
+V
S
10k
INPUT
Figure 21. Offset Nulling (DIP Pinout)
Figure 22. 0.01% Settling Time
2.2 F
0.1 F
AD842
499
499
2.2 F
0.1 F
15V
DDD5109
FLAT-TOP
PULSE
GENERATOR
50
499
1k
499
1k
+15V
HP6263
ERROR
AMP
( 15)
TEK
7603
OSCILLOSCOPE
TEK
7A13
TEK
7A16
FET PROBE
TEK P6201
Figure 23. Settling Time Test Circuit
Figure 23 shows how measurement of the AD842's 0.01% set-
tling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high-speed propri-
etary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
300
load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp gains the
error from the false summing junction by 15, and it contains a
gain vernier to fine trim the gain.
Figure 24 shows the "long term" stability of the settling charac-
teristics of the AD842 output after a 10 V step. There is no
evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful
layout, avoids these problems by minimizing the effects of tran-
sistor isolation capacitance discharge and thermally induced
shifts in circuit operating points. These problems do not occur
even under high output current conditions.
AD842
8
REV. E
GROUNDING AND BYPASSING
In designing practical circuits with the AD842, the user must
remember that whenever high frequencies are involved, some
Figure 24. AD842 Settling Demonstrating No Settling
Tails
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased
interlead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 k
are recommended. If a larger resistor must be used, a small
(<10 pF) feedback capacitor connected in parallel with the feed-
back resistor, R
F
, may be used to compensate for these stray
capacitances and optimize the dynamic performance of the
amplifier in the particular application.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2
F capacitor in parallel with
a 0.1
F ceramic disk capacitor is recommended.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD842 is sensitive to capaci-
tive loading. The AD842 is designed to drive capacitive loads of
up to 20 pF without degradation of its rated performance. Ca-
pacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF.
USING A HEAT SINK
The AD842 draws less quiescent power than most precision
high speed amplifiers and is specified for operation without a
heat sink. However, when driving low impedance loads, the cur-
rent to the load can be 10 times the quiescent current. This will
create a noticeable temperature rise. Improved performance can
be achieved by using a small heat sink such as the Aavid Engi-
neering #602B.
TERMINATED LINE DRIVER
The AD842 is optimized for high speed line driver applications.
Figure 25 shows the AD842 driving a doubly terminated cable
in a gain-of-2 follower configuration. The AD842 maintains a
typical slew rate of 375 V/
s, which means it can drive a 10 V,
6.0 MHz signal or a
3 V, 19.9 MHz signal.
The termination resistor, R
T
, (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. A back-termination resistor (R
BT
, also equal to the
characteristic impedance of the cable) may be placed between
the AD842 output and the cable in order to damp any stray
signals caused by a mismatch between R
T
and the cable's char-
acteristic impedance. This will result in a "cleaner" signal. With
this circuit, the voltage on the line equals V
IN
because one half
of V
OUT
is dropped across R
BT
.
The AD842 has
100 mA minimum output current and, there-
fore, can drive
5 V into a 50 cable.
The feedback resistors, R1 and R2, must be chosen carefully.
Large value resistors are desirable in order to limit the amount
of current drawn from the amplifier output. But large resistors
can cause amplifier instability because the parallel resistance
R1 R2 combines with the input capacitance (typically 25 pF) to
create an additional pole. Also, the voltage noise of the AD842
is equivalent to a 5 k
resistor, so large resistors can signifi-
cantly increase the system noise. Resistor values of 1 k
or 2 k
are recommended.
If termination is not used, cables appear as capacitive loads and
can be decoupled from the AD842 by a resistor in series with
the output.
AD842
TERMINATION
RESISTOR FOR
INPUT SIGNAL
V
IN
+V
S
0.1 F
2.2 F
V
S
0.1 F
2.2 F
R2
R1
R
ST
50 OR 75
CABLE
R
T
R
T
= R
ST
= CABLE CHARACTERISTIC
IMPEDANCE
+
Figure 25. Line Driver Configuration
AD842
9
REV. E
OVERDRIVE RECOVERY
Figure 26 shows the overdrive recovery capability of the AD842.
Typical recovery time is 80 ns from negative overdrive and
400 ns from positive overdrive.
Figure 26. Overdrive Recovery
50
AD842
+V
S
0.1 F
2.2 F
V
S
0.1 F
2.2 F
+
1k
OUTPUT
HP3314A
PULSE GENERATOR
OR EQUIVALENT
1 s, 1V SQUARE
WAVE INPUT
Figure 27. Overdrive Recovery Test Circuit
AD842
10
REV. E
14-Lead Plastic Package
(N-14)
14
1
7
8
PIN 1
0.795 (20.19)
0.725 (18.42)
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C1195c
0
3/00 (rev. E)
PRINTED IN U.S.A.
14-Lead Cerdip Package
(Q-14)
14
1
7
8
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN
0.098 (2.49) MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
16-Lead SOIC Package
(R-16)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.050 (1.27)
BSC
16
9
8
1
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4133 (10.50)
0.3977 (10.00)
0.0125 (0.32)
0.0091 (0.23)
8
0
0.0291 (0.74)
0.0098 (0.25)
45
0.0500 (1.27)
0.0157 (0.40)
20-Terminal Leadless Ceramic Chip Carrier Package
(E-20A)
1
20
4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
45 TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) BSC
0.200 (5.08)
BSC
0.150 (3.81)
BSC
0.075
(1.91)
REF
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
12-Lead Metal Can Package
(TO-8 Style)
0.181 (4.60)
0.148 (3.76)
REFERENCE PLANE
0.050 (1.27) MAX
0.019 (0.48)
0.016 (0.41)
0.045 (1.14)
0.000 (0.00)
0.040 (1.02) MAX
BASE & SEATING PLANE
0.555 (14.10)
0.545 (13.84)
0.375 (9.53)
MIN
0.615 (15.62)
0.592 (15.04)
0.021 (0.53)
0.016 (0.41)
1
2
3
6
5
4
8
7
9
10
11
12
0.036 (0.91)
0.026 (0.66)
0.037 (0.94)
0.026 (0.66)
0.100 (2.54)
BSC
0.200
(5.08)
BSC
0.200 (5.08)
BSC
0.400
(10.16)
BSC
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