REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8517/AD8527
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
7 MHz Rail-to-Rail
Low Voltage Operational Amplifiers
PIN CONFIGURATIONS
5-Lead SOT-23
(RT Suffix)
1
2
3
5
4 IN A
+IN A
V+
OUT A
AD8517
V
8-Lead SOIC
(R Suffix)
OUT A
IN A
+IN A
OUT B
IN B
+IN B
1
8
2
7
3
6
4
5
V+
V
AD8527
8-Lead MSOP
(RM Suffix)
IN A
+IN A
V
OUT B
IN B
+IN B
1
4
5
8
AD8527
OUT A
V+
FEATURES
Single Supply Operation: 1.8 V to 6 V
Space-Saving SOT-23, SOIC Packaging
Wide Bandwidth: 7 MHz @ 5 V
Low Offset Voltage: 3.5 mV Max
Rail-to-Rail Output Swing and Rail-to-Rail Input
8 V/ s Slew Rate
Only 900 A Supply Current @ 5 V
APPLICATIONS
Portable Communications
Portable Phones
Sensor Interface
Active Filters
PCMCIA Cards
ASIC Input Drivers
Wearable Computers
Battery-Powered Devices
New Generation Phones
Personal Digital Assistants
GENERAL DESCRIPTION
The AD8517 brings precision and bandwidth to the SOT-23-5
package even at single supply voltages as low as 1.8 V. The
small package makes it possible to place the AD8517 next to
sensors, reducing external noise pickup. The AD8527 dual
amplifier is offered in the space-saving MSOP package.
The AD8517 and AD8527 are rail-to-rail input and output
bipolar amplifiers with a gain bandwidth of 7 MHz and typical
voltage offset of 1.3 mV from a 1.8 V supply. The low supply
current makes these parts ideal for battery-powered applications.
The 8 V/
s slew rate makes the AD8517/AD8527 a good match
for driving ASIC inputs, such as voice codecs.
The AD8517/AD8527 is specified over the extended industrial
(40
C to +125C) temperature range. The AD8517 single is
available in 5-lead SOT-23 surface-mount packages. The dual
AD8527 is available in 8-lead SOIC and MSOP packages.
2
REV. B
AD8517/AD8527SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
AD8517ART (SOT-23-5)
V
OS
1.3
3.5
mV
40
C T
A
+125C
5
mV
AD8527
V
OS
1.3
3.5
mV
40
C T
A
+125C
5
mV
Input Bias Current
I
B
450
nA
40
C T
A
+125C
900
nA
Input Offset Current
I
OS
225
nA
40
C T
A
+125C
750
nA
Input Voltage Range
V
CM
0
5
V
Common-Mode Rejection Ratio
CMRR
0 V
V
CM
5.0 V,
40
C T
A
+125C
60
70
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 k
, 0.5 V < V
OUT
< 4.5 V
20
V/mV
R
L
= 10 k
, 0.5 V < V
OUT
< 4.5 V
50
100
V/mV
R
L
= 10 k
, 40C T
A
+125C
30
V/mV
Offset Voltage Drift
V
OS
/
T
2
V/C
Bias Current Drift
I
B
/
T
500
pA/
C
OUTPUT CHARACTERISTICS
Output Voltage Swing High
V
OH
I
L
= 250
A,
40
C T
A
+125C
4.965
V
I
L
= 5 mA
4.70
V
Output Voltage Swing Low
V
OL
I
L
= 250
A,
40
C T
A
+125C
35
mV
I
L
= 5 mA
200
mV
Short Circuit Current
I
SC
Short to Ground, Instantaneous
10
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= 2.2 V to 6 V
90
dB
40
C T
A
+125C
65
dB
Supply Current/Amplifier
I
SY
V
OUT
= 2.5 V
900
1,200
A
40
C T
A
+125C
1,400
A
DYNAMIC PERFORMANCE
Slew Rate
SR
1 V < V
OUT
< 4 V, R
L
= 10 k
8
V/
s
Gain Bandwidth Product
GBP
7
MHz
Settling Time
T
S
4 V Step, 0.1%
400
ns
Phase Margin
m
50
Degrees
NOISE PERFORMANCE
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
0.5
V p-p
Voltage Noise Density
e
n
f = 1 kHz
15
nV/
Hz
Current Noise Density
i
n
f = 1 kHz
1.2
pA/
Hz
Specifications subject to change without notice.
(V
S
= 5.0 V, V = 0 V, V
CM
= 2.5 V, T
A
= 25 C unless otherwise noted)
3
REV. B
AD8517/AD8527
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
AD8517ART (SOT-23-5)
V
OS
1.3
3.5
mV
40
C T
A
+125C
5
mV
AD8527
V
OS
1.3
3.5
mV
40
C T
A
+125C
5
mV
Input Bias Current
I
B
450
nA
Input Offset Current
I
OS
225
nA
Input Voltage Range
V
CM
0
2.2
V
Common-Mode Rejection Ratio
CMRR
0 V
V
CM
2.2 V,
40
C T
A
+125C
55
70
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 k
, 0.5 V < V
OUT
< 1.7 V
20
V/mV
R
L
= 10 k
20
50
V/mV
OUTPUT CHARACTERISTICS
Output Voltage Swing High
V
OH
I
L
= 250
A
2.165
V
I
L
= 2.5 mA
1.9
V
Output Voltage Swing Low
V
OL
I
L
= 250
A
35
mV
I
L
= 2.5 mA
200
mV
POWER SUPPLY
Supply Current/Amplifier
I
SY
V
OUT
= 1.1 V
750
1,100
A
40
C T
A
+125C
1,300
A
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 10 k
8
V/
s
Gain Bandwidth Product
GBP
7
MHz
Phase Margin
m
50
Degrees
NOISE PERFORMANCE
Voltage Noise Density
e
n
f = 1 kHz
15
nV/
Hz
Current Noise Density
i
n
f = 1 kHz
1.2
pA/
Hz
Specifications subject to change without notice.
(V
S
= 2.2 V, V = 0 V, V
CM
= 1.1 V, T
A
= 25 C unless otherwise noted)
4
REV. B
AD8517/AD8527SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
AD8517ART (SOT-23-5)
V
OS
1.3
3.5
mV
0
C T
A
125C
5
mV
AD8527
V
OS
1.3
3.5
mV
0
C T
A
125C
5
mV
Input Bias Current
I
B
450
nA
Input Offset Current
I
OS
225
nA
Input Voltage Range
V
CM
0
1.8
V
Common-Mode Rejection Ratio
CMRR
0 V
V
CM
1.8 V,
0
C T
A
125C
50
70
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 k
, 0.5 V < V
OUT
< 1.3 V
20
V/mV
R
L
= 10 k
20
50
V/mV
OUTPUT CHARACTERISTICS
Output Voltage Swing High
V
OH
I
L
= 250
A
1.765
V
I
L
= 2.5 mA
1.5
V
Output Voltage Swing Low
V
OL
I
L
= 250
A
35
mV
I
L
= 2.5 mA
200
mV
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= 1.7 V to 2.2 V,
0
C T
A
125C
50
65
dB
Supply Current/Amplifier
I
SY
V
OUT
= 0.9 V
650
1,100
A
0
C T
A
125C
1,300
A
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 10 k
7
V/
s
Gain Bandwidth Product
GBP
7
MHz
Phase Margin
m
50
Degrees
NOISE PERFORMANCE
Voltage Noise Density
e
n
f = 1 kHz
15
nV/
Hz
Current Noise Density
i
n
f = 1 kHz
1.2
pA/
Hz
Specifications subject to change without notice.
(V
S
= 1.8 V, V = 0 V, V
CM
= 0.9 V, T
A
= 25 C unless otherwise noted)
AD8517/AD8527
5
REV. B
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . .
0.6 V
Internal Power Dissipation
SOT-23 (RT) . . . . . . . . . . . . See Thermal Resistance Chart
SOIC (R) . . . . . . . . . . . . . . . See Thermal Resistance Chart
SOIC (RM) . . . . . . . . . . . . See Thermal Resistance Chart
Output Short-Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . Indefinite for T
A
< +40
C
Storage Temperature Range
R, RM and RT Packages . . . . . . . . . . . . . 65
C to +150C
Operating Temperature Range
AD8517, AD8527 . . . . . . . . . . . . . . . . . . 40
C to +125C
Junction Temperature Range
R, RM and RT Packages . . . . . . . . . . . . . 65
C to +150C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . 300
C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8517/AD8527 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
INPUT OFFSET VOLTAGE mV
120
90
0
4
4
3
QUANTITY OF AMPLIFIERS
2
1
0
1
2
3
60
30
V
S
= 5V
V
CM
= 2.5V
T
A
= 25 C
COUNT = 935 OP AMPS
Figure 1. Input Offset Voltage Distribution
SUPPLY VOLTAGE V
950
900
600
1
6
2
SUPPLY CURRENT
A
3
4
5
800
750
700
650
850
Figure 2. Supply Current per Amplifier vs. Supply Voltage
ORDERING GUIDE
Temperature
Package
Package
Branding
Model
Range
Description
Option
Information
AD8517ART-REEL
40
C to +125C
5-Lead SOT-23
RT-5
ADA
AD8527AR
40
C to +125C
8-Lead SOIC
SO-8
AD8527ARM-REEL
40
C to +125C
8-Lead
SOIC
RM-8
AFA
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
For supply voltages less than 6 V the input voltage is limited to less than or equal
to the supply voltage.
Package Type
JA
1
JC
Unit
5-Lead SOT-23 (RT)
230
146
C/W
8-Lead SOIC (R)
158
43
C/W
8-Lead
SOIC (RM)
210
45
C/W
NOTE
1
JA
is specified for worst-case conditions, i.e.,
JA
is specified for device soldered
in circuit board for SOT-23 and SOIC packages.
AD8517/AD8527
6
REV. B
Typical Characteristics
TEMPERATURE C
1,200
600
50
150
25
SUPPLY CURRENT
A
0
25
50
75
100
125
1,100
1,000
900
800
700
V
S
= 5V
Figure 3. Supply Current per Amplifier vs. Temperature
COMMON-MODE VOLTAGE V
600
600
400
200
0
200
400
3
3
2
INPUT BIAS CURRENT
nA
1
0
1
2
V
S
= 2.5V
T
A
= 25 C
Figure 4. Input Bias Current vs. Common-Mode Voltage
LOAD CURRENT A
140
120
0
10
10k
100
OUTPUT VOLTAGE
mV
1k
100
80
60
40
20
SINK
SOURCE+
T
A
= 25 C
Figure 5. Output Voltage to Supply Rail vs. Load Current
FREQUENCY Hz
100k
100M
1M
OPEN-LOOP GAIN
dB
10M
60
50
40
40
30
20
10
0
10
20
30
45
0
45
90
90
PHASE SHIFT
Degrees
V
S
= 5V
T
A
= 25 C
GAIN
PHASE
Figure 6. Open-Loop Gain vs. Frequency
FREQUENCY Hz
10
100M
1k
CLOSED-LOOP GAIN
dB
1M
40
40
20
0
20
60
100
10k
100k
10M
V
S
= 5V
T
A
= 25 C
C
L
10pF
Figure 7. Closed-Loop Gain vs. Frequency
FREQUENCY Hz
10
1k
CMRR
dB
1M
100
20
40
60
80
0
100
10k
100k
10M
V
S
= 2.5V
T
A
= 25 C
Figure 8. CMRR vs. Frequency
AD8517/AD8527
7
REV. B
FREQUENCY Hz
10
1k
PSRR
dB
1M
120
20
40
60
80
0
100
10k
100k
10M
100
PSRR
V
S
= 2.5V
T
A
= 25 C
PSRR
Figure 9. PSRR vs. Frequency
V
S
= 5V
V
CM
= 2.5V
R
L
= 10k
T
A
= 25 C
V
IN
= 50mV
A
V
= 1
CAPACITANCE pF
60
50
0
10
1k
100
OVERSHOOT
%
30
20
10
40
OS
+OS
Figure 10. Overshoot vs. Capacitance Load
FREQUENCY Hz
6
5
0
10k
10M
100k
MAXIMUM OUTPUT SWING
V p-p
1M
3
2
1
4
DISTORTION = 3%
V
S
= 5V
A
V
= +1
R
L
= 10k
T
A
= 25 C
C
L
= 15pF
Figure 11. Output Swing vs. Frequency
FREQUENCY Hz
10
100M
1k
OUTPUT IMPEDANCE
1M
0
80
60
40
100
100
10k
100k
10M
V
S
= 5V
T
A
= 25 C
10
20
30
50
70
90
AV
CC
= 10
AV
CC
= 1
Figure 12. Output Impedance vs. Frequency
VOLTAGE NOISE DENSITY
nV/ Hz
FREQUENCY Hz
50
0
10
10k
100
1k
40
30
20
10
V
S
= 5V
T
A
= 25 C
Figure 13. Voltage Noise Density vs. Frequency
FREQUENCY Hz
12
0
10
10k
100
1k
8
4
V
S
= 5V
T
A
= 25 C
CURRENT NOISE DENSITY
pA/ Hz
Figure 14. Current Noise Density vs. Frequency
AD8517/AD8527
8
REV. B
VOLTAGE
20mV/Div
TIME 1s/Div
V
S
= 2.5V
A
V
= 120k
T
A
= 25 C
Figure 15. 0.1 Hz to 10 Hz Noise
TIME 200 s/Div
0
0
0
VOLTAGE
1V/Div
0
0
0
0
0
V
S
= 2.5V
A
V
= + 1
V
IN
= SINEWAVE
T
A
= 25 C
Figure 16. No Phase Reversal
THEORY OF OPERATION
The AD85x7 is a rail-to-rail operational amplifier that can operate at
supply voltages as low as 1.8 V. This family is fabricated using Analog
Devices' high-speed complementary bipolar process, also called
XFCB. The process trench isolates each transistor to minimize
parasitic capacitance thereby allowing high-speed performance.
Figure 19 shows a simplified schematic of the AD85x7 family.
The input stage consists of two parallel complementary differen-
tial pair: one NPN pair (Q1 and Q2) and one PNP pair (Q3 and
Q4). The voltage drops across R7. R8, R9, and R10 are kept low
for rail-to-rail operation. The major gain stage of the op amp is a
double-folded cascode consisting of transistors Q5, Q6, Q8, and
Q9. The output stage, which also operates rail-to-rail, is driven by
Q14. The transistors Q13 and Q10 act as level-shifters to give
more headroom during 1.8 V operation.
As the voltage at the base of Q13 increases, Q18 starts to sink
current. When the voltage at the base of Q13 decreases, I8 flows
through D16 and Q15 increasing the VBE of Q17, then Q20
sources current.
The output stage also furnishes gain, which depends on the load
resistance, since the output transistors are in common emitter
configuration. The output swing when sinking or sourcing 250
A
is 35 mV from each rail.
The input bias current characteristics depend on the common-
mode voltage, see Figure 4. As the input voltage reaches about
1 V below V
CC
, the PNP pair (Q3 and Q4) turns off.
The 1 k
input resistor R1 and R2, together with the diodes D7
and D8, protect the input pairs against avalanche damage.
The AD85x7 family exhibits no phase reversal as the input
signal exceeds the supply by more than 0.6 V. Excessive current
can flow through the input pins via the ESD diodes D1D2 or
D3D4, in the event their ~0.6 V thresholds are exceeded. Such
fault currents must be limited to 5 mA or less by the use of
external series resistance(s).
LOW VOLTAGE OPERATION
Battery Voltage Discharge
The AD8517 operates at supply voltages as low as 1.8 V. This
amplifier is ideal for battery-powered applications since it can
operate at the end of discharge voltage of most popular batteries.
Table I lists the Nominal and End of Discharge Voltages of several
typical batteries.
TIME 500ns/Div
VOLTAGE
20mV/Div
V
S
= 2.5V
A
V
= 1
T
A
= 25 C
C
L
= 100pF
R
L
= 10k
Figure 17. Small Signal Transient Response
TIME 200ns/Div
VOLTAGE
500mV/Div
V
S
= 2.5V
A
V
= 1
R
L
= 10k
T
A
= 25 C
Figure 18. Large Signal Transient Response
AD8517/AD8527
9
REV. B
Q14
IN
V
EE
V
CC
V
OUT
Q1
Q3
R5
R6
I2
R1
IN
R2
R4
R3
I1
R7
R8
D2
ESD
D7
D8
Q2
Q4
D1
ESD
D3
ESD
D4
ESD
Q5
Q6
Q7
C1
Q8
Q11
Q9
I4
I3
I5
Q13
I7
I6
C3
R10
R9
R11
Q15
Q17
D6
R12
Q18
I8
C2
R14
Q19
Q20
C4
D9
V
CC
D16
R13
V
EE
Q10
Figure 19. Simplified Schematic
Table I. Typical Battery Life Voltage Range
Nominal
End of Voltage
Battery
Voltage (V)
Discharge (V)
Lead-Acid
2
1.8
Lithium
2.6-3.6
1.7-2.4
NiMH
1.2
1
NiCd
1.2
1
Carbon-Zinc
1.5
1.1
RAIL-TO-RAIL INPUT AND OUTPUT
The AD8517 features an extraordinary rail-to-rail input and
output with supply voltages as low as 1.8 V. With the amplifier's
supply range set to 1.8 V, the input can be set to 1.8 V p-p,
allowing the output to swing to both rails without clipping. Figure
20 shows a scope picture of both input and output taken at unity
gain, with a frequency of 1 kHz, at V
S
= 1.8 V and V
IN
= 1.8 V p-p.
TIME 200 s/Div
V
S
= 0.9V
V
IN
= 1.8 V p-p
V
IN
V
OUT
Figure 20. Rail-to-Rail Input Output
The rail-to-rail feature of the AD8517 can be observed over the
supply voltage range, 1.8 V to 5 V. Traces are shown offset for
clarity.
INPUT BIAS CONSIDERATION
The input bias current (I
B
) is a nonideal, real-life parameter that
affects all op amps. I
B
can generate a somewhat significant offset
voltage. This offset voltage is created by I
B
when flowing through
the negative feedback resistor R
F
. If I
B
is 500 nA (worst case),
and R
F
is 100 k
, the corresponding generated offset voltage is
50 mV (V
OS
= I
B
R
F
).
Obviously the lower R
F
the lower the generated voltage offset.
Using a compensation resistor, R
B
, as shown in Figure 21, can
significantly minimize this effect. With the input bias current mini-
mized, we still need to be aware of the input offset current (I
OS
)
which will generate a slight offset error. Figure 21 shows three
different configurations to minimize IB-induced offset errors.
NONINVERTING CONFIGURATION
R
B
= R
I
R
F
V
OUT
R
F
R
I
V
I
AD8517
R
S
UNITY GAIN BUFFER
V
OUT
R
F
= R
S
V
I
AD8517
V
OUT
R
F
R
I
R
B
= R
I
R
F
V
I
INVERTING CONFIGURATION
AD8517
Figure 21. Input Bias Cancellation Circuits
AD8517/AD8527
10
REV. B
DRIVING CAPACITIVE LOAD
Gain vs. Capacitive Load
Most amplifiers have difficulty driving capacitance due to degradation
of phase caused by additional phase lag from the capacitive load.
Higher capacitance at the output can increase the amount of over-
shoot and ringing in the amplifier's step response and could even
affect the stability of the device. The value of capacitance load an
amplifier can drive before oscillation varies with gain, supply volt-
age, input signal, temperature, and frequency, among others. Unity
gain is the most challenging configuration for driving capacitance
load. However, the AD8517 offers good capacitance driving ability.
Table II shows the AD8517's ability to capacitance load at differ-
ent gains before instability occurs. This table is good for all V
SY
.
Table II. Gain and Capacitance Load
Gain
Max Capacitance
1
400 pF
2
1.5 nF
2.5
8 nF
3
Unconditionally Stable
In-the-Loop Compensation Technique for Driving
Capacitive Loads
When driving capacitive loads in unity configuration, the in-the-
loop compensation technique is recommended to avoid oscillation
as is illustrated in Figure 22.
V
IN
R
X
C
L
C
F
R
F
R
G
V
OUT
AD8517
R
F
+
R
G
C
F
=
1
+
A
CL
1
R
F
C
L
R
O
R
X
=
R
O
R
G
R
F
WHERE R
O
= OPEN-LOOP OUTPUT RESISTANCE
Figure 22. In-the-Loop Compensation Technique for
Driving Capacitive Loads
Snubber Network Compensation for Driving Capacitive Loads
As load capacitance increases, the overshoot and settling time
will increase and the unity gain bandwidth of the device will
decrease. Figure 23 shows an example of the AD8517 config-
ured for unity gain and driving a 10 k
resistor and a 680 pF
capacitor placed in parallel, with a square wave input set to a
frequency of 250 kHz and unity gain.
VOLTAGE
200mV/Div
TIME 1 s/Div
F = 250kHz
AV = +1
C = 680pF
Figure 23. Photo of a Ringing Square Wave
By connecting a series RC from the output of the device to
ground, known as the "snubber" network, this ringing and over-
shoot can be significantly reduced. Figure 24 shows the network
setup, and Figure 25 shows the improvement of the output
response with the "snubber" network added.
5V
C
X
V
IN
R
X
C
L
V
OUT
AD8517
Figure 24. Snubber Network Compensation for Capacitive
Loads
TIME 1 s/Div
F = 250kHz
AV = +1
C = 680pF
VOLTAGE
200mV/Div
Figure 25. Photo of a Square Wave with the Snubber
Network Compensation
The network operates in parallel with the load capacitor, C
L
,
and provides compensation for the added phase lag. The actual
values of the network resistor and capacitor have to be empiri-
cally determined. Table III shows some values of snubber network
for large capacitance load.
AD8517/AD8527
11
REV. B
Table III. Snubber Network Values for Large Capacitive Loads
C
LOAD
Rx
Cx
680 pF
300
3 nF
1 nF
100
10 nF
10 nF
400
30
nF
TOTAL HARMONIC DISTORTION + NOISE
The AD85x7 family offers a low total harmonic distortion, which
makes this amplifier ideal for audio applications. Figure 26 shows a
graph of THD + N, for a V
S
> 3 V the THD + N is about 0.001%
and 0.03% for V
S
1.8 V in a noninverting configuration with a
gain of 1. In an inverting configuration, the noise is 0.003% for
all V
SY
.
FREQUENCY Hz
0.01
0.0001
10
20k
THD + N
%
0.001
0.1
1
100
1k
10k
V
S
> 3V TO 5V
V
S
= 1.8V
A
V
= +2
Figure 26. THD + N vs. Frequency Graph
A MICROPOWER REFERENCE VOLTAGE GENERATOR
Many single supply circuits are configured with the circuit-biased
to one-half of the supply voltage. In these cases, a false-ground
reference can be created by using a voltage divider buffered by an
amplifier. Figure 27 shows the schematic for such a circuit.
The two 1 M
resistors generate the reference voltages while
drawing only 0.9
A of current from a 1.8 V supply. A capacitor
connected from the inverting terminal to the output of the op
amp provides compensation to allow for a bypass capacitor to be
connected at the reference output. This bypass capacitor helps
establish an ac ground for the reference output.
AD8517
10k
0.022 F
V
REF
0.9V TO 2.5V
1 F
1 F
1M
1.8V TO 5V
100
1M
Figure 27. A Micropower Reference Voltage Generator
MICROPHONE PREAMPLIFIER
The AD8517 is ideal to use as a microphone preamplifier.
Figure 28 shows this implementation.
R3
220k
V
CC
V
REF
C1
0.1 F
V
CC
R1
2.2k
ELECTRET
MIC
V
OUT
AD8517
V
IN
R2
22k
|
A
V
|
=
R3
R2
Figure 28. A Microphone Preamplifier
R1 is used to bias an electret microphone and C1 blocks dc
voltage from the amplifier. The magnitude of the gain of the
amplifier is approximately R3/R2 when R2
10 R1. V
REF
should be equal to 1/2 1.8 V for maximum voltage swing.
Direct Access Arrangement for Telephone Line Interface
Figure 28 illustrates a 1.8 V transmit/receive telephone line
interface for 600
transmission systems. It allows full duplex
transmission of signals on a transformer-coupled 600
line in a
differential manner. Amplifier A1 provides gain that can be ad-
justed to meet the modem output drive requirements. Both A1
and A2 are configured to apply the largest possible signal on a
single supply to the transformer. Amplifier A3 is configured as a
difference amplifier for two reasons: (1) It prevents the transmit
signal from interfering with the receive signal and (2) it extracts
the receive signal from the transmission line for amplification by
A4. A4's gain can be adjusted in the same manner as A1's to
meet the modem's input signal requirements. Standard resistor
values permit the use of SIP (Single In-line Package) format
resistor arrays. Couple this with the AD8517/AD8527's 5-lead
SOT-23, 8-lead MSOP, and 8-lead SOIC footprint and this
circuit offers a compact solution.
6.2V
6.2V
TRANSMIT
TxA
RECEIVE
RxA
C1
0.1 F
R1
10k
R2
9.09k
2k
P1
Tx GAIN
ADJUST
A1
R3
360
1:1
T1
TO
TELEPHONE
LINE
1
2
3
7
6
5
2
3
1
6
5
7
10 F
R7
10k
R8
10k
R5
10k
R6
10k
R9
10k
R14
14.3k
R10
10k
R11
10k
R12
10k
R13
10k
C2
0.1 F
P2
Rx GAIN
ADJUST
2k
Z
O
600
+1.8V DC
MIDCOM
671-8005
A2
A3
A4
1/2
AD8517
1/2
AD8517
1/2
AD8527
1/2
AD8527
Figure 29. A Single-Supply Direct Access Arrangement
for Modems
12
REV. B
PRINTED IN U.S.A.
AD8517/AD8527
C3736b2.57/00 (rev. B) 01020
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Narrow Body SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
4
1
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
45
5-Lead SOT-23
(RT-5)
0.1181 (3.00)
0.1102 (2.80)
PIN 1
0.0669 (1.70)
0.0590 (1.50)
0.1181 (3.00)
0.1024 (2.60)
1
3
4
5
0.0748 (1.90)
BSC
0.0374 (0.95) BSC
2
0.0079 (0.20)
0.0031 (0.08)
0.0217 (0.55)
0.0138 (0.35)
10
0
0.0197 (0.50)
0.0138 (0.35)
0.0059 (0.15)
0.0019 (0.05)
0.0512 (1.30)
0.0354 (0.90)
SEATING
PLANE
0.0571 (1.45)
0.0374 (0.95)
8-Lead MSOP
(RM-8)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
0.011 (0.28)
0.003 (0.08)
0.028 (0.71)
0.016 (0.41)
33
27
0.120 (3.05)
0.112 (2.84)
SPICE Model
The SPICE model for the AD8517 amplifier is available and
can be downloaded from the Analog Devices' web site at
http://www.analog.com. The macro-model accurately simulates
a number of AD8517 parameters, including offset voltage, input
common-mode range, and rail-to-rail output swing. The output
voltage versus output current characteristics of the macro-model is
identical to the actual AD8517 performance, which is a critical
feature with a rail-to-rail amplifier model. The model also accu-
rately simulates many ac effects, such as gain-bandwidth product,
phase margin, input voltage noise, CMRR and PSRR versus
frequency, and transient response. Its high degree of model
accuracy makes the AD8517 macro-model one of the most
reliable and true-to-life models available for any amplifier.
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