REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8541/AD8542/AD8544
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
1
2
3
4
IN A
V+
+IN A
OUT D
IN D
+IN D
OUT A
V
AD8544
5
6
7
10
9
8
IN B
OUT B
+IN C
IN C
OUT C
+IN B
11
12
13
14
1
2
3
4
8
7
6
5
AD8541
IN A
V
+IN A
V+
OUT A
NC
NC
NC
NC = NO CONNECT
1
2
3
5
4
IN A
+IN A
V+
OUT A
AD8541
V
1
2
3
4
8
7
6
5
AD8542
IN A
V
+IN A
OUT B
IN B
V+
+IN B
OUT A
General Purpose CMOS
Rail-to-Rail Amplifiers
PIN CONFIGURATIONS
FEATURES
Single Supply Operation: +2.7 V to +5.5 V
Low Supply Current: 45 A/Amplifier
Wide Bandwidth: 1 MHz
No Phase Reversal
Low Input Currents: 4 pA
Unity Gain Stable
Rail-to-Rail Input and Output
APPLICATIONS
ASIC Input or Output Amplifier
Sensor Interface
Piezo Electric Transducer Amplifier
Medical Instrumentation
Mobile Communication
Audio Output
Portable Systems
GENERAL DESCRIPTION
The AD8541/AD8542/AD8544 are single, dual and quad rail-
to-rail input and output single supply amplifiers featuring very
low supply current and 1 MHz bandwidth. All are guaranteed to
operate from a +2.7 V single supply as well as a +5 V supply.
These parts provide 1 MHz bandwidth at low current consump-
tion of 45
A per amplifier.
Very low input bias currents enable the AD8541/AD8542/AD8544
to be used for integrators, photodiode amplifiers, piezo electric
sensors and other applications with high source impedance. Supply
current is only 45
A per amplifier, ideal for battery operation.
Rail-to-rail inputs and outputs are useful to designers buffering
ASICs in single supply systems. The AD8541/AD8542/AD8544
are optimized to maintain high gains at lower supply voltages,
making them useful for active filters and gain stages.
The AD8541/AD8542/AD8544 are specified over the extended
industrial (40
C to +125C) temperature range. The AD8541
is available in 8-lead SO and 5-lead SOT-23 packages. The
AD8542 is available in 8-lead SO, 8-lead MSOP, and 8-lead
TSSOP surface mount packages. The AD8544 is available in
14-lead narrow SO-14 and 14-lead TSSOP surface mount pack-
ages. All TSSOP, MSOP, and SOT versions are available in tape
and reel only.
SO-8 (R)
SOT-23-5 (RT)
SO-8 (R), RM-8, and RU-8
SO-14 (R) and RU-14
2
REV. A
AD8541/AD8542/AD8544SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
1
6
mV
40
C T
A
+125C
7
mV
Input Bias Current
I
B
4
60
pA
40
C T
A
+85C
100
pA
40
C T
A
+125C
1,000
pA
Input Offset Current
I
OS
0.1
30
pA
40
C T
A
+85C
50
pA
40
C T
A
+125C
500
pA
Input Voltage Range
0
+2.7
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 0 V to +2.7 V
40
45
dB
40
C T
A
+125C
38
dB
Large Signal Voltage Gain
A
VO
R
L
= 100 k
, V
O
= +0.5 V to +2.2 V
100
500
V/mV
40
C T
A
+85C
50
V/mV
40
C T
A
+125C
2
V/mV
Offset Voltage Drift
V
OS
/
T
40
C T
A
+125C
4
V/C
Bias Current Drift
I
B
/
T
40
C T
A
+85C
100
fA/
C
40
C T
A
+125C
2,000
fA/
C
Offset Current Drift
I
OS
/
T
40
C T
A
+125C
25
fA/
C
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
I
L
= 1 mA
+2.575 +2.65
V
40
C T
A
+125C
+2.550
V
Output Voltage Low
V
OL
I
L
= 1 mA
35
100
mV
40
C T
A
+125C
125
mV
Output Current
I
OUT
V
OUT
= V
S
1 V
15
mA
I
SC
20
mA
Closed Loop Output Impedance
Z
OUT
f = 200 kHz, A
V
= 1
50
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= +2.5 V to +6 V
65
76
dB
40
C T
A
+125C
60
dB
Supply Current/Amplifier
I
SY
V
O
= 0 V
38
55
A
40
C T
A
+125C
75
A
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 100 k
0.4
0.75
V/
s
Settling Time
t
S
To 0.1% (1 V Step)
5
s
Gain Bandwidth Product
GBP
980
kHz
Phase Margin
o
63
Degrees
NOISE PERFORMANCE
Voltage Noise Density
e
n
f = 1 kHz
40
nV/
Hz
e
n
f = 10 kHz
38
nV/
Hz
Current Noise Density
i
n
<0.1
pA/
Hz
Specifications subject to change without notice.
(V
S
= +2.7 V, V
CM
= +1.35 V, T
A
= +25 C unless otherwise noted)
3
REV. A
AD8541/AD8542/AD8544
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
1
6
mV
40
C T
A
+125C
7
mV
Input Bias Current
I
B
4
60
pA
40
C T
A
+85C
100
pA
40
C T
A
+125C
1,000
pA
Input Offset Current
I
OS
0.1
30
pA
40
C T
A
+85C
50
pA
40
C T
A
+125C
500
pA
Input Voltage Range
0
+3
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 0 V to +3 V
40
45
dB
40
C T
A
+125C
38
dB
Large Signal Voltage Gain
A
VO
R
L
= 100 k
, V
O
= +0.5 V to +2.2 V
100
500
V/mV
40
C T
A
+85C
50
V/mV
40
C T
A
+125C
2
V/mV
Offset Voltage Drift
V
OS
/
T
40
C T
A
+125C
4
V/C
Bias Current Drift
I
B
/
T
40
C T
A
+85C
100
fA/
C
40
C T
A
+125C
2,000
fA/
C
Offset Current Drift
I
OS
/
T
40
C T
A
+125C
25
fA/
C
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
I
L
= 1 mA
+2.875 +2.955
V
40
C T
A
+125C
+2.850
V
Output Voltage Low
V
OL
I
L
= 1 mA
32
100
mV
40
C T
A
+125C
125
mV
Output Current
I
OUT
V
OUT
= V
S
1 V
18
mA
I
SC
25
mA
Closed Loop Output Impedance
Z
OUT
f = 200 kHz, A
V
= 1
50
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= +2.5 V to +6 V
65
76
dB
40
C T
A
+125C
60
dB
Supply Current/Amplifier
I
SY
V
O
= 0 V
40
60
A
40
C T
A
+125C
75
A
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 100 k
0.4
0.8
V/
s
Settling Time
t
S
To 0.01% (1 V Step)
5
s
Gain Bandwidth Product
GBP
980
kHz
Phase Margin
o
64
Degrees
NOISE PERFORMANCE
Voltage Noise Density
e
n
f = 1 kHz
42
nV/
Hz
e
n
f = 10 kHz
38
nV/
Hz
Current Noise Density
i
n
<0.1
pA/
Hz
Specifications subject to change without notice.
(V
S
= +3.0 V, V
CM
= +1.5 V, T
A
= +25 C unless otherwise noted)
4
REV. A
AD8541/AD8542/AD8544SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
1
6
mV
40
C T
A
+125C
7
mV
Input Bias Current
I
B
4
60
pA
40
C T
A
+85C
100
pA
40
C T
A
+125C
1,000
pA
Input Offset Current
I
OS
0.1
30
pA
40
C T
A
+85C
50
pA
40
C T
A
+125C
500
pA
Input Voltage Range
0
+5
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 0 V to +5 V
40
48
dB
40
C T
A
+125C
38
dB
Large Signal Voltage Gain
A
VO
R
L
= 100 k
, V
O
= +0.5 V to +2.2 V
20
40
V/mV
40
C T
A
+85C
10
V/mV
40
C T
A
+125C
2
V/mV
Offset Voltage Drift
V
OS
/
T
40
C T
A
+125C
4
V/C
Bias Current Drift
I
B
/
T
40
C T
A
+85C
100
fA/
C
40
C T
A
+125C
2,000
fA/
C
Offset Current Drift
I
OS
/
T
40
C T
A
+125C
25
fA/
C
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
I
L
= 1 mA
+4.9
+4.965
V
40
C T
A
+125C
+4.875
V
Output Voltage Low
V
OL
I
L
= 1 mA
25
100
mV
40
C T
A
+125C
125
mV
Output Current
I
OUT
V
OUT
= V
S
1 V
30
mA
I
SC
60
mA
Closed Loop Output Impedance
Z
OUT
f = 200 kHz, A
V
= 1
45
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= +2.5 V to +6 V
65
76
dB
40
C T
A
+125C
60
dB
Supply Current/Amplifier
I
SY
V
O
= 0 V
45
65
A
40
C T
A
+125C
85
A
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 100 k
, C
L
= 200 pF
0.45
0.92
V/
s
Full-Power Bandwidth
BW
P
1% Distortion
70
kHz
Settling Time
t
S
To 0.1% (1 V Step)
6
s
Gain Bandwidth Product
GBP
1,000
kHz
Phase Margin
o
67
Degrees
NOISE PERFORMANCE
Voltage Noise Density
e
n
f = 1 kHz
42
nV/
Hz
e
n
f = 10 kHz
38
nV/
Hz
Current Noise Density
i
n
<0.1
pA/
Hz
Specifications subject to change without notice.
(V
S
= +5.0 V, V
CM
= +2.5 V, T
A
= +25 C unless otherwise noted)
AD8541/AD8542/AD8544
5
REV. A
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage(V
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V
S
Differential Input Voltage
2
. . . . . . . . . . . . . . . . . . . . . . .
6 V
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Operating Temperature Range . . . . . . . . . . 40
C to +125C
Junction Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
For supplies less than +6 V, the differential input voltage is equal to
V
S
.
ORDERING GUIDE
Temperature
Package
Package
Branding
Model
Range
Description
Option
Information
AD8541AR
40
C to +125C
8-Lead SOIC
SO-8
AD8541ART
*
40
C to +125C
5-Lead SOT-23
RT-5
A4A
AD8542AR
40
C to +125C
8-Lead SOIC
SO-8
AD8542ARM
*
40
C to +125C
8-Lead MSOP
RM-8
AVA
AD8542ARU
*
40
C to +125C
8-Lead TSSOP
RU-8
AD8544AR
40
C to +125C
14-Lead SOIC
SO-14
AD8544ARU
*
40
C to +125C
14-Lead TSSOP
RU-14
*Available in reels only.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8541/AD8542/AD8544 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PACKAGE INFORMATION
Package Type
JA
1
JC
Units
5-Lead SOT-23 (RT)
256
81
C/W
8-Lead SOIC (R)
158
43
C/W
8-Lead MSOP (RM)
210
45
C/W
8-Lead TSSOP (RU)
240
43
C/W
14-Lead SOIC (R)
120
36
C/W
14-Lead TSSOP (RU)
240
43
C/W
NOTE
1
JA
is specified for worst case conditions, i.e.,
JA
is specified for device soldered
onto a circuit board for surface mount packages.
AD8541/AD8542/AD8544
6
REV. A
COMMON-MODE VOLTAGE V
0.5
0.5
5.5
1.5
2.5
3.5
4.5
INPUT BIAS CURRENT pA
9
8
0
4
3
2
1
7
5
6
V
S
= +2.7V AND +5V
V
CM
= V
S
/2
Figure 3. Input Bias Current vs.
Common-Mode Voltage
FREQUENCY Hz
POWER SUPPLY REJECTION
dB
100
1k
10M
10k
100k
1M
160
140
40
120
100
80
60
40
20
0
20
V
S
= +2.7V
T
A
= +25 C
+PSRR
PSRR
Figure 6. Power Supply Rejection
Ratio vs. Frequency
CAPACITANCE pF
SMALL SIGNAL OVERSHOOT
%
60
0
10
100
10k
1k
30
20
10
40
V
S
= +2.7V
R
L
=
T
A
= +25 C
50
+OS
OS
Figure 9. Small Signal Overshoot vs.
Load Capacitance
INPUT OFFSET VOLTAGE mV
4.5
3.5
4.5
2.5 1.5
0.5
1.5
2.5
3.5
0.5
NUMBER OF AMPLIFIERS
180
160
0
80
60
40
20
140
100
120
V
S
= +5V
V
CM
= +2.5V
T
A
= +25 C
Figure 1. Input Offset Voltage
Distribution
TEMPERATURE C
INPUT BIAS CURRENT
pA
400
0
40
20
140
0
20
40
80
100 120
60
350
200
150
100
50
300
250
V
S
= +2.7V AND +5V
V
CM
= V
S
/2
Figure 4. Input Bias Current vs.
Temperature
LOAD CURRENT mA
OUTPUT VOLTAGE
mV
10k
100
0.01
0.001
0.01
100
0.1
1
10
1
SINK
0.1
10
V
S
= +2.7V
T
A
= +25 C
1k
SOURCE
Figure 7. Output Voltage to Supply
Rail vs. Load Current
TEMPERATURE C
INPUT OFFSET VOLTAGE
mV
1.0
2.5
4.0
55
35
15
5
25 45
65
85 105 125
0.5
2.0
3.0
3.5
1.0
1.5
0.0
0.5
V
S
= +2.7V AND +5V
V
CM
= V
S
/2
145
Figure 2. Input Offset Voltage
vs. Temperature
TEMPERATURE C
INPUT OFFSET CURRENT
pA
7
1
55
35
145
15
25
85 105 125
65
6
3
2
1
0
5
4
V
S
= +2.7V AND +5V
V
CM
= V
S
/2
5
45
Figure 5. Input Offset Current vs.
Temperature
FREQUENCY Hz
OUTPUT SWING
Vp-p
3.0
2.5
0
1k
10k
10M
100k
1M
2.0
1.5
0.5
1.0
V
S
= +2.7V
V
IN
= 2.5Vp-p
R
L
= 2k
T
A
= +25 C
Figure 8. Closed-Loop Output
Voltage Swing vs. Frequency
Typical Performance Characteristics
AD8541/AD8542/AD8544
7
REV. A
CAPACITANCE pF
SMALL SIGNAL OVERSHOOT
%
60
0
10
100
10k
1k
30
20
10
40
V
S
= +2.7V
R
L
= 10k
T
A
= +25 C
50
+OS
OS
Figure 10. Small Signal Overshoot
vs. Load Capacitance
500mV
10 s
1.35V
V
S
= +2.7V
R
L
= 2k
A
V
= +1
T
A
= +25 C
Figure 13. Large Signal Transient
Response
FREQUENCY Hz
COMMON-MODE REJECTION
dB
1k
10k
10M
100k
1M
60
50
40
30
20
V
S
= +5V
T
A
= +25 C
10
0
10
70
80
90
Figure 16. Common-Mode Rejection
Ratio vs. Frequency
CAPACITANCE pF
SMALL SIGNAL OVERSHOOT
%
60
0
10
100
10k
1k
30
20
10
40
V
S
= +2.7V
R
L
= 2k
T
A
= +25 C
50
+OS
OS
Figure 11. Small Signal Overshoot
vs. Load Capacitance
FREQUENCY Hz
GAIN
dB
1k
10k
10M
100k
1M
80
60
40
20
0
45
90
135
180
PHASE SHIFT
Degrees
V
S
= +2.7V
R
L
= NO LOAD
T
A
= +25 C
Figure 14. Open-Loop Gain and
Phase vs. Frequency
LOAD CURRENT mA
OUTPUT VOLTAGE
mV
10k
100
0.01
0.001
0.01
100
0.1
1
10
1
SINK
0.1
10
V
S
= +5V
T
A
= +25 C
1k
SOURCE
Figure 17. Output Voltage to Supply
Rail vs. Frequency
50mV
10 s
1.35V
V
S
= +2.7V
R
L
= 100k
C
L
= 300pF
A
V
= +1
T
A
= +25 C
Figure 12. Small Signal Transient
Response
FREQUENCY Hz
POWER SUPPLY REJECTION RATIO
dB
100
1k
10M
10k
100k
1M
160
140
40
120
100
80
60
40
20
0
20
V
S
= +5V
T
A
= +25 C
+PSRR
PSRR
Figure 15. Power Supply Rejection
Ratio vs. Frequency
FREQUENCY Hz
OUTPUT SWING
Vp-p
3.0
2.5
0
1k
10k
10M
100k
1M
2.0
1.5
0.5
1.0
V
S
= +5V
V
IN
= +4.9Vp-p
R
L
= NO LOAD
T
A
= +25 C
4.0
3.5
5.0
4.5
Figure 18. Closed Loop Output
Voltage Swing vs. Frequency
AD8541/AD8542/AD8544
8
REV. A
FREQUENCY Hz
OUTPUT SWING
Vp-p
3.0
2.5
0
1k
10k
10M
100k
1M
2.0
1.5
0.5
1.0
V
S
= +5V
V
IN
= +4.9Vp-p
R
L
= 2k
T
A
= +25 C
4.0
3.5
5.0
4.5
Figure 19. Closed-Loop Output
Voltage Swing vs. Frequency
CAPACITANCE pF
SMALL SIGNAL OVERSHOOT
%
60
0
10
100
10k
1k
30
20
10
40
V
S
= +5V
R
L
=
T
A
= +25 C
50
+OS
OS
Figure 22. Small Signal Overshoot
vs. Load Capacitance
FREQUENCY Hz
GAIN
dB
1k
10k
10M
100k
1M
80
60
40
20
0
45
90
135
180
PHASE SHIFT
Degrees
V
S
= +5V
R
L
= NO LOAD
T
A
= +25 C
Figure 25. Open-Loop Gain & Phase
vs. Frequency
CAPACITANCE pF
SMALL SIGNAL OVERSHOOT
%
60
0
10
100
10k
1k
30
20
10
40
V
S
= +5V
R
L
= 10k
T
A
= +25 C
50
+OS
OS
Figure 20. Small Signal Overshoot
vs. Load Capacitance
50mV
10 s
2.5V
V
S
= +5V
R
L
= 100k
C
L
= 300pF
A
V
= +1
T
A
= +25 C
Figure 23. Small Signal Transient
Response
1V
20 s
2.5V
V
S
= +5V
R
L
= 10k
A
V
= +1
T
A
= +25 C
V
OUT
V
IN
Figure 26. No Phase Reversal
CAPACITANCE pF
SMALL SIGNAL OVERSHOOT
%
60
0
10
100
10k
1k
30
20
10
40
V
S
= +5V
R
L
= 2k
T
A
= +25 C
50
+OS
OS
Figure 21. Small Signal Overshoot
vs. Load Capacitance
1V
10 s
2.5V
V
S
= +5V
R
L
= 2k
A
V
= +1
T
A
= +25 C
Figure 24. Large Signal Transient
Response
SUPPLY VOLTAGE V
SUPPLY CURRENT/AMPLIFIER
A
60
0
0
1
6
2
3
4
5
50
40
30
20
10
T
A
= +25 C
Figure 27. Supply Current per
Amplifier vs. Supply Voltage
AD8541/AD8542/AD8544
9
REV. A
TEMPERATURE C
SUPPLY CURRENT/AMPLIFIER
A
55
20
55
35
145
15
5
25 45
65
85 105 125
50
45
40
35
30
25
V
S
= +5V
V
S
= +2.7V
Figure 28. Supply Current per
Amplifier vs. Temperature
FREQUENCY kHz
200mV/DIVISION
0
5
25
10
15
20
V
S
= +5V
A
V
= +1
MARKER SET @ 10kHz
MARKER READING: 37.6 V/ Hz
T
A
= +25 C
Figure 30. Voltage Noise
FREQUENCY Hz
IMPEDANCE
1k
10k
100M
100k
1M
10M
1,000
900
0
800
700
600
500
400
300
200
100
V
S
= +2.7V AND +5V
A
V
= +1
T
A
= +25 C
Figure 29. Closed-Loop Output
Impedance vs. Frequency
NOTES ON THE AD854x AMPLIFIERS
The AD8541/AD8542/AD8544 amplifiers are improved perfor-
mance general purpose operational amplifiers. Performance has
been improved over previous amplifiers in several ways.
Lower Supply Current for 1 MHz Gain Bandwidth
The AD854x series typically uses 45 microamps of current per
amplifier. This is much less than the 200
A to 700 A used in
earlier generation parts with similar performance. This makes
the AD854x series a good choice for upgrading portable designs
for longer battery life. Alternatively, additional functions and
performance can be added at the same current drain.
Higher Output Current
At +5 V single supply, the short circuit current is typically 60
A.
Even 1 V from the supply rail, the AD854x amplifiers can provide
30 mA, sourcing or sinking.
Sourcing and sinking is strong at lower voltages, with 15 mA
available at +2.7 V, and 18 mA at 3.0 V. For even higher output
currents, please see the Analog Devices AD8531/AD853/AD8534
parts, with output currents to 250 mA. Information on these
parts is available from your Analog Devices representative, and
datasheets are available at the Analog Devices website at
www.analog.com.
Better Performance at Lower Voltages
The AD854x family parts have been designed to provide better ac
performance, at 3.0 V and 2.7 V, than previously available parts.
Typical gain-bandwidth product is close to 1 MHz at 2.7 V. Volt-
age gain at 2.7 V and 3.0 V is typically 500,000. Phase margin is
typically over +60
C, making the part easy to use.
APPLICATIONS
Notch Filter
The AD8542 has very high open loop gain (especially with supply
voltage below 4 V), which makes it useful for active filters of all
types. For example, Figure 31 illustrates the AD8542 in the clas-
sic Twin-T Notch Filter design. The Twin-T Notch is desired for
simplicity, low output impedance and minimal use of op amps. In
fact, this notch filter may be designed with only one op amp if Q
adjustment is not required. Simply remove U2 as illustrated in
Figure 32. However, a major drawback to this circuit topology is
ensuring that all the Rs and Cs closely match. The components
must closely match or notch frequency offset and drift will cause
the circuit to no longer attenuate at the ideal notch frequency.
To achieve desired performance, 1% or better component
tolerances or special component screens are usually required.
One method to desensitize the circuit-to-component mis-
match is to increase R2 with respect to R1, which lowers Q. A
lower Q increases attenuation over a wider frequency range,
but reduces attenuation at the peak notch frequency.
1/2 AD8542
[ ]
4
1
R1
R1+R2
1
2
RC
C
26.7nF
R1
97.5k
C2
53.6 F
R/2
50k
R2
2.5k
R
100k
R
100k
5
6
7
8
3
2
V
OUT
4
1
1/2 AD8542
5.0V
2.5V
REF
C
26.7nF
2.5V
REF
f
0
=
1
f
0
=
U2
U1
Figure 31. 60 Hz Twin-T Notch Filter, Q = 10
C
2C
R/2
R
R
7
3
2
V
OUT
4
6
AD8541
5.0V
2.5V
REF
C
V
IN
Figure 32. 60 Hz Twin-T Notch Filter, Q =
(Ideal)
Figure 33 diagrams another example of the AD8542 in a
notch filter circuit. The FNDR notch filter has several
unique features as compared to the Twin-T Notch including:
less critical matching requirements; Q is directly proportional
to a single resistor R1. While matching component values is
still important, it is also much easier and/or less expensive to
AD8541/AD8542/AD8544
10
REV. A
accomplish in the FNDR circuit. For example, the Twin-T
Notch uses three capacitors with two unique values, whereas the
FNDR circuit uses only two capacitors, which may be of the
same value. U3 is simply a buffer that is added to lower the out-
put impedance of the circuit.
4
f
=
R
2
C2
L
=
C2
1 F
1/4 AD8544
11
6
1/4 AD8544
1/4 AD8544
10
8
9
C1
1 F
1
2
LC1
R
2.61k
R1
Q ADJUST
200
V
OUT
2.5V
REF
2
1
3
1/4 AD8544
R
2.61k
12
14
13
NC
2.5V
REF
SPARE
5
7
R
2.61k
R
2.61k
2.5V
REF
U3
U2
U1
U4
Figure 33. FNDR 60 Hz Notch Filter with Output Buffer
Comparator Function
A comparator function is a common application for a spare op
amp in a quad package. Figure 34 illustrates 1/4 of the AD8544
as a comparator in a standard overload detection application.
Unlike so many op amps, the AD854x family can double as
comparator because this op amp family has rail-to-rail differen-
tial input range, rail-to-rail output, and a great speed vs. power
ratio. R2 is used to introduce hysteresis. The AD854x when
used as comparators have 5
s propagation delay @ 5 V and 5 s
overload recovery time.
R1
1k
V
OUT
2.5V
REF
V
IN
1/4 AD8544
2.5V
DC
R2
1M
Figure 34. The AD854x Comparator ApplicationOverload
Detector
Photodiode Application
The AD854x family has very high impedance with input bias
current typically around 4 pA. This characteristic allows the
AD854x op amps to be used in photodiode applications and
other applications that require high input impedance. Note that
the AD854x has significant voltage offset, which can be removed
by capacitive coupling or software calibration.
Figure 35, illustrates a photodiode or current measurement
application. The feedback resistor is limited to 10 M
to avoid
excessive output offset. Also note that a resistor is not needed
on the noninverting input to cancel bias current offset, because
the bias current related output offset is not significant when
compared to the voltage offset contribution. For the best per-
formance follow the standard high impedance layout techniques
including: shield circuit, clean circuit board, put a trace con-
nected to the noninverting input around the inverting input,
and use separate analog and digital power supplies.
AD8541
4
6
7
3
2
V
OUT
2.5V
REF
R
10M
C
100pF
D
2.5V
REF
OR
V+
Figure 35. High Input Impedance ApplicationPhotodiode
Amplifier
AD8541/AD8542/AD8544
11
REV. A
* AD8542 SPICE Macro-model Typical Values
* 6/98, Ver. 1
* TAM / ADSC
*
* Copyright 1998 by Analog Devices
*
* Refer to "README.DOC" file for License State-
ment. Use of this
* model indicates your acceptance of the terms
and provisions in
* the License Statement.
*
* Node Assignments
*
noninverting input
*
|
inverting input
*
|
|
positive supply
*
|
|
|
negative supply
*
|
|
|
|
output
*
|
|
|
|
|
*
|
|
|
|
|
.SUBCKT AD8542
1
2
99
50
45
*
* INPUT STAGE
*
M1 4 1 8 8 PIX L=0.6E-6 W=16E-6
M2 6 7 8 8 PIX L=0.6E-6 W=16E-6
M3 11 1 10 10 NIX L=0.6E-6 W=16E-6
M4 12 7 10 10 NIX L=0.6E-6 W=16E-6
RC1 4 50 20E3
RC2 6 50 20E3
RC3 99 11 20E3
RC4 99 12 20E3
C1 4 6 1.5E-12
C2 11 12 1.5E-12
I1 99 8 1E-5
I2 10 50 1E-5
V1 99 9 0.2
V2 13 50 0.2
D1 8 9 DX
D2 13 10 DX
EOS 7 2 POLY(3) (22,98) (73,98) (81,0) 1E-3 1 1
1
IOS 1 2 2.5E-12
*
* CMRR 64dB, ZERO AT 20kHz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 79.6E3
CCM1 21 22 100E-12
RCM2 22 98 50
*
* PSRR=90dB, ZERO AT 200Hz
*
RPS1 70 0 1E6
RPS2 71 0 1E6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1.59E6
CPS3 72 73 500E-12
RPS4 73 98 25
*
* VOLTAGE NOISE REFERENCE OF 35nV/rt(Hz)
*
VN1 80 0 0
RN1 80 0 16.45E-3
HN 81 0 VN1 35
RN2 81 0 1
*
* INTERNAL VOLTAGE REFERENCE
*
VFIX 90 98 DC 1
S1 90 91 (50,99) VSY_SWITCH
VSN1 91 92 DC 0
RSY 92 98 1E3
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY 99 50 POLY(1) (99,50) 0 3.7E-6
*
* ADAPTIVE GAIN STAGE
* AT Vsy>+4.2, AVol=45 V/mv
* AT Vsy<+3.8, AVol=450 V/mv
*
G1 98 30 POLY(2) (4,6) (11,12) 0 2.5E-5 2.5E-5
VR1 30 31 DC 0
H1 31 98 POLY(2) VR1 VSN1 0 5.45E6 0 0 49.05E9
CF 45 30 10E-12
D3 30 99 DX
D4 50 30 DX
*
* OUTPUT STAGE
*
M5 45 46 99 99 POX L=0.6E-6 W=375E-6
M6 45 47 50 50 NOX L=0.6E-6 W=500E-6
EG1 99 46 POLY(1) (98,30) 1.05 1
EG2 47 50 POLY(1) (30,98) 1.04 1
*
* MODELS
*
.MODEL POX PMOS (LEVEL=2,KP=20E-6,VTO=-
+1,LAMBDA=0.067)
.MODEL NOX NMOS (LEVEL=2,KP=20E-
+6,VTO=1,LAMBDA=0.067)
.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-
+0.7,LAMBDA=0.01,KF=1E-31)
.MODEL NIX NMOS (LEVEL=2,KP=20E-
+6,VTO=0.7,LAMBDA=0.01,KF=1E-31)
.MODEL DX D(IS=1E-14)
.MODEL VSY_SWITCH VSWITCH(ROFF=100E3,RON=1,VOFF=-
+4.2,VON=-3.5)
.ENDS AD8542
12
REV. A
C3414
0
3/00 (rev. A)
PRINTED IN U.S.A.
AD8541/AD8542/AD8544
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead TSSOP
(RU-08)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
0.0256 (0.65)
BSC
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
14-Lead TSSOP
(RU-14)
14
8
7
1
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
5-Lead SOT-23
(RT Suffix)
0.1181 (3.00)
0.1102 (2.80)
PIN 1
0.0669 (1.70)
0.0590 (1.50)
0.1181 (3.00)
0.1024 (2.60)
1
3
4
5
0.0748 (1.90)
BSC
0.0374 (0.95) BSC
2
0.0079 (0.20)
0.0031 (0.08)
0.0217 (0.55)
0.0138 (0.35)
10
0
0.0197 (0.50)
0.0138 (0.35)
0.0059 (0.15)
0.0019 (0.05)
0.0512 (1.30)
0.0354 (0.90)
SEATING
PLANE
0.0571 (1.45)
0.0374 (0.95)
14-Lead SOIC
(SO-14)
14
8
7
1
0.3444 (8.75)
0.3367 (8.55)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
4
1
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
8-Lead MSOP
(RM-8)
0.009 (0.23)
0.005 (0.13)
0.028 (0.70)
0.016 (0.40)
6
0
0.037 (0.95)
0.030 (0.75)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
0.193
(4.90)
BSC
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.016 (0.40)
0.010 (0.25)
0.043
(1.10)
MAX
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