REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD8551/AD8552/AD8554

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

Zero-Drift, Single-Supply,

Rail-to-Rail Input/Output

Operational Amplifiers

8-Lead SOIC

(R Suffix)

AD8551

IN A

+IN A

V+

OUT A

NC = NO CONNECT

AD8552

IN A

+IN A

OUT B

IN B

V+

+IN B

OUT A

14-Lead SOIC

(R Suffix)

IN A

+IN A

V+

+IN B

IN B

OUT B

OUT D

IN D

+IN D

+IN C

IN C

OUT C

OUT A

AD8554

FEATURES
Low Offset Voltage: 1 V
Input Offset Drift: 0.005 V/ C
Rail-to-Rail Input and Output Swing
+5 V/+2.7 V Single-Supply Operation
High Gain, CMRR, PSRR: 130 dB
Ultralow Input Bias Current: 20 pA
Low Supply Current: 700 A/Op Amp
Overload Recovery Time: 50 s
No External Capacitors Required

APPLICATIONS
Temperature Sensors
Pressure Sensors
Precision Current Sensing
Strain Gage Amplifiers
Medical Instrumentation
Thermocouple Amplifiers

GENERAL DESCRIPTION

This new family of amplifiers has ultralow offset, drift and bias
current. The AD8551, AD8552 and AD8554 are single, dual and
quad amplifiers featuring rail-to-rail input and output swings. All
are guaranteed to operate from +2.7 V to +5 V single supply.

The AD855x family provides the benefits previously found only
in expensive autozeroing or chopper-stabilized amplifiers. Using
Analog Devices' new topology these new zero-drift amplifiers
combine low cost with high accuracy. No external capacitors are
required.

With an offset voltage of only 1

V and drift of 0.005

the AD8551 is perfectly suited for applications where error
sources cannot be tolerated. Temperature, position and pres-
sure sensors, medical equipment and strain gage amplifiers
benefit greatly from nearly zero drift over their operating
temperature range. The rail-to-rail input and output swings
provided by the AD855x family make both high-side and low-
side sensing easy.

The AD855x family is specified for the extended industrial/
automotive (40

C to +125

C) temperature range. The AD8551

single is available in 8-lead MSOP and narrow 8-lead SOIC
packages. The AD8552 dual amplifier is available in 8-lead
narrow SO and 8-lead TSSOP surface mount packages. The
AD8554 quad is available in narrow 14-lead SOIC and 14-lead
TSSOP packages.

8-Lead MSOP

(RM Suffix)

IN A
IN A

V+

OUT A
NC

AD8551

NC = NO CONNECT

8-Lead TSSOP

(RU Suffix)

IN A

+IN A

OUT B

IN B

+IN B

V+

AD8552

OUT A

14-Lead TSSOP

(RU Suffix)

OUT A

IN A
IN A

IN D

OUT D

IN B
IN B

OUT B

IN C

OUT C

IN C

AD8554

PIN CONFIGURATIONS

8-Lead SOIC

(R Suffix)

REV. 0

AD8551/AD8552/AD8554SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

INPUT CHARACTERISTICS

Offset Voltage

+125

Input Bias Current

+125

1.0

1.5

Input Offset Current

+125

150

200

Input Voltage Range

Common-Mode Rejection Ratio

CMRR

= 0 V to +5 V

120

140

+125

115

130

Large Signal Voltage Gain

= 10 k

, V

= +0.3 V to +4.7 V

125

145

+125

120

135

Offset Voltage Drift

+125

0.005 0.04

OUTPUT CHARACTERISTICS

Output Voltage High

= 100 k

to GND

4.99

4.998

C to +125

4.99

4.997

= 10 k

to GND

4.95

4.98

C to +125

4.95

4.975

Output Voltage Low

= 100 k

to V+

C to +125

= 10 k

to V+

C to +125

Short Circuit Limit

C to +125

Output Current

C to +125

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

= +2.7 V to +5.5 V

120

130

+125

115

130

Supply Current/Amplifier

= 0 V

850

975

+125

1,000 1,075

DYNAMIC PERFORMANCE

Slew Rate

= 10 k

0.4

Overload Recovery Time

0.05

0.3

Gain Bandwidth Product

GBP

1.5

MHz

NOISE PERFORMANCE

Voltage Noise

p-p

0 Hz to 10 Hz

1.0

V p-p

p-p

0 Hz to 1 Hz

0.32

V p-p

Voltage Noise Density

f = 1 kHz

nV/

Current Noise Density

f = 10 Hz

fA/

NOTE

Gain testing is highly dependent upon test bandwidth.

Specifications subject to change without notice.

= +5 V, V

= +2.5 V, V

= +2.5 V, T

= +25 C unless otherwise noted)

REV. 0

AD8551/AD8552/AD8554

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

INPUT CHARACTERISTICS

Offset Voltage

+125

Input Bias Current

+125

1.0

1.5

Input Offset Current

+125

150

200

Input Voltage Range

2.7

Common-Mode Rejection Ratio

CMRR

= 0 V to +2.7 V

115

130

+125

110

130

Large Signal Voltage Gain

= 10 k

, V

= +0.3 V to +2.4 V

110

140

+125

105

130

Offset Voltage Drift

+125

0.005 0.04

OUTPUT CHARACTERISTICS

Output Voltage High

= 100 k

to GND

2.685

2.697

C to +125

2.685

2.696

= 10 k

to GND

2.67

2.68

C to +125

2.67

2.675

Output Voltage Low

= 100 k

to V+

C to +125

= 10 k

to V+

C to +125

Short Circuit Limit

C to +125

Output Current

C to +125

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

= +2.7 V to +5.5 V

120

130

+125

115

130

Supply Current/Amplifier

= 0 V

750

900

+125

950

1,000

DYNAMIC PERFORMANCE

Slew Rate

= 10 k

0.5

Overload Recovery Time

0.05

Gain Bandwidth Product

GBP

MHz

NOISE PERFORMANCE

Voltage Noise

p-p

0 Hz to 10 Hz

1.6

V p-p

Voltage Noise Density

f = 1 kHz

nV/

Current Noise Density

f = 10 Hz

fA/

NOTE

Gain testing is highly dependent upon test bandwidth.

Specifications subject to change without notice.

= +2.7 V, V

= +1.35 V, V

= +1.35 V, T

= +25 C unless otherwise noted)

AD8551/AD8552/AD8554

REV. 0

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option

Brand

AD8551ARM

C to +125

8-Lead MSOP

RM-8

AHA

AD8551AR

C to +125

8-Lead SOIC

SO-8

AD8552ARU

C to +125

8-Lead TSSOP

RU-8

AD8552AR

C to +125

8-Lead SOIC

SO-8

AD8554ARU

C to +125

14-Lead TSSOP

RU-14

AD8554AR

C to +125

14-Lead SOIC

SO-14

NOTES

Due to package size limitations, these characters represent the part number.

Available in reels only. 1,000 or 2,500 pieces per reel.

Available in reels only. 2,500 pieces per reel.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . GND to V

+ 0.3 V

Differential Input Voltage

. . . . . . . . . . . . . . . . . . . . . .

5.0 V

ESD(Human Body Model) . . . . . . . . . . . . . . . . . . . . . 2,000 V
Output Short-Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range

RM, RU and R Packages . . . . . . . . . . . . . 65

C to +150

Operating Temperature Range

AD8551A/AD8552A/AD8554A . . . . . . . . 40

C to +125

Junction Temperature Range

RM, RU and R Packages . . . . . . . . . . . . . 65

C to +150

Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.

Differential input voltage is limited to

5.0 V or the supply voltage, whichever is less.

Package Type

Units

8-Lead MSOP (RM)

190

C/W

8-Lead TSSOP (RU)

240

C/W

8-Lead SOIC (R)

158

C/W

14-Lead TSSOP (RU)

180

C/W

14-Lead SOIC (R)

120

C/W

NOTE

is specified for worst case conditions, i.e.,

is specified for device in socket

for P-DIP packages,

is specified for device soldered in circuit board for

SOIC and TSSOP packages.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8551/AD8552/AD8554 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

AD8551/AD8552/AD8554

REV. 0

OFFSET VOLTAGE V

NUMBER OF AMPLIFIERS

180

2.5

0.5

120

100

2.5

= +2.7V

= +1.35V

= +25 C

140

160

1.5

0.5

1.5

Figure 1. Input Offset Voltage
Distribution at +2.7 V

OFFSET VOLTAGE V

NUMBER OF AMPLIFIERS

180

120

100

= +5V

= +2.5V

= +25 C

140

160

2.5

0.5

2.5

1.5

0.5

1.5

Figure 4. Input Offset Voltage
Distribution at +5 V

LOAD CURRENT mA

0.1

0.001

OUTPUT VOLTAGE mV

0.1

100

10k

SOURCE

SINK

= +2.7V

= +25 C

100

0.0001

0.01

Figure 7. Output Voltage to Supply
Rail vs. Output Current at +2.7 V

INPUT COMMON-MODE VOLTAGE V

INPUT BIAS CURRENT pA

= +5V

= 40 C, +25 C, +85 C

40 C

+25 C

+85 C

Figure 2. Input Bias Current vs.
Common-Mode Voltage

INPUT OFFSET DRIFT nV/ C

NUMBER OF AMPLIFIERS

= +5V

= +2.5V

= 40 C TO +125 C

Figure 5. Input Offset Voltage Drift
Distribution at +5 V

TEMPERATURE C

INPUT BIAS CURRENT 

1000

125

75 100

250

500

750

150

= +2.5V

= +5V

Figure 8. Bias Current vs. Temperature

INPUT COMMON-MODE VOLTAGE V

INPUT BIAS CURRENT pA

1,500

2,000

1,000

500

1,000

1,500

500

= +5V

= +125 C

Figure 3. Input Bias Current vs.
Common-Mode Voltage

LOAD CURRENT mA

0.1

0.001

OUTPUT VOLTAGE mV

0.1

100

10k

100

0.0001

0.01

SOURCE

SINK

= +5V

= +25 C

Figure 6. Output Voltage to Supply
Rail vs. Output Current at +5 V

TEMPERATURE C

SUPPLY CURRENT 

1.0

0.8

125

75 100

0.6

0.4

0.2

150

+5V

+2.7V

Figure 9. Supply Current vs.
Temperature

Typical Performance Characteristics

AD8551/AD8552/AD8554

REV. 0

SUPPLY VOLTAGE V

SUPPLY CURRENT PER AMPLIFIER 

800

700

400

300

200

100

600

500

= +25 C

Figure 10. Supply Current vs.
Supply Voltage

FREQUENCY Hz

CLOSED-LOOP GAIN dB

100

10M

10k

100k

= 100

= +2.7V

= 0pF

= 2k

= 10

= +1

Figure 13. Closed Loop Gain vs.
Frequency at +2.7 V

= +5V

= 100

= 1

= 10

FREQUENCY Hz

OUTPUT IMPEDANCE 

100

10M

10k

100k

300

270

240

210

180

150

120

Figure 16. Output Impedance vs.
Frequency at +5 V

FREQUENCY Hz

OPEN-LOOP GAIN dB

10k

100k

100M

10M

135

180

225

270

PHASE SHIFT De

rees

= +2.7V

= 0pF

Figure 11. Open-Loop Gain and
Phase Shift vs. Frequency at +2.7 V

= 100

= +5V

= 0pF

= 2k

= 10

= +1

FREQUENCY Hz

CLOSED-LOOP GAIN dB

100

10M

10k

100k

Figure 14. Closed Loop Gain vs.
Frequency at +5 V

2 s

500mV

= +2.7V

= 300pF

= 2k

= +1

Figure 17. Large Signal Transient
Response at +2.7 V

FREQUENCY Hz

OPEN-LOOP GAIN dB

10k

100k

100M

10M

135

180

225

270

PHASE SHIFT Degrees

= +5V

= 0pF

Figure 12. Open-Loop Gain and
Phase Shift vs. Frequency at +5 V

FREQUENCY Hz

OUTPUT IMPEDANCE 

100

10M

10k

100k

300

270

240

210

180

150

120

= +2.7V

= 100

= 1

= 10

Figure 15. Output Impedance vs.
Frequency at +2.7 V

5 s

= +5V

= 300pF

= 2k

= +1

Figure 18. Large Signal Transient
Response at +5 V

AD8551/AD8552/AD8554

REV. 0

5 s

50mV

= 1.35V

= 50pF

= +1

Figure 19. Small Signal Transient
Response at +2.7 V

CAPACITANCE pF

SMALL SIGNAL OVERSHOOT %

100

10k

+OS

= 2.5V

= 2k

= +25 C

Figure 22. Small Signal Overshoot
vs. Load Capacitance at +5 V

200 s

= 2.5V

= 2k

= 100

= 60mV p-p

Figure 25. No Phase Reversal

5 s

50mV

= 2.5V

= 50pF

= +1

Figure 20. Small Signal Transient
Response at +5 V

= 2.5V

= 200mV p-p

(RET TO GND)
C

= 0pF

= 10k

= 100

20 s

OUT

BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV

Figure 23. Positive Overvoltage
Recovery

= +2.7V

FREQUENCY Hz

CMRR dB

140

100

10M

10k

100k

120

100

Figure 26. CMRR vs. Frequency
at +2.7 V

CAPACITANCE pF

SMALL SIGNAL OVERSHOOT %

100

10k

+OS

= 1.35V

= 2k

= +25 C

Figure 21. Small Signal Overshoot
vs. Load Capacitance at +2.7 V

= 2.5V

= +200mV p-p

(RET TO GND)
C

= 0pF

= 10k

= 100

20 s

OUT

BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV

Figure 24. Negative Overvoltage
Recovery

FREQUENCY Hz

CMRR dB

140

100

10M

10k

100k

120

100

= +5V

Figure 27. CMRR vs. Frequency
at +5 V

AD8551/AD8552/AD8554

REV. 0

FREQUENCY Hz

PSRR dB

140

100

10M

10k

100k

120

100

+PSRR

PSRR

= 1.35V

Figure 28. PSRR vs. Frequency
at

1.35 V

3.0

2.5

2.0

1.5

0.5

1.0

= 2.5V

= 2k

= +1

THD+N < 1%
T

= +25 C

3.5

4.0

4.5

5.0

5.5

FREQUENCY Hz

OUTPUT SWING V p-p

100

10k

100k

Figure 31. Maximum Output Swing
vs. Frequency at +5 V

 nV/ Hz

= +2.7V

= 0

0.5

FREQUENCY kHz

1.0

1.5

2.0

2.5

104

130

156

182

Figure 34. Voltage Noise Density at
+2.7 V from 0 Hz to 2.5 kHz

+PSRR

PSRR

= 2.5V

FREQUENCY Hz

PSRR dB

140

100

10M

10k

100k

120

100

Figure 29. PSRR vs. Frequency
at

2.5 V

2mV

= 1.35V

= 10,000

Figure 32. 0.1 Hz to 10 Hz Noise
at +2.7 V

 nV/ Hz

= +2.7V

= 0

FREQUENCY kHz

112

Figure 35. Voltage Noise Density at
+2.7 V from 0 Hz to 25 kHz

FREQUENCY Hz

OUTPUT SWING V p-p

3.0

2.5

100

10k

100k

2.0

1.5

0.5

1.0

= 1.35V

= 2k

= +1

THD+N < 1%
T

= +25 C

Figure 30. Maximum Output Swing
vs. Frequency at +2.7 V

2mV

= 2.5V

= 10,000

Figure 33. 0.1 Hz to 10 Hz Noise at +5 V

= +5V

= 0

0.5

FREQUENCY kHz

1.0

1.5

2.0

2.5

 nV/ Hz

Figure 36. Voltage Noise Density at
+5 V from 0 Hz to 2.5 kHz

AD8551/AD8552/AD8554

REV. 0

 nV/ Hz

= ±5V

= 0

FREQUENCY kHz

112

Figure 37. Voltage Noise Density
at +5 V from 0 Hz to 25 kHz

TEMPERATURE C

SHORT-CIRCUIT CURRENT mA

125

75 100

150

= +2.7V

SC+

Figure 40. Output Short-Circuit
Current vs. Temperature

100

TEMPERATURE C

OUTPUT VOLTAGE SWING mV

250

200

125

75 100

150

= +5.0V

125

175

225

= 1k

= 10k

= 100k

Figure 43. Output Voltage to Supply
Rail vs. Temperature

 nV/ Hz

= +5V

= 0

FREQUENCY Hz

120

144

168

Figure 38. Voltage Noise Density
at +5 V from 0 Hz to 10 Hz

TEMPERATURE C

SHORT-CIRCUIT CURRENT mA

100

125

75 100

150

= +5.0V

SC+

Figure 41. Output Short-Circuit
Current vs. Temperature

TEMPERATURE C

POWER SUPPLY REJECTION dB

150

145

125

75 100

140

135

130

150

= +2.7V TO +5.5V

Figure 39. Power-Supply Rejection
vs. Temperature

100

TEMPERATURE C

OUTPUT VOLTAGE SWING mV

250

200

125

75 100

150

= +5.0V

125

175

225

= 1k

= 10k

= 100k

Figure 42. Output Voltage to
Supply Rail vs. Temperature

AD8551/AD8552/AD8554

REV. 0

FUNCTIONAL DESCRIPTION

The AD855x family of amplifiers are high precision rail-to-rail
operational amplifiers that can be run from a single supply volt-
age. Their typical offset voltage of less than 1

V allows these

amplifiers to be easily configured for high gains without risk of
excessive output voltage errors. The extremely small tempera-
ture drift of 5 nV/

C ensures a minimum of offset voltage error

over its entire temperature range of 40

C to +125

C, making

the AD855x amplifiers ideal for a variety of sensitive measure-
ment applications in harsh operating environments such as
under-hood and braking/suspension systems in automobiles.

The AD855x family are CMOS amplifiers and achieve their
high degree of precision through autozero stabilization. This
autocorrection topology allows the AD855x to maintain its low
offset voltage over a wide temperature range and over its operat-
ing lifetime.

Amplifier Architecture

Each AD855x op amp consists of two amplifiers, a main amplifier
and a secondary amplifier, used to correct the offset voltage of the
main amplifier. Both consist of a rail-to-rail input stage, allowing
the input common-mode voltage range to reach both supply rails.
The input stage consists of an NMOS differential pair operating
concurrently with a parallel PMOS differential pair. The outputs
from the differential input stages are combined in another gain
stage whose output is used to drive a rail-to-rail output stage.

The wide voltage swing of the amplifier is achieved by using two
output transistors in a common-source configuration. The output
voltage range is limited by the drain to source resistance of these
transistors. As the amplifier is required to source or sink more
output current, the r

of these transistors increases, raising the

voltage drop across these transistors. Simply put, the output volt-
age will not swing as close to the rail under heavy output current
conditions as it will with light output current. This is a character-
istic of all rail-to-rail output amplifiers. Figures 6 and 7 show how
close the output voltage can get to the rails with a given output
current. The output of the AD855x is short circuit protected to
approximately 50 mA of current.

The AD855x amplifiers have exceptional gain, yielding greater
than 120 dB of open-loop gain with a load of 2 k

. Because the

output transistors are configured in a common-source configu-
ration, the gain of the output stage, and thus the open-loop gain
of the amplifier, is dependent on the load resistance. Open-loop
gain will decrease with smaller load resistances. This is another
characteristic of rail-to-rail output amplifiers.

Basic Autozero Amplifier Theory

Autocorrection amplifiers are not a new technology. Various IC
implementations have been available for over 15 years and some
improvements have been made over time. The AD855x design
offers a number of significant performance improvements over
older versions while attaining a very substantial reduction in de-
vice cost. This section offers a simplified explanation of how the
AD855x is able to offer extremely low offset voltages and high
open-loop gains.

As noted in the previous section on amplifier architecture, each
AD855x op amp contains two internal amplifiers. One is used as
the primary amplifier, the other as an autocorrection, or nulling,
amplifier. Each amplifier has an associated input offset voltage,
which can be modeled as a dc voltage source in series with the
noninverting input. In Figures 44 and 45 these are labeled as
V

OSX

, where x denotes the amplifier associated with the offset; A

for the nulling amplifier, B for the primary amplifier. The open-
loop gain for the +IN and IN inputs of each amplifier is given
as A

. Both amplifiers also have a third voltage input with an

associated open-loop gain of B

There are two modes of operation determined by the action of
two sets of switches in the amplifier: An autozero phase and an
amplification phase.

Autozero Phase

In this phase, all

A switches are closed and all

B switches are

opened. Here, the nulling amplifier is taken out of the gain loop
by shorting its two inputs together. Of course, there is a degree of
offset voltage, shown as V

OSA

, inherent in the nulling amplifier

which maintains a potential difference between the +IN and IN
inputs. The nulling amplifier feedback loop is closed through

and V

OSA

appears at the output of the nulling amp and on C

an internal capacitor in the AD855x. Mathematically, we can ex-
press this in the time domain as:

A V

B V

A OSA

A OA

[ ]

(1)

which can be expressed as,

A V

A OSA

[ ]

(2)

This shows us that the offset voltage of the nulling amplifier
times a gain factor appears at the output of the nulling amplifier
and thus on the C

capacitor.

IN+

OUT

OSA

Figure 44. Autozero Phase of the AD855x

Amplification Phase

When the

B switches close and the

A switches open for the

amplification phase, this offset voltage remains on C

and

essentially corrects any error from the nulling amplifier. The
voltage across C

is designated as V

. Let us also designate

as the potential difference between the two inputs to the

primary amplifier, or V

= (V

IN+

). Now the output of the

nulling amplifier can be expressed as:

A V

B V

OSA

[ ]

(

)

[ ]

(3)

AD8551/AD8552/AD8554

REV. 0

IN+

OUT

OSA

Figure 45. Output Phase of the Amplifier

Because

A is now open and there is no place for C

to dis-

charge, the voltage V

at the present time t is equal to the

voltage at the output of the nulling amp V

at the time when

A was closed. If we call the period of the autocorrection

switching frequency T

, then the amplifier switches between

phases every 0.5

. Therefore, in the amplification phase:

[ ]

(4)

And substituting Equation 4 and Equation 2 into Equation 3 yields:

A V

A B V

A OSA

[ ]

(5)

For the sake of simplification, let us assume that the autocorrection
frequency is much faster than any potential change in V

OSA

OSB

. This is a good assumption since changes in offset voltage are

a function of temperature variation or long-term wear time, both of
which are much slower than the auto-zero clock frequency of the
AD855x. This effectively makes V

time invariant and we can re-

arrange Equation 5 and rewrite it as:

A V

A B V

OSA

A OSA

[ ]

(

)

(6)

or,

OSA

[ ]

(7)

We can already get a feel for the autozeroing in action. Note the
V

term is reduced by a 1 + B

factor. This shows how the

nulling amplifier has greatly reduced its own offset voltage error
even before correcting the primary amplifier. Now the primary
amplifier output voltage is the voltage at the output of the
AD855x amplifier. It is equal to:

A V

B V

OUT

OSB

[ ]

(

)

(8)

In the amplification phase, V

= V

, so this can be rewritten as:

A V

OUT

B OSB

OSA

[ ]

(9)

Combining terms,

t A

A B

A B V

A V

OUT

B OSA

B OSB

[ ]

(

)

(10)

The AD855x architecture is optimized in such a way that
A

= A

and B

= B

and B

>> 1. Also, the gain product of

is much greater than A

. These allow Equation 10 to be

simplified to:

t A B

A V

OUT

OSA

OSB

[ ]

(

)

(11)

Most obvious is the gain product of both the primary and nulling
amplifiers. This A

term is what gives the AD855x its extremely

high open-loop gain. To understand how V

OSA

and V

OSB

relate to

the overall effective input offset voltage of the complete amplifier,
we should set up the generic amplifier equation of:

OUT

EFF

= ×

(

)

(12)

Where k is the open-loop gain of an amplifier and V

OS, EFF

is its

effective offset voltage. Putting Equation 12 into the form of
Equation 11 gives us:

t A B

A B

OUT

EFF

[ ]

(13)

And from here, it is easy to see that:

EFF

OSA

OSB

(14)

Thus, the offset voltages of both the primary and nulling ampli-
fiers are reduced by the gain factor B

. This takes a typical input

offset voltage from several millivolts down to an effective input
offset voltage of submicrovolts. This autocorrection scheme is
what makes the AD855x family of amplifiers among the most
precise amplifiers in the world.

High Gain, CMRR, PSRR

Common-mode and power supply rejection are indications of
the amount of offset voltage an amplifier has as a result of a
change in its input common-mode or power supply voltages. As
shown in the previous section, the autocorrection architecture of
the AD855x allows it to quite effectively minimize offset volt-
ages. The technique also corrects for offset errors caused by
common-mode voltage swings and power supply variations.
This results in superb CMRR and PSRR figures in excess of
130 dB. Because the autocorrection occurs continuously, these
figures can be maintained across the device's entire temperature
range, from 40

C to +125

Maximizing Performance Through Proper Layout

To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD855x, care
should be taken in the circuit board layout. The PC board sur-
face must remain clean and free of moisture to avoid leakage
currents between adjacent traces. Surface coating of the circuit
board will reduce surface moisture and provide a humidity
barrier, reducing parasitic resistance on the board. The use of
guard rings around the amplifier inputs will further reduce leak-
age currents. Figure 46 shows how the guard ring should be
configured and Figure 47 shows the top view of how a surface
mount layout can be arranged. The guard ring does not need to

AD8551/AD8552/AD8554

REV. 0

be a specific width, but it should form a continuous loop around
both inputs. By setting the guard ring voltage equal to the volt-
age at the noninverting input, parasitic capacitance is minimized
as well. For further reduction of leakage currents, components
can be mounted to the PC board using Teflon standoff insulators.

OUT

AD8552

OUT

AD8552

OUT

AD8552

Figure 46. Guard Ring Layout and Connections to Reduce
PC Board Leakage Currents

V+

REF

IN1

IN2

GUARD
RING

AD8552

REF

GUARD
RING

Figure 47. Top View of AD8552 SOIC Layout with
Guard Rings

Other potential sources of offset error are thermoelectric voltages
on the circuit board. This voltage, also called Seebeck voltage,
occurs at the junction of two dissimilar metals and is proportional
to the temperature of the junction. The most common metallic
junctions on a circuit board are solder-to-board trace and solder-
to-component lead. Figure 48 shows a cross-section diagram view
of the thermal voltage error sources. If the temperature of the PC
board at one end of the component (T

) is different from the

temperature at the other end (T

), the Seebeck voltages will not

be equal, resulting in a thermal voltage error.

This thermocouple error can be reduced by using dummy com-
ponents to match the thermoelectric error source. Placing the
dummy component as close as possible to its partner will ensure
both Seebeck voltages are equal, thus canceling the thermo-
couple error. Maintaining a constant ambient temperature on
the circuit board will further reduce this error. The use of a
ground plane will help distribute heat throughout the board and
will also reduce EMI noise pickup.

SURFACE MOUNT

COMPONENT

LEAD

SOLDER

PC BOARD

COPPER
TRACE

SC2

TS2

SC1

TS1

IF T

, THEN

TS1

+ V

SC1

TS2

+ V

SC2

Figure 48. Mismatch in Seebeck Voltages Causes a
Thermoelectric Voltage Error

OUT

AD855x

= 1 + (R

)

= R

NOTE: R

SHOULD BE PLACED IN CLOSE PROXIMITY AND

ALIGNMENT TO R

TO BALANCE SEEBECK VOLTAGES

Figure 49. Using Dummy Components to Cancel
Thermoelectric Voltage Errors

1/f Noise Characteristics

Another advantage of autozero amplifiers is their ability to cancel
flicker noise. Flicker noise, also known as 1/f noise, is noise inher-
ent in the physics of semiconductor devices and increases 3 dB
for every octave decrease in frequency. The 1/f corner frequency
of an amplifier is the frequency at which the flicker noise is equal
to the broadband noise of the amplifier. At lower frequencies,
flicker noise dominates, causing higher degrees of error for sub-
Hertz frequencies or dc precision applications.

Because the AD855x amplifiers are self-correcting op amps,
they do not have increasing flicker noise at lower frequencies.
In essence, low frequency noise is treated as a slowly varying
offset error and is greatly reduced as a result of autocorrection.
The correction becomes more effective as the noise frequency
approaches dc, offsetting the tendency of the noise to increase
exponentially as frequency decreases. This allows the AD855x
to have lower noise near dc than standard low-noise amplifiers
that are susceptible to 1/f noise.

Intermodulation Distortion

The AD855x can be used as a conventional op amp for gain/
bandwidth combinations up to 1.5 MHz. The autozero correc-
tion frequency of the device is fixed at 4 kHz. Although a trace
amount of this frequency will feed through to the output, the
amplifier can be used at much higher frequencies. Figure 50
shows the spectral output of the AD8552 with the amplifier
configured for unity gain and the input grounded.

The 4 kHz autozero clock frequency appears at the output with
less than 2

V of amplitude. Harmonics are also present, but at

reduced levels from the fundamental autozero clock frequency.
The amplitude of the clock frequency feedthrough is proportional
to the closed-loop gain of the amplifier. Like other autocorrection
amplifiers, at higher gains there will be more clock frequency
feedthrough. Figure 51 shows the spectral output with the ampli-
fier configured for a gain of 60 dB.

AD8551/AD8552/AD8554

REV. 0

FREQUENCY kHz

140

OUTPUT SIGNAL

100

120

= +5V

= 0dB

Figure 50. Spectral Analysis of AD855x Output in Unity
Gain Configuration

FREQUENCY kHz

140

OUTPUT SIGNAL

100

120

= +5V

= +60dB

Figure 51. Spectral Analysis of AD855x Output with
+60 dB Gain

When an input signal is applied, the output will contain some
degree of Intermodulation Distortion (IMD). This is another
characteristic feature of all autocorrection amplifiers. IMD will
show up as sum and difference frequencies between the input sig-
nal and the 4 kHz clock frequency (and its harmonics) and is at a
level similar to or less than the clock feedthrough at the output.
The IMD is also proportional to the closed loop gain of the ampli-
fier. Figure 52 shows the spectral output of an AD8552 configured
as a high gain stage (+60 dB) with a 1 mV input signal applied.
The relative levels of all IMD products and harmonic distortion
add up to produce an output error of 60 dB relative to the input
signal. At unity gain, these would add up to only 120 dB relative
to the input signal.

FREQUENCY kHz

OUTPUT SIGNAL

100

120

OUTPUT SIGNAL
1Vrms @ 200Hz

IMD < 100 Vrms

= +5V

= +60dB

Figure 52. Spectral Analysis of AD855x in High Gain with
a 1 mV Input Signal

For most low frequency applications, the small amount of auto-
zero clock frequency feedthrough will not affect the precision of the
measurement system. Should it be desired, the clock frequency
feedthrough can be reduced through the use of a feedback capaci-
tor around the amplifier. However, this will reduce the bandwidth
of the amplifier. Figures 53a and 53b show a configuration for
reducing the clock feedthrough and the corresponding spectral
analysis at the output. The 3 dB bandwidth of this configuration
is 480 Hz.

= 1mV rms

@ 200Hz

100

100k

3.3nF

Figure 53a. Reducing Autocorrection Clock Noise with a
Feedback Capacitor

FREQUENCY kHz

OUTPUT SIGNAL

100

120

= +5V

= +60dB

Figure 53b. Spectral Analysis Using a Feedback Capacitor

AD8551/AD8552/AD8554

REV. 0

Broadband and External Resistor Noise Considerations

The total broadband noise output from any amplifier is primarily
a function of three types of noise: Input voltage noise from the
amplifier, input current noise from the amplifier and Johnson
noise from the external resistors used around the amplifier. Input
voltage noise, or e

, is strictly a function of the amplifier used.

The Johnson noise from a resistor is a function of the resistance
and the temperature. Input current noise, or i

, creates an equiva-

lent voltage noise proportional to the resistors used around the
amplifier. These noise sources are not correlated with each other
and their combined noise sums in a root-squared-sum fashion.
The full equation is given as:

kTr

i r

n TOTAL

n S

( )

(15)

Where, e

= The input voltage noise of the amplifier,

= The input current noise of the amplifier,

= Source resistance connected to the noninverting
terminal,

k = Boltzmann's constant (1.38 10

-23

J/K)

T = Ambient temperature in Kelvin (K = 273.15 +

The input voltage noise density, e

of the AD855x is 42 nV/

Hz,

and the input noise, i

is 2 fA/

Hz. The e

n, TOTAL

will be domi-

nated by input voltage noise provided the source resistance is less
than 106 k

. With source resistance greater than 106 k

, the

overall noise of the system will be dominated by the Johnson
noise of the resistor itself.

Because the input current noise of the AD855x is very small, i

does not become a dominant term unless r

is greater than 4 G

which is an impractical value of source resistance.

The total noise, e

n, TOTAL

, is expressed in volts per square-root

Hertz, and the equivalent rms noise over a certain bandwidth
can be found as:

n TOTAL

(16)

Where BW is the bandwidth of interest in Hertz.

For a complete treatise on circuit noise analysis, please refer to the
1995 Linear Design Seminar book available from Analog Devices.

Output Overdrive Recovery

The AD855x amplifiers have an excellent overdrive recovery of
only 200

s from either supply rail. This characteristic is particu-

larly difficult for autocorrection amplifiers, as the nulling amplifier
requires a nontrivial amount of time to error correct the main am-
plifier back to a valid output. Figure 23 and Figure 24 show the
positive and negative overdrive recovery time for the AD855x.

The output overdrive recovery for an autocorrection amplifier is
defined as the time it takes for the output to correct to its final
voltage from an overload state. It is measured by placing the
amplifier in a high gain configuration with an input signal that
forces the output voltage to the supply rail. The input voltage is
then stepped down to the linear region of the amplifier, usually
to half-way between the supplies. The time from the input signal
step-down to the output settling to within 100

V of its final

value is the overdrive recovery time. Most competitors' auto-
correction amplifiers require a number of autozero clock cycles
to recover from output overdrive and some can take several
milliseconds for the output to settle properly.

Input Overvoltage Protection

Although the AD855x is a rail-to-rail input amplifier, care should
be taken to ensure that the potential difference between the in-
puts does not exceed +5 V. Under normal operating conditions,
the amplifier will correct its output to ensure the two inputs are at
the same voltage. However, if the device is configured as a com-
parator, or is under some unusual operating condition, the input
voltages may be forced to different potentials. This could cause
excessive current to flow through internal diodes in the AD855x
used to protect the input stage against overvoltage.

If either input exceeds either supply rail by more than 0.3 V, large
amounts of current will begin to flow through the ESD protection
diodes in the amplifier. These diodes are connected between the
inputs and each supply rail to protect the input transistors against
an electrostatic discharge event and are normally reverse-biased.
However, if the input voltage exceeds the supply voltage, these
ESD diodes will become forward-biased. Without current limit-
ing, excessive amounts of current could flow through these diodes
causing permanent damage to the device. If inputs are subject to
overvoltage, appropriate series resistors should be inserted to
limit the diode current to less than 2 mA maximum.

Output Phase Reversal

Output phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. As common-mode volt-
age is moved outside of the common-mode range, the outputs of
these amplifiers will suddenly jump in the opposite direction to the
supply rail. This is the result of the differential input pair shutting
down, causing a radical shifting of internal voltages which results in
the erratic output behavior.

The AD855x amplifier has been carefully designed to prevent
any output phase reversal, provided both inputs are maintained
within the supply voltages. If one or both inputs could exceed
either supply voltage, a resistor should be placed in series with
the input to limit the current to less than 2 mA. This will ensure
the output will not reverse its phase.

Capacitive Load Drive

The AD855x has excellent capacitive load driving capabilities
and can safely drive up to 10 nF from a single +5 V supply.
Although the device is stable, capacitive loading will limit the
bandwidth of the amplifier. Capacitive loads will also increase
the amount of overshoot and ringing at the output. An R-C
snubber network, Figure 54, can be used to compensate the
amplifier against capacitive load ringing and overshoot.

+5V

OUT

200mV p-p

AD855x

4.7nF

0.47 F

Figure 54. Snubber Network Configuration for Driving
Capacitive Loads

Although the snubber will not recover the loss of amplifier band-
width from the load capacitance, it will allow the amplifier to drive
larger values of capacitance while maintaining a minimum of
overshoot and ringing. Figure 55 shows the output of an AD855x
driving a 1 nF capacitor with and without a snubber network.

AD8551/AD8552/AD8554

REV. 0

10 s

100mV

WITH

SNUBBER

WITHOUT

SNUBBER

= +5V

LOAD

= 4.7nF

Figure 55. Overshoot and Ringing are Substantially
Reduced Using a Snubber Network

The optimum value for the resistor and capacitor is a function of
the load capacitance and is best determined empirically since
actual C

LOAD

will include stray capacitances and may differ sub-

stantially from the nominal capacitive load. Table I shows some
snubber network values that can be used as starting points.

Table I. Snubber Network Values for Driving Capacitive Loads

LOAD

1 nF

200

1 nF

4.7 nF

0.47

10 nF

Power-Up Behavior

On power-up, the AD855x will settle to a valid output within 5

Figure 56a shows an oscilloscope photo of the output of the ampli-
fier along with the power supply voltage, and Figure 56b shows
the test circuit. With the amplifier configured for unity gain, the
device takes approximately 5

s to settle to its final output voltage.

This turn-on response time is much faster than most other auto-
correction amplifiers, which can take hundreds of microseconds or
longer for their output to settle.

5 s

OUT

V+

BOTTOM TRACE = 2V/DIV
TOP TRACE = 1V/DIV

Figure 56a. AD855x Output Behavior on Power-Up

= 0V TO +5V

100k

AD855x

100k

OUT

Figure 56b. AD855x Test Circuit for Turn-On Time

APPLICATIONS
A +5 V Precision Strain-Gage Circuit

The extremely low offset voltage of the AD8552 makes it an
ideal amplifier for any application requiring accuracy with high
gains, such as a weigh scale or strain-gage. Figure 57 shows a
configuration for a single supply, precision strain-gage measure-
ment system.

A REF192 provides a +2.5 V precision reference voltage for A2.
The A2 amplifier boosts this voltage to provide a +4.0 V reference
for the top of the strain-gage resistor bridge. Q1 provides the cur-
rent drive for the 350

bridge network. A1 is used to amplify the

output of the bridge with the full-scale output voltage equal to:

(

)

(17)

Where R

is the resistance of the load cell. Using the values given

in Figure 57, the output voltage will linearly vary from 0 V with
no strain to +4.0 V under full strain.

OUT

350

LOAD

CELL

AD8552-A

17.4k

100

0V TO +4.0V

NOTE: USE 0.1% TOLERANCE RESISTORS.

20k

AD8552-B

REF192

12.0k

+5V

+2.5V

+4.0V

40mV

FULL-SCALE

2N2222

EQUIVALENT

17.4k

100

Figure 57. A +5 V Precision Strain-Gage Amplifier

+3 V Instrumentation Amplifier

The high common-mode rejection, high open-loop gain, and
operation down to +3 V of supply voltage makes the AD855x
an excellent choice of op amp for discrete single supply instru-
mentation amplifiers. The common-mode rejection ratio of
the AD855x is greater than 120 dB, but the CMRR of the sys-
tem is also a function of the external resistor tolerances. The
gain of the difference amplifier shown in Figure 58 is given as:

OUT

(18)

AD8551/AD8552/AD8554

REV. 0

OUT

AD855x

, THEN V

OUT

(V1 V2)

Figure 58. Using the AD855x as a Difference Amplifier

In an ideal difference amplifier, the ratio of the resistors are set
exactly equal to:

(19)

Which sets the output voltage of the system to:

A V

OUT

(

)

(20)

Due to finite component tolerance the ratio between the four
resistors will not be exactly equal, and any mismatch results in a
reduction of common-mode rejection from the system. Referring
to Figure 58, the exact common-mode rejection ratio can be ex-
pressed as:

CMRR

R R

(21)

In the 3 op amp instrumentation amplifier configuration shown
in Figure 59, the output difference amplifier is set to unity gain
with all four resistors equal in value. If the tolerance of the resis-
tors used in the circuit is given as

, the worst-case CMRR of

the instrumentation amplifier will be:

CMRR

MIN

(22)

OUT

AD8554-C

AD8554-B

AD8554-A

OUT

= 1 +

2R
R

(V1 V2)

TRIM

Figure 59. A Discrete Instrumentation Amplifier
Configuration

Thus, using 1% tolerance resistors would result in a worst-case
system CMRR of 0.02, or 34 dB. Therefore either high precision
resistors or an additional trimming resistor, as shown in Figure
59, should be used to achieve high common-mode rejection. The
value of this trimming resistor should be equal to the value of R
multiplied by its tolerance. For example, using 10 k

resistors

with 1% tolerance would require a series trimming resistor equal to
100

A High Accuracy Thermocouple Amplifier

Figure 60 shows a K-type thermocouple amplifier configuration
with cold-junction compensation. Even from a +5 V supply, the
AD8551 can provide enough accuracy to achieve a resolution
of better than 0.02

C from 0

C to 500

C. D1 is used as a

temperature measuring device to correct the cold-junction error
from the thermocouple and should be placed as close as possible
to the two terminating junctions. With the thermocouple mea-
suring tip immersed in a zero-degree ice bath, R

should be

adjusted until the output is at 0 V.

Using the values shown in Figure 60, the output voltage will
track temperature at 10 mV/

C. For a wider range of tempera-

ture measurement, R

can be decreased to 62 k

. This will

create a 5 mV/

C change at the output, allowing measurements

of up to 1000

AD8551

0V TO 5.00V
(0 C TO 500 C)

+5V

0.1 F

10 F

124k

453

40.2k

10.7k

2.74k

REF02EZ

0.1 F

+12V

1N4148

53.6

5.62k

+5.000V

K-TYPE

THERMOCOUPLE

40.7 V/ C

200

Figure 60. A Precision K-Type Thermocouple Amplifier
with Cold-Junction Compensation

Precision Current Meter

Because of its low input bias current and superb offset voltage at
single supply voltages, the AD855x is an excellent amplifier for
precision current monitoring. Its rail-to-rail input allows the
amplifier to be used as either a high-side or low-side current
monitor. Using both amplifiers in the AD8552 provides a simple
method to monitor both current supply and return paths for
load or fault detection.

Figure 61 shows a high-side current monitor configuration. Here,
the input common-mode voltage of the amplifier will be at or near
the positive supply voltage. The amplifier's rail-to-rail input provides
a precise measurement even with the input common-mode voltage at
the supply voltage. The CMOS input structure does not draw any
input bias current, ensuring a minimum of measurement error.

The 0.1

resistor creates a voltage drop to the noninverting

input of the AD855x. The amplifier's output is corrected until
this voltage appears at the inverting input. This creates a current
through R

, which in turn flows through R

. The Monitor Output

is given by:

Monitor Output

SENSE

(23)

Using the components shown in Figure 61, the Monitor Output
transfer function is 2.5 V/A.

AD8551/AD8552/AD8554

REV. 0

Figure 62 shows the low-side monitor equivalent. In this circuit,
the input common-mode voltage to the AD8552 will be at or near
ground. Again, a 0.1

resistor provides a voltage drop propor-

tional to the return current. The output voltage is given as:

OUT

SENSE

= + -

(24)

For the component values shown in Figure 62, the output trans-
fer function decreases from V+ at 2.5 V/A.

+3V

0.1 F

SENSE

0.1

V+

Si9433

MONITOR

OUTPUT

+3V

2.49k

100

1/2

AD8552

Figure 61. A High-Side Load Current Monitor

V+

RETURN TO
GROUND

1/2 AD8552

V+

2.49k

OUT

100

0.1

SENSE

Figure 62. A Low-Side Load Current Monitor

Precision Voltage Comparator

The AD855x can be operated open-loop and used as a precision
comparator. The AD855x has less than 50

V of offset voltage

when run in this configuration. The slight increase of offset
voltage stems from the fact that the autocorrection architecture
operates with lowest offset in a closed loop configuration, that
is, one with negative feedback. With 50 mV of overdrive, the de-
vice has a propagation delay of 15

s on the rising edge and

s on the falling edge.

Care should be taken to ensure the maximum differential volt-
age of the device is not exceeded. For more information, please
refer to the section on Input Overvoltage Protection.

SPICE Model

The SPICE macro-model for the AD855x amplifier is given in
Listing 1. This model simulates the typical specifications for the
AD855x, and it can be downloaded from the Analog Devices
website at http://www.analog.com. The schematic of the
macro-model is shown in Figure 63.

Transistors M1 through M4 simulate the rail-to-rail input differ-
ential pairs in the AD855x amplifier. The EOS voltage source in
series with the noninverting input establishes not only the 1

offset voltage, but is also used to establish common-mode and
power supply rejection ratios and input voltage noise. The dif-
ferential voltages from nodes 14 to 16 and nodes 17 to 18 are
reflected to E1, which is used to simulate a secondary pole-zero
combination in the open-loop gain of the amplifier.

The voltage at node 32 is then reflected to G1, which adds an
additional gain stage and, in conjunction with CF, establishes
the slew rate of the model at 0.5 V/

s. M5 and M6 are in a

common-source configuration, similar to the output stage of the
AD855x amplifier. EG1 and EG2 fix the quiescent current in
these two transistors at 100

A, and also help accurately simu-

late the V

OUT

vs. I

OUT

characteristic of the amplifier.

The network around ECM1 creates the common-mode voltage
error, with CCM1 setting the corner frequency for the CMRR
roll-off. The power supply rejection error is created by the
network around EPS1, with CPS3 establishing the corner fre-
quency for the PSRR roll-off. The two current loops around
nodes 80 and 81 are used to create a 42 nV/

Hz noise figure

across RN2. All three of these error sources are reflected to the
input of the op amp model through EOS. Finally, GSY is used
to accurately model the supply current versus supply voltage in-
crease in the AD855x.

This macro-model has been designed to accurately simulate a
number of specifications exhibited by the AD855x amplifier,
and is one of the most true-to-life macro-models available for
any op amp. It is optimized for operation at +27

C. Although

the model will function at different temperatures, it may lose
accuracy with respect to the actual behavior of the AD855x.

AD8551/AD8552/AD8554

REV. 0

SPICE macro-model for the AD855x

* AD8552 SPICE Macro-model
* Typical Values
* 7/99, Ver. 1.0
* TAM / ADSC
*
* Copyright 1999 by Analog Devices
*
* Refer to "README.DOC" file for License
* Statement. Use of this model indicates
* your acceptance of the terms and
* provisions in the License Statement.
*
* Node Assignments
*

noninverting input

inverting input

positive supply

negative supply

output

.SUBCKT AD8552

99 50 45

*
* INPUT STAGE
*
M1 4 7 8 8 PIX L=1E-6 W=355.3E-6
M2 6 2 8 8 PIX L=1E-6 W=355.3E-6
M3 11 7 10 10 NIX L=1E-6 W=355.3E-6
M4 12 2 10 10 NIX L=1E-6 W=355.3E-6
RC1 4 14 9E+3
RC2 6 16 9E+3
RC3 17 11 9E+3
RC4 18 12 9E+3
RC5 14 50 1E+3
RC6 16 50 1E+3
RC7 99 17 1E+3
RC8 99 18 1E+3
C1 14 16 30E-12
C2 17 18 30E-12
I1 99 8 100E-6
I2 10 50 100E-6
V1 99 9 0.3
V2 13 50 0.3
D1 8 9 DX
D2 13 10 DX
EOS 7 1 POLY(3) (22,98) (73,98) (81,98)
+ 1E-6 1 1 1
IOS 1 2 2.5E-12
*
* CMRR 120dB, ZERO AT 20Hz
*
ECM1 21 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 21 22 50E+6
CCM1 21 22 159E-12
RCM2 22 98 50
*
* PSRR=120dB, ZERO AT 1Hz
*
RPS1 70 0 1E+6
RPS2 71 0 1E+6
CPS1 99 70 1E-5
CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 15.9E+6
CPS3 72 73 10E-9
RPS4 73 98 16

* VOLTAGE NOISE REFERENCE OF 42nV/rt(Hz)
*
VN1 80 98 0
RN1 80 98 16.45E-3
HN 81 98 VN1 42
RN2 81 98 1
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY 99 50 (99,50) 48E-6
EVP 97 98 (99,50) 0.5
EVN 51 98 (50,99) 0.5
*
* LHP ZERO AT 7MHz, POLE AT 50MHz
*
E1 32 98 POLY(2) (4,6) (11,12) 0 .5814 .5814
R2 32 33 3.7E+3
R3 33 98 22.74E+3
C3 32 33 1E-12
*
* GAIN STAGE
*
G1 98 30 (33,98) 22.7E-6
R1 30 98 259.1E+6
CF 45 30 45.4E-12
D3 30 97 DX
D4 51 30 DX
*
* OUTPUT STAGE
*
M5 45 46 99 99 POX L=1E-6 W=1.111E-3
M6 45 47 50 50 NOX L=1E-6 W=1.6E-3
EG1 99 46 POLY(1) (98,30) 1.1936 1
EG2 47 50 POLY(1) (30,98) 1.2324 1
*

* MODELS

.MODEL POX PMOS (LEVEL=2,KP=10E-6,

+ VTO=-1,LAMBDA=0.001,RD=8)

.MODEL NOX NMOS (LEVEL=2,KP=10E-6,

+ VTO=1,LAMBDA=0.001,RD=5)

.MODEL PIX PMOS (LEVEL=2,KP=100E-6,

+ VTO=-1,LAMBDA=0.01)

.MODEL NIX NMOS (LEVEL=2,KP=100E-6,

+ VTO=1,LAMBDA=0.01)

.MODEL DX D(IS=1E-14,RS=5)

.ENDS AD8552

REV. 0

C3688810/99

PRINTED IN U.S.A.

AD8551/AD8552/AD8554

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

8-Lead MSOP

(RM Suffix)

0.122 (3.10)
0.114 (2.90)

0.199 (5.05)
0.187 (4.75)

PIN 1

0.0256 (0.65) BSC

0.122 (3.10)
0.114 (2.90)

SEATING

PLANE

0.006 (0.15)
0.002 (0.05)

0.018 (0.46)
0.008 (0.20)

0.043 (1.09)
0.037 (0.94)

0.120 (3.05)
0.112 (2.84)

0.011 (0.28)
0.003 (0.08)

0.028 (0.71)
0.016 (0.41)

33
27

0.120 (3.05)
0.112 (2.84)

8-Lead SOIC

(R Suffix)

0.1968 (5.00)

0.1890 (4.80)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.0688 (1.75)

0.0532 (1.35)

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0500

(1.27)

BSC

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

x 45°

8-Lead TSSOP

(RU Suffix)

0.122 (3.10)
0.114 (2.90)

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

0.0256 (0.65)

BSC

SEATING

PLANE

0.006 (0.15)
0.002 (0.05)

0.0118 (0.30)
0.0075 (0.19)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)
0.020 (0.50)

8
0

14-Lead TSSOP

(RU Suffix)

0.201 (5.10)
0.193 (4.90)

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

SEATING

PLANE

0.006 (0.15)
0.002 (0.05)

0.0118 (0.30)
0.0075 (0.19)

0.0256

(0.65)

BSC

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)
0.020 (0.50)

8
0

14-Lead SOIC

(R Suffix)

0.3444 (8.75)
0.3367 (8.55)

0.2440 (6.20)
0.2284 (5.80)

0.1574 (4.00)
0.1497 (3.80)

PIN 1

SEATING

PLANE

0.0098 (0.25)
0.0040 (0.10)

0.0192 (0.49)
0.0138 (0.35)

0.0688 (1.75)
0.0532 (1.35)

0.0500

(1.27)

BSC

0.0099 (0.25)
0.0075 (0.19)

0.0500 (1.27)
0.0160 (0.41)

8
0

0.0196 (0.50)
0.0099 (0.25)

x 45

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD8554

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD8554