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a
AD8561
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
Ultrafast 7 ns
Single Supply Comparator
PIN CONFIGURATIONS
FEATURES
7 ns Propagation Delay at 5 V
Single Supply Operation: 3 V to 10 V
Low Power
Latch Function
TSSOP Packages
APPLICATIONS
High Speed Timing
Clock Recovery and Clock Distribution
Line Receivers
Digital Communications
Phase Detectors
High Speed Sampling
Read Channel Detection
PCMCIA Cards
Upgrade for LT1016 Designs
GENERAL DESCRIPTION
The AD8561 is a single 7 ns comparator with separate input and
output sections. Separate supplies enable the input stage to be
operated from
5 V dual supplies and +5 V single supplies.
Fast 7 ns propagation delay makes the AD8561 a good choice
for timing circuits and line receivers. Propagation delays for
rising and falling signals are closely matched and track over
temperature. This matched delay makes the AD8561 a good
choice for clock recovery, since the duty cycle of the output will
match the duty cycle of the input.
The AD8561 has the same pinout as the LT1016, with lower
supply current and a wider common-mode input range, which
includes the negative supply rail.
The AD8561 is specified over the industrial (40
C to +85
C)
temperature range. The AD8561 is available in both the 8-lead
plastic DIP, 8-lead TSSOP or narrow SO-8 surface mount
packages.
8-Lead Narrow Body SO
(SO-8)
8-Lead Plastic DIP
(N-8)
8-Lead TSSOP
(RU-8)
IN
IN
V
OUT
GND
LATCH
OUT
1
4
5
8
AD8561
V
8
7
6
5
1
2
3
4
V
IN
IN
OUT
OUT
GND
LATCH
V
AD8561
V
IN
V
IN
OUT
OUT
GND
LATCH
AD8561
2
REV. 0
AD8561SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
2.3
7
mV
40
C
T
A
+85
C
8
mV
Offset Voltage Drift
V
OS
/
T
4
V/
C
Input Bias Current
I
B
V
CM
= 0 V
6
3
A
I
B
40
C
T
A
+85
C
7
3.5
A
Input Offset Current
I
OS
V
CM
= 0 V
4
A
Input Common-Mode Voltage Range
V
CM
0.0
+3.0
V
Common-Mode Rejection Ratio
CMRR
0 V
V
CM
+3.0 V
65
85
dB
Large Signal Voltage Gain
A
VO
R
L
= 10 k
3000
V/V
Input Capacitance
C
IN
3.0
pF
LATCH ENABLE INPUT
Logic "1" Voltage Threshold
V
IH
2.0
1.65
V
Logic "0" Voltage Threshold
V
IL
1.60
0.8
V
Logic "1" Current
I
IH
V
LH
= 3.0 V
1.0
0.3
A
Logic "0" Current
I
IL
V
LL
= 0.3 V
4
2
A
Latch Enable
Pulsewidth
t
PW(E)
6
ns
Setup Time
t
S
1
ns
Hold Time
t
H
1.2
ns
DIGITAL OUTPUTS
Logic "1" Voltage
V
OH
I
OH
= 50
A,
V
IN
> 250 mV
3.5
V
Logic "1" Voltage
V
OH
I
OH
= 3.2 mA,
V
IN
> 250 mV
2.4
3.5
V
Logic "0" Voltage
V
OL
I
OL
= 3.2 mA,
V
IN
> 250 mV
0.25
0.4
V
DYNAMIC PERFORMANCE
Propagation Delay
t
P
200 mV Step with 100 mV Overdrive
6.75
9.8
ns
40
C
T
A
+85
C
8
13
ns
Propagation Delay
t
P
100 mV Step with 5 mV Overdrive
8
ns
Differential Propagation Delay
(Rising Propagation Delay vs.
Falling Propagation Delay)
t
P
100 mV Step with 100 mV Overdrive
1
0.5
2.0
ns
Rise Time
20% to 80%
3.8
ns
Fall Time
80% to 20%
1.5
ns
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
+4.5 V
V+
+5.5 V
50
65
dB
Positive Supply Current
I+
4.5
6.0
mA
40
C
T
A
+85
C
7.5
mA
Ground Supply Current
I
GND
V
O
= 0 V, R
L
=
2.2
3.3
mA
40
C
T
A
+85
C
3.8
mA
Analog Supply Current
I
2.3
4.5
mA
40
C
T
A
+85
C
5.5
mA
NOTES
1
Guaranteed by design.
Specifications subject to change without notice.
(@ V+ = +5.0 V, V = V
GND
= 0 V, T
A
= +25 C unless otherwise noted)
3
REV. 0
AD8561
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
1
7
mV
40
C
T
A
+85
C
8
mV
Offset Voltage Drift
V
OS
/
T
4
V/
C
Input Bias Current
I
B
V
CM
= 0 V
6
3
A
I
B
40
C
T
A
+85
C
7
2.5
A
Input Offset Current
I
OS
V
CM
= 0 V
4
A
Input Common-Mode Voltage Range
V
CM
5.0
+3.0
V
Common-Mode Rejection Ratio
CMRR
5.0 V
V
CM
+3.0 V
65
85
dB
Large Signal Voltage Gain
A
VO
R
L
= 10 k
3000
V/V
Input Capacitance
C
IN
3.0
pF
LATCH ENABLE INPUT
Logic "1" Voltage Threshold
V
IH
2.0
1.65
V
Logic "0" Voltage Threshold
V
IL
1.60
0.8
V
Logic "1" Current
I
IH
V
LH
= 3.0 V
1
0.5
20
A
Logic "0" Current
I
IL
V
LL
= 0.3 V
4
2
20
A
Latch Enable
Pulsewidth
t
PW(E)
6
ns
Setup Time
t
S
1.0
ns
Hold Time
t
H
1.2
ns
DIGITAL OUTPUTS
Logic "1" Voltage
V
OH
I
OH
= 3.2 mA
2.6
3.5
V
Logic "0" Voltage
V
OL
I
OL
= 3.2 mA
0.2
0.3
V
DYNAMIC PERFORMANCE
Propagation Delay
t
P
200 mV Step with 100 mV Overdrive
6.5
9.8
ns
40
C
T
A
+85
C
8
13
ns
Propagation Delay
t
P
100 mV Step with 5 mV Overdrive
7
ns
Differential Propagation Delay
(Rising Propagation Delay vs.
Falling Propagation Delay)
t
P
100 mV Step with 100 mV Overdrive
1
0.5
2
ns
Rise Time
20% to 80%
3.8
ns
Fall Time
80% to 20%
1.5
ns
Dispersion
1
ns
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
4.5 V
V
CC
and V
EE
5.5 V
55
70
dB
Supply Current
V
O
= 0 V, R
L
=
Positive Supply Current
I+
4.7
6.5
mA
40
C
T
A
+85
C
7.5
mA
Ground Supply Current
I
GND
V
O
= 0 V, R
L
=
2.2
3.3
mA
40
C
T
A
+85
C
3.8
mA
Negative Supply Current
I
2.4
4.5
mA
40
C
T
A
+85
C
5.5
mA
NOTES
1
Guaranteed by design.
Specifications subject to change without notice.
(@ V+
= +5.0 V, V = V
GND
= 0 V, V = 5 V, T
A
= +25 C unless otherwise noted)
4
REV. 0
AD8561SPECIFICATIONS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8561 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
7
mV
Input Bias Current
I
B
V
CM
= 0 V
6
3.0
A
I
B
40
C
T
A
+85
C
7
4
A
Input Common-Mode Voltage Range
V
CM
0
+1.5
V
Common-Mode Rejection Ratio
CMRR
0.1 V
V
CM
1.5 V
60
dB
OUTPUT CHARACTERISTICS
Output High Voltage
V
OH
I
OH
= 3.2 mA, V
IN
> 250 mV
1.2
1
V
Output Low Voltage
V
OL
I
OL
= +3.2 mA, V
IN
> 250 mV
0.3
V
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
+2.7 V
V
CC
, V
EE
+6 V
40
dB
Supply Currents
V
O
= 0 V, R
L
=
V+ Supply Current
I+
4.0
4.5
mA
40
C
T
A
+85
C
5.5
mA
Ground Supply Current
I
GND
1.6
2.5
mA
40
C
T
A
+85
C
3.0
mA
V Supply Current
I
2.4
3.3
mA
40
C
T
A
+85
C
3.8
mA
DYNAMIC PERFORMANCE
Propagation Delay
t
P
100 mV Step with 20 mV Overdrive
2
8.5
9.8
ns
NOTES
1
Output high voltage without pull-up resistor. It may be useful to have a pull-up resistor to V+ for 3 V operation.
2
Guaranteed by design.
Specifications subject to change without notice.
(@ V+
= +3.0 V, V = V
GND
= 0 V, T
A
= +25 C unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS
Total Analog Supply Voltage . . . . . . . . . . . . . . . . . . . . . +14 V
Digital Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +14 V
Analog Positive SupplyDigital Positive Supply . . . . . 600 mV
Input Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .
8 V
Output Short-Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
N, R, RU Package . . . . . . . . . . . . . . . . . . 65
C to +150
C
Operating Temperature Range . . . . . . . . . . . 40
C to +85
C
Junction Temperature Range
N, R, RU Package . . . . . . . . . . . . . . . . . . 65
C to +150
C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300
C
Package Type
JA
2
JC
Units
8-Lead Plastic DIP (N)
103
43
C/W
8-Lead SO (R)
158
43
C/W
8-Lead TSSOP
240
43
C/W
NOTES
1
The analog input voltage is equal to
7 V or the analog supply voltage, whichever
is less.
2
JA
is specified for the worst case conditions, i.e.,
JA
is specified for device in socket
for P-DIP and
JA
is specified for device soldered in circuit board for SOIC and
TSSOP packages.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Options
AD8561AN
40
C to +85
C
8-Lead Plastic DIP
N-8
AD8561ARU
40
C to +85
C
8-Lead Thin Shrink Small Outline
RU-8
AD8561AR
40
C to +85
C
8-Lead Small Outline IC
SO-8
WARNING!
ESD SENSITIVE DEVICE
AD8561
5
REV. 0
Typical Performance Characteristics
(V+ = +5 V, V = 0 V, T
A
= +25 C unless otherwise noted)
DIFFERENTIAL INPUT VOLTAGE mV
OUTPUT VOLTAGE Volts
5
4
0
2.5 2.0
1.5
1.5 1.0 0.5
0
0.5
1.0
3
2
1
V
S
= 5V, SINGLE SUPPLY
+125 C
+25 C
40 C
Figure 1. Output Voltage vs. Differen-
tial Input Voltage
LOAD CAPACITANCE pF
PROPAGATION DELAY ns
20
15
0
0
10
50
20
30
40
10
5
V
S
= 5V, SINGLE SUPPLY
STEP SIZE = 100mV
OVERDRIVE LOAD = 5mV
t
PD
FALLING EDGE
t
PD
+
FALLING EDGE
Figure 4. Propagation Delay vs. Load
Capacitance
TEMPERATURE C
PROPAGATION DELAY ns
20
15
0
50
25
50
0
25
10
5
V
S
= +5V, SINGLE SUPPLY
STEP SIZE = 100mV
OVERDRIVE = 5mV,
LOAD CAPACITANCE = 10pF
75
100
125
Figure 7. Propagation Delay vs.
Temperature
INPUT VOLTAGE mV
NUMBER OF COMPARATORS
500
400
0
5
5
4 3 2 1
0
1
2
3
4
300
200
100
Figure 2. Typical Distribution of Input
Offset Voltage
SOURCE RESISTANCE k
PROPAGATION DELAY ns
40
30
0
0
0.5
2
1
1.5
20
10
V
S
= 5V, SINGLE SUPPLY
OVERDRIVE = 10mV
CAPACITANCE LOAD = 10pF
T
A
= +25 C
100mV
STEP SIZE = 800mV
400mV
200mV
Figure 5. Propagation Delay vs.
Source Resistance
COMMON-MODE VOLTAGE Volts
PROPAGATION DELAY ns
20
15
0
0
1
5
2
3
4
10
5
V
S
= 5V
STEP SIZE = 100mV
OVERDRIVE = 5mV
LOAD CAPACITANCE = 10pF
+25 C
40 C
+125 C
Figure 8. Propagation Delay vs. V
CM
OVERDRIVE mV
PROPAGATION DELAY ns
20
15
0
0
10
50
20
30
40
10
5
V
S
= 5V, SINGLE SUPPLY
STEP SIZE = 100mV
CAPACITANCE LOAD = 10pF
T
A
= +25 C
Figure 3. Propagation Delay vs.
Overdrive
SUPPLY VOLTAGE Volts
PROPAGATION DELAY ns
20
15
0
4.5
4.75
5.5
5
5.25
10
5
SINGLE SUPPLY,
STEP SIZE = 100mV
OVERDRIVE = 5mV
CAPACITANCE LOAD = 10pF
T
A
= +25 C
Figure 6. Propagation Delay vs. Posi-
tive Supply Voltage
TEMPERATURE C
TIME ns
4
3
0
50
25
125
0
25
50
75
100
2
1
HOLD TIME
SET-UP TIME
Figure 9. Latch Setup-and-Hold Time
vs. Temperature
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