ChipFind - документация

Электронный компонент: AD8608

Скачать:  PDF   ZIP

Document Outline

Precision Low Noise CMOS Rail-to-Rail
Input/Output Operational Amplifiers
AD8605/AD8606/AD8608
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
Low offset voltage: 65 V maximum
Low input bias currents: 1 pA maximum
Low noise: 8 nV/Hz
Wide bandwidth: 10 MHz
High open-loop gain: 120 dB
Unity gain stable
Single-supply operation: 2.7 V to 5.5 V
MicroCSPTM
GENERAL DESCRIPTION
The AD8605, AD8606, and AD8608
1
are single, dual, and quad
rail-to-rail input and output, single-supply amplifiers. They
feature very low offset voltage, low input voltage and current
noise, and wide signal bandwidth. They use Analog Devices'
patented DigiTrim trimming technique, which achieves
superior precision without laser trimming.
The combination of low offsets, low noise, very low input bias
currents, and high speed makes these amplifiers useful in a
wide variety of applications. Filters, integrators, photodiode
amplifiers, and high impedance sensors all benefit from the
combination of performance features. Audio and other ac
applications benefit from the wide bandwidth and low
distortion. Applications for these amplifiers include optical
control loops, portable and loop-powered instrumentation,
and audio amplification for portable devices.
The AD8605, AD8606, and AD8608 are specified over the
extended industrial temperature range (-40C to +125C). The
AD8605 single is available in the 5-lead SOT-23 and 5-bump
MicroCSP packages. The 5-bump MicroCSP offers the smallest
available footprint for any surface-mount operational amplifier.
The AD8606 dual is available in an 8-lead MSOP package and a
narrow SOIC surface-mount package. The AD8608 quad is
available in a 14-lead TSSOP and a narrow 14-lead SOIC
package. MicroCSP, SOT, MSOP, and TSSOP versions are
available in tape and reel only.
1
Protected by U.S. Patent No. 5,969,657; other patents pending.
APPLICATIONS
Photodiode amplification
Battery-powered instrumentation
Multipole filters
Sensors
Barcode scanners
Audio
FUNCTIONAL BLOCK DIAGRAMS
1
2
3
5
4 IN
+IN
V+
OUT
AD8605
V
02731-D-001
1
2
3
4
8
7
6
5
AD8608
IN A
V
+IN A
OUT B
IN B
V+
+IN B
OUT A
02731-D-005
Figure 1. 5-Lead SOT-23 (RT Suffix)
Figure 2. 8-Lead SOIC (R Suffix)
AD8605 ONLY
OUT
V+
V
+IN
IN
1
3
5
4
2
TOP VIEW
(BUMP SIDE DOWN)
02731-D-006
IN A
+IN A
V+
+IN B
IN B
OUT B
OUT D
IN D
+IN D
V
+IN C
IN C
OUT C
OUT A
AD8608
1
2
3
4
5
6
7
14
13
12
11
10
9
8
02731-D-004
Figure 3. 5-Bump MicroCSP
(CB Suffix)
Figure 4. 14-Lead SOIC (R Suffix)
IN A
+IN A
V
OUT B
IN B
+IN B
V+
1
8
AD8606
OUT A
4
5
02731-D-003
OUT A
IN A
+IN A
V+
+IN B
IN B
OUT B
IN D
+IN D
V
OUT D
IN C
OUT C
+IN C
14
8
1
7
AD8608
02731-D-002
Figure 5. 8-Lead MSOP (RM Suffix)
Figure 6. 14-Lead TSSOP (RU Suffix)
AD8605/AD8606/AD8608
Rev. D | Page 2 of 20
TABLE OF CONTENTS
5 V Electrical Specifications ............................................................ 3
2.7 V Electrical Specifications ......................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Application Information................................................................ 13
Output Phase Reversal............................................................... 13
Maximum Power Dissipation ................................................... 13
Input Overvoltage Protection ................................................... 13
THD + Noise............................................................................... 13
Total Noise Including Source Resistors ................................... 14
Channel Separation.................................................................... 14
Capacitive Load Drive ............................................................... 14
Light Sensitivity .......................................................................... 15
MicroCSP Assembly Considerations....................................... 15
I-V Conversion Applications ........................................................ 16
Photodiode Preamplifier Applications .................................... 16
Audio and PDA Applications ................................................... 16
Instrumentation Amplifiers ...................................................... 17
D/A Conversion ......................................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
5/04--Data Sheet Changed from Rev. C to Rev. D
Updated Format............................................................. Universal
Edit to Light Sensitivity Section ............................................... 16
Updated Outline Dimensions ................................................... 19
Changes to Ordering Guide ...................................................... 20
7/03--Data Sheet Changed from Rev. B to Rev. C
Changes to Features....................................................................... 1
Change to General Description ................................................... 1
Addition to Functional Block Diagrams .................................... 1
Addition to Absolute Maximum Ratings ................................... 4
Addition to Ordering Guide ........................................................ 4
Change to Equation In Maximum Power Dissipation
Section........................................................................................ 11
Added Light Sensitivity Section................................................. 12
Added New Figure 8 and Renumbered Subsequent Figures . 13
Added New MicroCSP Assembly Considerations Section .... 13
Changes to Figure 9..................................................................... 13
Change to Equation in Photodiode Preamplifier
Applications Section ................................................................ 13
Changes to Figure 12................................................................... 14
Change to Equation in D/A Conversion Section .................... 14
Updated Outline Dimensions ................................................... 15
3/03--Data Sheet Changed from Rev. A to Rev. B
Changes to Functional Block Diagram....................................... 1
Changes to Absolute Maximum Ratings .................................... 4
Changes to Ordering Guide ....................................................... 4
Changes to Figure 9 .................................................................... 13
Updated Outline Dimensions.................................................... 15
11/02--Data Sheet Changed from Rev. 0 to Rev. A
Change to Electrical Characteristics ........................................... 2
Changes to Absolute Maximum Ratings .................................... 4
Changes Ordering Guide ............................................................. 4
Change to TPC 6 .......................................................................... 5
Updated Outline Dimensions.................................................... 15
AD8605/AD8606/AD8608
Rev. D | Page 3 of 20
5 V ELECTRICAL SPECIFICATIONS
Table 1. @ V
S
= 5 V, V
CM
= V
S
/2, T
A
= 25C, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
OS
AD8605/AD8606
V
S
= 3.5 V, V
CM
= 3 V
20
65
V
AD8608
V
S
= 3.5 V, V
CM
= 2.7 V
20
75
V
V
S
= 5 V, V
CM
= 0 V to 5 V
80
300
V
-40C < T
A
< +125C
750
V
Input Bias Current
I
B
0.2
1
pA
AD8605/AD8606
-40C < T
A
< +85C
50
pA
AD8605/AD8606
-40C < T
A
< +125C
250
pA
AD8608
-40C < T
A
< +85C
100
pA
AD8608
-40C < T
A
< +125C
300
pA
Input Offset Current
I
OS
0.1
0.5
pA
-40C < T
A
< +85C
20
pA
-40C < T
A
< +125C
75
pA
Input Voltage Range
0
5
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 0 V to 5 V
85
100
dB
-40C < T
A
< +125C
75
90
dB
Large Signal Voltage Gain
A
VO
V
O
= 0.5 V to 4.5 V
300
1,000
V/mV
R
L
= 2 k, V
CM
= 0 V
Offset Voltage Drift
AD8605/AD8606
V
OS
/T
1
4.5
V/C
AD8608
V
OS
/T
1.5
6.0
V/C
INPUT CAPACITANCE
Common-Mode Input Capacitance
8.8
pF
Differential Input Capacitance
2.59
pF
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
I
L
= 1 mA
4.96
4.98
V
I
L
= 10 mA
4.7
4.79
V
-40C < T
A
< +125C
4.6
V
Output Voltage Low
V
OL
I
L
= 1 mA
20
40
mV
I
L
= 10 mA
170
210
mV
-40C < T
A
< +125C
290
mV
Output Current
I
OUT
80
mA
Closed-Loop Output Impedance
Z
OUT
f = 1 MHz, A
V
= 1
10
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
AD8605/AD8606
V
S
= 2.7 V to 5.5 V
80
95
dB
AD8608
V
S
= 2.7 V to 5.5 V
77
92
dB
-40C < T
A
< +125C
70
90
dB
Supply Current/Amplifier
I
SY
V
O
= 0 V
1
1.2
mA
-40C < T
A
< +125C
1.4
mA
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 2 k
5
V/s
Settling Time
t
S
To 0.01%, 0 V to 2 V step
< 1
s
Full Power Bandwidth
BW
P
< 1% distortion
360
kHz
Gain Bandwidth Product
GBP
10
MHz
Phase Margin
O
65
Degrees
AD8605/AD8606/AD8608
Rev. D | Page 4 of 20
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
NOISE PERFORMANCE
Peak-to-Peak Noise
e
n
p-p
f = 0.1 Hz to 10 Hz
2.3
3.5
V p-p
Voltage Noise Density
e
n
f = 1 kHz
8
12
nV/Hz
Voltage Noise Density
e
n
f = 10 kHz
6.5
nV/Hz
Current Noise Density
i
n
f = 1 kHz
0.01
pA/Hz
AD8605/AD8606/AD8608
Rev. D | Page 5 of 20
2.7 V ELECTRICAL SPECIFICATIONS
Table 2. @ V
S
= 2.7 V, V
CM
= V
S
/2, T
A
= 25C, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
OS
AD8605/AD8606
V
S
= 3.5 V, V
CM
= 3 V
20
65
V
AD8608
V
S
= 3.5 V, V
CM
= 2.7 V
20
75
V
V
S
= 2.7 V, V
CM
= 0 V to 2.7 V
80
300
V
-40C < T
A
< +125C
750
V
Input Bias Current
I
B
0.2
1
pA
AD8605/AD8606
-40C < T
A
< +85C
50
pA
AD8605/AD8606
-40C < T
A
< +125C
250
pA
AD8608
-40C < T
A
< +85C
100
pA
AD8608
-40C < T
A
< +125C
300
pA
Input Offset Current
I
OS
0.1
0.5
pA
-40C < T
A
< +85C
20
pA
-40C < T
A
< +125C
75
pA
Input Voltage Range
0
2.7
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 0 V to 2.7 V
80
95
dB
-40C < T
A
< +125C
70
85
dB
Large Signal Voltage Gain
A
VO
RL = 2 k, V
O
= 0.5 V to 2.2 V
110
350
V/mV
Offset Voltage Drift
AD8605/AD8606
V
OS
/T
1
4.5
V/C
AD8608
V
OS
/T
1.5
6.0
V/C
INPUT CAPACITANCE
Common-Mode Input Capacitance
8.8
pF
Differential Input Capacitance
2.59
pF
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
I
L
= 1 mA
2.6
2.66
V
-40C < T
A
< +125C
2.6
V
Output Voltage Low
V
OL
I
L
= 1 mA
25
40
mV
-40C < T
A
< +125C
50
mV
Output Current
I
OUT
30
mA
Closed-Loop Output Impedance
Z
OUT
f = 1 MHz, A
V
= 1
12
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
AD8605/AD8606
V
S
= 2.7 V to 5.5 V
80
95
dB
AD8608
V
S
= 2.7 V to 5.5 V
77
92
dB
-40C < T
A
< +125C
70
90
dB
Supply Current/Amplifier
ISY
V
O
= 0 V
1.15
1.4
mA
-40C < T
A
< +125C
1.5
mA
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 2 k
5
V/s
Settling Time
t
S
To 0.01%, 0 V to 1 V step
< 0.5
s
Gain Bandwidth Product
GBP
9
MHz
Phase Margin
O
50
Degrees
NOISE PERFORMANCE
Peak-to-Peak Noise
e
n
p-p
f = 0.1 Hz to 10 Hz
2.3
3.5
V p-p
Voltage Noise Density
e
n
f = 1 kHz
8
12
nV/Hz
Voltage Noise Density
e
n
f = 10 kHz
6.5
nV/Hz
Current Noise Density
i
n
f = 1 kHz
0.01
pA/Hz
AD8605/AD8606/AD8608
Rev. D | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter Rating
Supply Voltage
6 V
Input Voltage
GND to V
S
Differential Input Voltage
6 V
Output Short-Circuit Duration
to GND
Observe Derating Curves
Storage Temperature Range
All Packages
-65C to +150C
Operating Temperature Range
AD8605/AD8606/AD8608
-40C to +125C
Junction Temperature Range
All Packages
-65C to +150C
Lead Temperature Range
(Soldering, 60 sec)
300C
Table 4. Package Type
Package Type
JA
1
JC
Unit
5-Bump MicroCSP (CB)
220
220
C/W
5-Lead SOT-23 (RT)
230
92
C/W
8-Lead MSOP (RM)
210
45
C/W
8-Lead SOIC (R)
158
43
C/W
14-Lead SOIC (R)
120
36
C/W
14-Lead TSSOP (RU)
180
35
C/W
1
JA
is specified for worst-case conditions, i.e.,
JA
is specified for device in
socket for PDIP packages;
JA
is specified for device soldered onto a circuit
board for surface-mount packages.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8605/AD8606/AD8608
Rev. D | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET VOLTAGE (mV)
NUM
B
ER OF AM
PLIFIERS
4500
4000
0
2000
1500
1000
500
3000
2500
3500
300
200
100
0
100
200
300
V
S
= 5V
T
A
= 25C
V
CM
= 0V TO 5V
02731-D-007
Figure 7. Input Offset Voltage Distribution
TCVOS (mV/C)
12
0
4.8
0.4
NUMBE
R OF AMP
L
IFIE
RS
0.8
1.6
2.4
3.2
4.0
16
8
4
24
20
4.4
V
S
= 5V
T
A
= 40C TO +125C
V
CM
= 2.5V
0
1.2
2.0
2.8
3.6
0
2
7
3
1
-
D
-
0
0
8
Figure 8. AD8608 Input Offset Voltage Drift Distribution
TCVOS (mV/C)
20
10
0
2.6
0.2
NUMBE
R OF AMP
L
IFIE
RS
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
14
6
2
2.2 2.4
12
16
8
4
18
0
V
S
= 5V
T
A
= 40C TO +125C
V
CM
= 2.5V
02731-D-009
Figure 9. AD8605/AD8606 Input Offset Voltage Drift Distribution
300
200
300
IN
PU
T OFFSET VOLTA
G
E (
m
V)
100
0
200
100
V
S
= 5V
T
A
= 25C
COMMON-MODE VOLTAGE (V)
02731-D-010
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
(200 Units, 5 Wafer Lots, Including Process Skews)
TEMPERATURE (C)
360
160
0
0
125
25
INP
U
T BIAS
CURRE
NT (pA)
50
75
100
240
80
200
280
120
40
320
AD8605/AD8606
AD8608
V
S
= 2.5V
02731-D-011
Figure 11. Input Bias Current vs. Temperature
LOAD CURRENT (mA)
1k
10
0.1
0.001
10
0.01
V
SY
V
OUT
(mV
)
0.1
1
100
1
SINK
SOURCE
V
S
= 5V
T
A
= 25C
02731-D-012
Figure 12. Output Voltage to Supply Rail vs. Load Current
AD8605/AD8606/AD8608
Rev. D | Page 8 of 20
TEMPERATURE (C)
5.000
4.950
4.700
OUTPUT VOLTAGE (
V
)
4.850
4.750
4.900
4.800
V
OH
@ 1mA LOAD
V
S
= 5V
V
OH
@ 10mA LOAD
40
25 10
5
20
35
50
65
80
95
110 125
02731-D-013
Figure 13. Output Voltage Swing vs. Temperature
0.250
0
0.150
0.050
0.200
0.100
TEMPERATURE (C)
OUTPUT VOLTAGE (
V
)
V
OH
@ 1mA LOAD
V
S
= 5V
V
OH
@ 10mA LOAD
40
25 10
5
20
35
50
65
80
95
110 125
02731-D-014
Figure 14. Output Voltage Swing vs. Temperature
GAIN (
d
B)
100
80
100
60
40
20
0
20
40
60
80
225
180
225
135
90
45
0
45
90
135
180
PH
A
SE (
D
egrees)
FREQUENCY (Hz)
10k
100M
100k
1M
10M
V
S
= 2.5V
R
L
= 2kV
C
L
= 20pF
f
M
= 648
02731-D-015
Figure 15. Open-Loop Gain and Phase vs. Frequency
FREQUENCY (Hz)
6
5
0
1k
10M
10k
OUTPUT SWING (V p-p)
100k
1M
4
3
1
2
V
S
= 5V
V
IN
= 4.9V p-p
T
A
= 25C
R
L
= 2k
A
V
= 1
02731-D-016
Figure 16. Closed-Loop Output Voltage Swing
FREQUENCY (Hz)
100
90
0
1k
100M
10k
OUTP
UT IMP
E
DANCE
(
)
100k
1M
10M
80
70
20
60
50
30
10
40
V
S
= 2.5V
A
V
= 100
A
V
= 1
A
V
= 10
02731-D-017
Figure 17. Output Impedance vs. Frequency
FREQUENCY (Hz)
10k
CMRR (dB)
100k
1M
20
120
1k
10M
90
80
70
60
50
40
30
110
100
V
S
= 2.5V
02731-D-018
Figure 18. Common-Mode Rejection Ratio vs. Frequency
AD8605/AD8606/AD8608
Rev. D | Page 9 of 20
FREQUENCY (Hz)
140
80
60
1k
10M
10k
P
S
RR (dB)
100k
1M
40
0
40
100
120
60
20
20
V
S
= 5V
02731-D-019
Figure 19. PSRR vs. Frequency
CAPACITANCE (pF)
45
40
0
10
1k
100
SM
A
L
L SIGN
A
L
OVER
SH
OOT (
%
)
35
30
10
25
20
15
5
V
S
= 5V
R
L
=
T
A
= 25C
A
V
= 1
+OS
OS
02731-D-020
Figure 20. Small Signal Overshoot vs. Load Capacitance
TEMPERATURE (C)
2.0
1.5
S
U
P
P
L
Y
CURRE
NT/AMP
LIFIE
R
(mA)
1.0
1.5
0.5
1.0
0.5
0
50
125
35 20
95
110
5
20
35
50
65
80
V
S
= 2.7V
V
S
= 5V
02731-D-021
Figure 21. Supply Current vs. Temperature
SUPPLY VOLTAGE (V)
1.0
0.4
0
S
U
P
P
L
Y
CURRE
NT/AMP
LIFIE
R
(mA)
0.9
0.5
0.3
0.1
0.7
0.6
0.2
0.8
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
02731-D-022
Figure 22. Supply Current vs. Supply Voltage
TIME (1s/DIV)
VOLTA
GE N
O
ISE (
1
V/D
I
V)
V
S
= 5V
02731-D-023
Figure 23. 0.1 Hz to 10 Hz Input Voltage Noise
TIME (200ns/DIV)
VOLTA
G
E (
50mV/D
I
V)
V
S
= 2.5V
R
L
= 10k
C
L
= 200pF
A
V
= 1
02731-D-024
Figure 24. Small Signal Transient Response
AD8605/AD8606/AD8608
Rev. D | Page 10 of 20
TIME (400ns/DIV)
VOLTA
GE (
1
V/D
I
V)
V
S
= 2.5V
R
L
= 10k
C
L
= 200pF
A
V
= 1
02731-D-025
Figure 25. Large Signal Transient Response
TIME (400ns/DIV)
+2.5V
50mV
0V
0V
V
S
= 2.5V
R
L
= 10k
A
V
= 100
V
IN
= 50mV
02731-D-026
Figure 26. Negative Overload Recovery
V
S
= 2.5V
R
L
= 10k
A
V
= 100
V
IN
= 50mV
TIME (400ns/DIV)
+2.5V
50mV
0V
0V
02731-D-027
Figure 27. Positive Overload Recovery
FREQUENCY (kHz)
36
20
4
32
28
12
8
24
16
V
S
= 2.5V
VOLTA
GE N
O
ISE D
E
N
S
ITY (
n
V/
Hz)
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
02731-D-028
Figure 28. Voltage Noise Density
0
6.7
20.1
13.4
26.8
40.2
33.5
53.6
46.9
FREQUENCY (kHz)
V
S
= 2.5V
VOLTA
GE N
O
ISE D
E
N
S
ITY (
n
V/
Hz)
0
1
9
8
7
6
5
4
3
2
1
02731-D-029
0
Figure 29. Voltage Noise Density
0
14.9
44.7
29.8
59.6
99.4
74.5
119.2
104.3
FREQUENCY (Hz)
V
S
= 2.5V
VOLTA
GE N
O
ISE D
E
N
S
ITY (
n
V/
Hz)
0
100
90
80
70
60
50
40
30
20
10
02731-D-030
Figure 30. Voltage Noise Density
AD8605/AD8606/AD8608
Rev. D | Page 11 of 20
1800
1600
0
NUMBE
R OF AMP
L
IFIE
RS
800
600
400
200
1200
1000
1400
OFFSET VOLTAGE (
V)
300
200
100
200
300
V
S
= 2.7V
T
A
= 25C
V
CM
= 0V TO 2.7V
0
100
02731-D-031
Figure 31. Input Offset Voltage Distribution
COMMON-MODE VOLTAGE (V)
300
200
300
0
2.7
IN
PU
T OFFSET VOLTA
GE (
V)
100
0
200
100
1.8
0.9
0
V
S
= 2.7V
T
A
= 25C
02731-D-032
Figure 32. Input Offset Voltage vs. Common-Mode Voltage
(200 Units, 5 Wafer Lots, Including Process Skews)
LOAD CURRENT (mA)
1k
10
0.1
0.001
10
0.01
OUTPUT VOLTAGE (mV)
0.1
1
100
1
SOURCE
SINK
V
S
= 2.7V
T
A
= 25C
02731-D-033
Figure 33. Output Voltage to Supply Rail vs. Load Current
TEMPERATURE (C)
2.680
2.675
2.650
5
20
125
50
35
OUTPUT VOLTAGE (
V
)
65
80
95
110
2.665
2.655
2.670
2.660
10
25
40
V
S
= 2.7V
V
OH
@ 1mA LOAD
02731-D-034
Figure 34. Output Voltage Swing vs. Temperature
0.045
0.025
0
0.035
0.015
0.005
0.030
0.040
0.020
0.010
TEMPERATURE (C)
5
20
125
50
35
OUTPUT VOLTAGE (V)
65
80
95
110
10
25
40
V
S
= 2.7V
V
OH
@ 1mA LOAD
02731-D-035
Figure 35. Output Voltage Swing vs. Temperature
FREQUENCY (Hz)
10k
100M
100k
GAIN (
d
B)
100
80
100
60
40
20
0
20
40
60
80
225
180
225
135
90
45
0
45
90
135
180
PH
A
SE (
D
egrees)
1M
10M
V
S
= 1.35V
R
L
= 2k
C
L
= 20pF
f
M
= 52.5
02731-D-036
Figure 36. Open-Loop Gain and Phase vs. Frequency
AD8605/AD8606/AD8608
Rev. D | Page 12 of 20
FREQUENCY (Hz)
3.0
2.5
0
1k
10M
10k
OUTPUT SWING (V p-p)
100k
1M
2.0
1.5
0.5
1.0
V
S
= 2.7V
V
IN
= 2.6V p-p
T
A
= 25C
R
L
= 2k
A
V
= 1
02731-D-037
Figure 37. Closed-Loop Output Voltage Swing vs. Frequency
FREQUENCY (Hz)
100
90
0
1k
100M
10k
OUTP
UT IMP
E
DANCE
(
)
100k
1M
10M
80
70
20
60
50
30
10
40
A
V
= 100
A
V
= 10
A
V
= 1
V
S
= 1.35V
02731-D-038
Figure 38. Output Impedance vs. Frequency
CAPACITANCE (pF)
60
50
0
10
1k
100
SM
A
LL SIGN
A
L
OVER
SH
OOT (
%
)
30
20
10
40
OS
+OS
V
S
= 2.7V
T
A
= 25C
A
V
= 1
02731-D-039
Figure 39. Small Signal Overshoot vs. Load Capacitance
TIME (1s/DIV)
V
S
= 2.7V
VOLTA
GE N
O
ISE (
1
V/D
I
V)
02731-D-040
Figure 40. 0.1 Hz to 10 Hz Input Voltage Noise
TIME (200ns/DIV)
VOLTA
G
E (
50mV/D
I
V)
V
S
= 1.35V
R
L
= 10k
C
L
= 200pF
A
V
= 1
02731-D-041
Figure 41. Small Signal Transient Response
TIME (400ns/DIV)
VOLTA
GE (
1
V/D
I
V)
V
S
= 1.35V
R
L
= 10k
C
L
= 200pF
A
V
= 1
02731-D-042
Figure 42. Large Signal Transient Response
AD8605/AD8606/AD8608
Rev. D | Page 13 of 20
APPLICATION INFORMATION
OUTPUT PHASE REVERSAL
Phase reversal is defined as a change in polarity at the output of
the amplifier when a voltage that exceeds the maximum input
common-mode voltage drives the input.
Phase reversal can cause permanent damage to the amplifier; it
may also cause system lockups in feedback loops. The AD8605
does not exhibit phase reversal even for inputs exceeding the
supply voltage by more than 2 V.
TIME (4
s/DIV)
VOLTA
G
E (
2
V/D
I
V)
V
OUT
V
IN
V
S
= 2.5V
V
IN
= 5V p-p
A
V
= 1
R
L
= 10k
02731-D-043
Figure 43. No Phase Reversal
MAXIMUM POWER DISSIPATION
Power dissipated in an IC causes the die temperature to
increase. This can affect the behavior of the IC and the
application circuit performance.
The absolute maximum junction temperature of the AD8605/
AD8606/AD8608 is 150C. Exceeding this temperature could
cause damage or destruction of the device. The maximum
power dissipation of the amplifier is calculated according to
the following formula:
JA
A
J
DISS
T
T
P
-
=
where:
T
J
= junction temperature
T
A
= ambient temperature
JA
= junction to-ambient-thermal resistance
Figure 44 compares the maximum power dissipation with
temperature for the various AD8605 family packages.
TEMPERATURE (C)
1.0
0.8
0
0
100
20
POW
E
R
D
I
SSIPA
TION
(
W
)
40
60
80
0.6
0.4
0.2
SOIC-14
2.0
1.8
1.6
1.4
1.2
SOIC-8
SOT-23
MSOP
02731-D-044
TSSOP
Figure 44. Maximum Power Dissipation vs. Temperature
INPUT OVERVOLTAGE PROTECTION
The AD8605 has internal protective circuitry. However, if the
voltage applied at either input exceeds the supplies by more
than 2.5 V, external resistors should be placed in series with the
inputs. The resistor values can be determined by the formula
(
)
(
)
mA
R
V
V
S
S
IN
5
200
+
-
The remarkable low input offset current of the AD8605 (<1 pA)
allows the use of larger value resistors. With a 10 k resistor at
the input, the output voltage has less than 10 nV of error
voltage. A 10 k resistor has less than 13 nV/Hz of thermal
noise at room temperature.
THD + NOISE
Total harmonic distortion is the ratio of the input signal in V
rms to the total harmonics in V rms throughout the spectrum.
Harmonic distortion adds errors to precision measurements
and adds unpleasant sonic artifacts to audio systems.
The AD8605 has a low total harmonic distortion. Figure 45
shows that the AD8605 has less than 0.005% or -86 dB of THD
+ N over the entire audio frequency range. The AD8605 is
configured in positive unity gain, which is the worst case, and
with a load of 10 k.
AD8605/AD8606/AD8608
Rev. D | Page 14 of 20
FREQUENCY (Hz)
0.1
0.01
0.0001
20
20k
100
THD + N (%)
1k
0.001
10k
V
SY
= 2.5V
A
V
= 1
B
W
= 22kHz
02731-D-045
Figure 45. THD + N
TOTAL NOISE INCLUDING SOURCE RESISTORS
The low input current noise and input bias current of the
AD8605 make it the ideal amplifier for circuits with substantial
input source resistance such as photodiodes. Input offset voltage
increases by less than 0.5 nV per 1 k of source resistance at
room temperature and increases to 10 nV at 85C. The total
noise density of the circuit is
( )
S
S
n
n
TOTAL
n
TR
k
R
i
e
e
4
2
2
,
+
+
=
where:
e
n
is the input voltage noise density of the AD8605
i
n
is the input current noise density of the AD8605
R
S
is the source resistance at the noninverting terminal
k is Boltzmann's constant (1.38 10
-23
J/K)
T is the ambient temperature in Kelvin (T = 273 + C)
For example, with R
S
= 10 k, the total voltage noise density is
roughly 15 nV/Hz.
For R
S
< 3.9 k, e
n
dominates and e
n,TOTAL
e
n
.
The current noise of the AD8605 is so low that its total density
does not become a significant term unless R
S
is greater than
6 M. The total equivalent rms noise over a specific bandwidth
is expressed as
(
)
BW
e
E
TOTAL
n
n
,
=
where BW is the bandwidth in hertz.
Note that the analysis above is valid for frequencies greater than
100 Hz and assumes relatively flat noise, above 10 kHz. For
lower frequencies, flicker noise (1/f) must be considered.
CHANNEL SEPARATION
Channel separation, or inverse crosstalk, is a measure of the
signal feed from one amplifier (channel) to an other on the
same IC.
The AD8606 has a channel separation of greater than -160 dB
up to frequencies of 1 MHz, allowing the two amplifiers to
amplify ac signals independently in most applications.
CHANNEL SEPARATION (dB)
FREQUENCY (Hz)
10M
1M
100k
10k
1k
100
100M
20
0
40
60
80
100
120
140
160
180
02731-D-046
Figure 46. Channel Separation vs. Frequency
CAPACITIVE LOAD DRIVE
The AD8605 can drive large capacitive loads without oscillation.
Figure 47 shows the output of the AD8606 in response to a
200 mV input signal. In this case, the amplifier was configured
in positive unity gain, worst case for stability, while driving a
1,000 pF load at its output. Driving larger capacitive loads in
unity gain may require the use of additional circuitry.
TIME (10
s/DIV)
VOLTA
GE (
100mV/D
I
V)
V
S
= 2.5V
A
V
= 1
R
L
= 10k
C
L
= 1
02731-D-047
Figure 47. Capacitive Load Drive without Snubber
A snubber network, shown in Figure 48, helps reduce the signal
overshoot to a minimum and maintain stability. Although this
circuit does not recover the loss of bandwidth induced by large
capacitive loads, it greatly reduces the overshoot and ringing.
This method does not reduce the maximum output swing of
the amplifier.
Figure 49 shows a scope photograph of the output at the
snubber circuit. The overshoot is reduced from over 70% to
less than 5%, and the ringing is eliminated by the snubber.
Optimum values for R
S
and C
S
are determined experimentally.
AD8605/AD8606/AD8608
Rev. D | Page 15 of 20
R
S
C
S
R
L
C
L
V+
V
4
2
3
8
1
AD8605
V
IN
200mV
02731-
D
-
049
Figure 48. Snubber Network Configuration
TIME (10
s/DIV)
VOLTA
GE (
100mV/D
I
V)
V
S
= 2.5V
A
V
= 1
R
L
= 10k
R
S
= 90
C
L
= 1,000pF
C
S
= 700pF
02731-D-048
Figure 49. Capacitive Load Drive with Snubber
Table 5 summarizes a few optimum values for capacitive loads.
Table 5.
C
L
(pF)
R
S
()
C
S
(pF)
500
100
1,000
1,000
70
1,000
2,000
60
800
An alternate technique is to insert a series resistor inside the
feedback loop at the output of the amplifier. Typically, the value
of this resistor is approximately 100 . This method also
reduces overshoot and ringing but causes a reduction in the
maximum output swing.
LIGHT SENSITIVITY
The AD8605ACB (MicroCSP package option) is essentially
a silicon die with additional post fabrication dielectric and
intermetallic processing designed to contact solder bumps on
the active side of the chip. With this package type, the die is
exposed to ambient light and is subject to photoelectric effects.
Light sensitivity analysis of the AD8605ACB mounted on
standard PCB material reveals that only the input bias current
(I
B
) parameter is impacted when the package is illuminated
directly by high intensity light. No degradation in electrical
performance is observed due to illumination by low intensity
(0.1 mW/cm
2
) ambient light. Figure 50 shows that I
B
increases
with increasing wavelength and intensity of incident light;
I
B
can reach levels as high as 4500 pA at a light intensity of
3 mW/cm
2
and a wavelength of 850 nm. The light intensities
shown in Figure 50 are not normal for most applications, i.e.,
even though direct sunlight can have intensities of 50 mW/cm
2
,
office ambient light can be as low as 0.1 mW/cm
2
.
When the MicroCSP package is assembled on the board with
the bump-side of the die facing the PCB, reflected light from the
PCB surface is incident on active silicon circuit areas and results
in the increased I
B
. No performance degradation occurs due to
illumination of the backside (substrate) of the AD8605ACB.
The AD8605ACB is particularly sensitive to incident light with
wavelengths in the near infrared range (NIR, 700 nm to 1000
nm). Photons in this waveband have a longer wavelength and
lower energy than photons in the visible (400 nm to 700 nm)
and near ultraviolet bands (NUV, 200 nm to 400 nm); therefore,
they can penetrate more deeply into the active silicon. Incident
light with wavelengths greater than 1100 nm has no photo-
electric effect on the AD8605ACB because silicon is trans-
parent to wave lengths in this range. The spectral content of
conventional light sources varies: sunlight has a broad spectral
range, with peak intensity in the visible band that falls off in the
NUV and NIR bands; fluorescent lamps have significant peaks
in the visible but not in the NUV or NIR bands.
Efforts have been made at a product level to reduce the effect
of ambient light; the under bump metal (UBM) has been
designed to shield the sensitive circuit areas on the active side
(bump-side) of the die. However, if an application encounters
any light sensitivity with the AD8605ACB, shielding the bump
side of the MicroCSP package with opaque material should
eliminate this effect. Shielding can be accomplished using
materials such as silica filled liquid epoxies that are used in
flip chip underfill techniques.
WAVELENGTH (nm)
3500
0
350
INP
U
T BIAS
CURRE
NT (pA)
2500
3000
2000
500
1000
1500
450
550
650
750
850
1mW/cm
2
4000
4500
5000
3mW/cm
2
2mW/cm
2
02731-D-050
Figure 50. AD8605ACB Input Bias Current Response to Direct Illumination of
Varying Intensity and Wavelength
MICROCSP ASSEMBLY CONSIDERATIONS
For detailed information on MicroCSP PCB assembly and
reliability, refer to ADI Application Note AN-617 on the ADI
website
www.analog.com
.
AD8605/AD8606/AD8608
Rev. D | Page 16 of 20
I-V CONVERSION APPLICATIONS
PHOTODIODE PREAMPLIFIER APPLICATIONS
The low offset voltage and input current of the AD8605 make it
an excellent choice for photodiode applications. In addition, the
low voltage and current noise make the amplifier ideal for
application circuits with high sensitivity.
R
D
I
D
C
D
50pF
AD8605
V
OUT
PHOTODIODE
+VOS
R
F
10M
C
F
10pF
02731-D-051
Figure 51. Equivalent Circuit for Photodiode Preamp
The input bias current of the amplifier contributes an error
term that is proportional to the value of R
F
.
The offset voltage causes a dark current induced by the shunt
resistance of the diode R
D
. These error terms are combined at
the output of the amplifier. The error voltage is written as
B
F
D
F
OS
O
I
R
R
R
V
E
+


+
=
1
Typically, R
F
is smaller than R
D
, thus R
F
/R
D
can be ignored.
At room temperature, the AD8605 has an input bias current of
0.2 pA and an offset voltage of 100 V. Typical values of R
D
are
in the range of 1 G.
For the circuit shown in Figure 9, the output error voltage is
approximately 100 V at room temperature, increasing to about
1 mV at 85C.
Where f
t
is the unity gain frequency of the amplifier, the
maximum achievable signal bandwidth is
T
F
t
MAX
C
R
f
f
=
2
AUDIO AND PDA APPLICATIONS
The AD8605's low distortion and wide dynamic range make it a
great choice for audio and PDA applications, including
microphone amplification and line output buffering.
Figure 52 shows a typical application circuit for headphone/line
out amplification.
R1 and R2 are used to bias the input voltage at half the supply.
This maximizes the signal bandwidth range. C1 and C2 are used
to ac couple the input signal. C1 and R2 form a high-pass filter
whose corner frequency is 1/2R1C1.
The high output current of the AD8605 allows it to drive heavy
resistive loads.
The circuit of Figure 52 was tested to drive a 16 W headphone.
The THD + N is maintained at approximately -60 dB
throughout the audio range.
5V
4
2
3
8
1
HEADPHONES
5V
4
6
5
8
7
C1
1
F
R1
10k
R2
10k
V1
500mV
1/2
AD8606
C3
100
F
R4
20
R3
1k
1/2
AD8606
C4
100
F
R6
20
R5
1k
C2
1
F
V2
500mV
02731-D-052
Figure 52. Single-Supply Headphone/Speaker Amplifier
AD8605/AD8606/AD8608
Rev. D | Page 17 of 20
INSTRUMENTATION AMPLIFIERS
The low offset voltage and low noise of the AD8605 make it a
great amplifier for instrumentation applications.
Difference amplifiers are widely used in high accuracy circuits
to improve the common-mode rejection ratio.
Figure 53 shows a simple difference amplifier. The CMRR of the
circuit is plotted versus frequency. Figure 54 shows the
common-mode rejection for a unity gain configuration and for
a gain of 10.
Making (R4/R3) = (R2/R1) and choosing 0.01% tolerance yields
a CMRR of 74 dB and minimizes the gain error at the output.
AD8605
5V
V2
V1
R1
1k
R3
1k
R2
10k
R4
10k
V
OUT
R4
R3
R2
R1
=
V
OUT
= (V2 V1)
R2
R1
02731-D-053
Figure 53. Difference Amplifier, A
V
= 10
FREQUENCY (Hz)
120
100
0
100
10M
1k
CMRR (dB)
10k
100k
1M
60
40
20
80
A
V
= 10
V
SY
= 2.5V
A
V
= 1
02731-D-054
Figure 54. Difference Amplifier CMRR vs. Frequency
D/A CONVERSION
The low input bias current and offset voltage of the AD8605
make it an excellent choice for buffering the output of a current
output DAC.
Figure 55 shows a typical implementation of the AD8605 at the
output of a 12-bit DAC.
The DAC8143 output current is converted to a voltage by the
feedback resistor. The equivalent resistance at the output of the
DAC varies with the input code, as does the output capacitance.
R2
AD8605
V
OS
R
F
C
F
R2
R2
V+
V
02731-
D-
055
R
R
R
V
REF
Figure 55. Simplified Circuit of the DAC8143 with AD8605 Output Buffer
To optimize the performance of the DAC, insert a capacitor in
the feedback loop of the AD8605 to compensate the amplifier
from the pole introduced by the output capacitance of the DAC.
Typical values for C
F
are in the range of 10 pF to 30 pF; it can be
adjusted for the best frequency response. The total error at the
output of the op amp can be computed by the formula:


+
=
q
R
V
E
F
OS
O
Re
1
where Req is the equivalent resistance seen at the output of the
DAC. As mentioned above, Req is code dependant and varies
with the input. A typical value for Req is 15 k. Choosing a
feedback resistor of 10 k yields an error of less than 200 V.
Figure 56 shows the implementation of a dual-stage buffer at
the output of a DAC. The first stage is used as a buffer.
Capacitor C1, with Req, creates a low-pass filter and thus
provides phase lead to compensate for frequency response. The
second stage of the AD8606 is used to provide voltage gain at
the output of the buffer.
Grounding the positive input terminals in both stages reduces
errors due to the common-mode output voltage. Choosing R1,
R2, and R3 to match within 0.01% yields a CMRR of 74 dB and
maintains minimum gain error in the circuit.
R
FB
V
DD
DB11
OUT1
AD7545
AGND
R
CS
R
P
V
IN
15V
V
OUT
V
REF
1/2
AD8606
1/2
AD8606
R4
5k
10%
R1
10k
R2
10k
R3
20k
C1
33pF
02731-D
-
056
Figure 56. Bipolar Operation
AD8605/AD8606/AD8608
Rev. D | Page 18 of 20
OUTLINE DIMENSIONS
PIN 1
1.60 BSC
2.80 BSC
1.90
BSC
0.95 BSC
1
3
4
5
2
0.22
0.08
10
5
0
0.50
0.30
0.15 MAX
SEATING
PLANE
1.45 MAX
1.30
1.15
0.90
2.90 BSC
0.60
0.45
0.30
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 57. 5-Lead Small Outline Transistor Package [SOT-23] (RT-5)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COPLANARITY
0.10
14
8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
8
0
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AB
45
Figure 58. 14-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-14)
0.80
0.60
0.40
8
0
4
8
5
4.90
BSC
PIN 1
0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 59. 8-Lead Mini Small Outline Package [MSOP] (RM-8)
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8
5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 60. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8)
4.50
4.40
4.30
14
8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05
0.30
0.19
1.20
MAX
1.05
1.00
0.80
0.20
0.09
8
0
0.75
0.60
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
SEATING
PLANE
0.50 REF
0.87
0.37
0.36
0.35
0.17
0.14
0.12
0.21
0.50
0.20
0.50
0.23
0.18
0.14
BOTTOM VIEW
0.94
0.90
0.86
1.33
1.29
1.25
TOP VIEW
(BALL SIDE DOWN)
PIN 1
IDENTIFIER
Figure 62. 5-Bump 2 1 2 Array MicroCSP [WLCSP] (CB-5)
AD8605/AD8606/AD8608
Rev. D | Page 19 of 20
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding
AD8605ACB-REEL
-40C to +125C
5-Bump MicroCSP
CB-5
B3A
AD8605ACB-REEL7
-40C to +125C
5-Bump MicroCSP
CB-5
B3A
AD8605ART-R2
-40C to +125C
5-Lead SOT-23
RT-5
B3A
AD8605ART-REEL
-40C to +125C
5-Lead SOT-23
RT-5
B3A
AD8605ART-REEL7
-40C to +125C
5-Lead SOT-23
RT-5
B3A
AD8605ARTZ-REEL
1
-40C to +125C
5-Lead SOT-23
RT-5
B3A
AD8605ARTZ-REEL7
1
-40C to +125C
5-Lead SOT-23
RT-5
B3A
AD8606ARM-R2
-40C to +125C
8-Lead MSOP
RM-8
B6A
AD8606ARM-REEL
-40C to +125C
8-Lead MSOP
RM-8
B6A
AD8606AR
-40C to +125C
8-Lead SOIC
R-8
AD8606AR-REEL
-40C to +125C
8-Lead SOIC
R-8
AD8606AR-REEL7
-40C to +125C
8-Lead SOIC
R-8
AD8608AR
-40C to +125C
14-Lead SOIC
R-14
AD8608AR-REEL
-40C to +125C
14-Lead SOIC
R-14
AD8608AR-REEL7
-40C to +125C
14-Lead SOIC
R-14
AD8608ARU
-40C to +125C
14-Lead TSSOP
RU-14
AD8608ARU-REEL
-40C to +125C
14-Lead TSSOP
RU-14
1
Z = Pb-free part.
AD8605/AD8606/AD8608
Rev. D | Page 20 of 20
NOTES
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02731-0-5/04(D)