Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- PIN CONFIGURATIONS
-
-
-
-
-
-
50 MHz, Precision, Low Distortion,
Low Noise CMOS Amplifiers
AD8651/AD8652
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
Bandwidth: 50 MHz @ 5 V
Low Noise: 4.5 nV/Hz
Offset voltage: 100 V typ, specified over
entire common-mode range
41 V/s slew rate
Rail-to-rail input and output swing
Input bias current: 1 pA
Single-supply operation: 2.7 V to 5.5 V
Space-saving MSOP and SOIC packaging
APPLICATIONS
Optical communications
Laser source drivers/controllers
Broadband communications
High speed ADC and DAC
Microwave link interface
Cell phone PA control
Video line driver
Audio
PIN CONFIGURATIONS
NC
1
IN
2
+IN
3
V
4
NC
8
V+
7
OUT
6
NC
5
NC = NO CONNECT
AD8651
TOP VIEW
(Not to Scale)
03301-0-001
Figure 1. 8-Lead MSOP (RM-8)
OUT A
1
IN A
2
+IN A
3
V
4
V+
8
OUT B
7
IN B
6
+IN B
5
AD8652
TOP VIEW
(Not to Scale)
03301-B
-
003
Figure 2. 8-Lead MSOP (RM-8)
NC
1
IN
2
+IN
3
V
4
NC
8
V+
7
OUT
6
NC
5
NC = NO CONNECT
AD8651
TOP VIEW
(Not to Scale)
03301-0-002
Figure 3. 8-Lead SOIC (R-8)
OUT A
1
IN A
2
+IN A
3
V
4
V+
8
OUT B
7
IN B
6
+IN B
5
AD8652
TOP VIEW
(Not to Scale)
03301-B
-
004
Figure 4. 8-Lead SOIC (R-8)
GENERAL DESCRIPTION
The AD8651 is a high precision, low noise, low distortion, rail-
to-rail CMOS operational amplifier that runs from a single-
supply voltage of 2.7 V to 5 V.
The AD8651 is a rail-to-rail input and output amplifier with a
gain bandwidth of 50 MHz and a typical voltage offset of
100 V across common mode from a 5 V supply. It also features
low noise--4.5 nV/Hz.
The AD8651 can be used in communications applications, such
as cell phone transmission power control, fiber optic
networking, wireless networking, and video line drivers.
The AD8651 features the newest generation of DigiTrim
in-package trimming. This new generation measures and
corrects the offset over the entire input common-mode range,
providing less distortion from V
OS
variation than is typical of
other rail-to-rail amplifiers. Offset voltage and CMRR are both
specified and guaranteed over the entire common-mode range
as well as over the extended industrial temperature range.
The AD8651 is offered in the 8-lead SOIC package and the
8-lead MSOP package. It is specified over the extended indus-
trial temperature range (-40C to +125C).
AD8651/AD8652
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3
Electrical Characteristics ................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Applications..................................................................................... 14
Theory of Operation .................................................................. 14
Rail-to-Rail Output Stage...................................................... 14
Rail-to-Rail Input Stage ......................................................... 14
Input Protection ..................................................................... 15
Overdrive Recovery ............................................................... 15
Layout, Grounding, and Bypassing considerations ............... 15
Power Supply Bypassing........................................................ 15
Grounding............................................................................... 15
Leakage Currents.................................................................... 15
Input Capacitance .................................................................. 15
Output Capacitance ............................................................... 16
Settling Time........................................................................... 16
THD Readings vs. Common-Mode Voltage ...................... 16
Driving a 16-Bit ADC............................................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
9/04--Data Sheet Changed from Rev. A to Rev. B
Added AD8652 ....................................................................Universal
Change to General Description ....................................................... 1
Changes to Electrical Characteristics ............................................. 3
Changes to Absolute Maximum Ratings ........................................ 5
Change to Figure 23 .......................................................................... 9
Change to Figure 26 .......................................................................... 9
Change to Figure 36 ........................................................................ 11
Change to Figure 42 ........................................................................ 12
Change to Figure 49 ........................................................................ 13
Change to Figure 51 ........................................................................ 13
Inserted Figure 52............................................................................ 13
Change to Theory of Operation section....................................... 14
Change to Input Protection section .............................................. 15
Changes to Ordering Guide ........................................................... 20
6/04--Changed from REV. 0 to REV. A
Change to Figure 18 .............................................................................8
Change to Figure 21 .............................................................................9
Change to Figure 29 .............................................................................10
Change to Figure 30 .............................................................................10
Change to Figure 43 .............................................................................12
Change to Figure 44 .............................................................................12
Change to Figure 47 .............................................................................13
Change to Figure 57 .............................................................................17
10/03 Revision 0: Initial Version
AD8651/AD8652
Rev. B | Page 3 of 20
ELECTRICAL CHARACTERISTICS
Table 1. V+ = 2.7 V, V = 0 V, VCM = V+/2, TA = 25C, unless otherwise specified
Parameter
Symbol Conditions
Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage
V
OS
AD8651
0 V
CM
2.7 V
100
350
V
40C
T
A
+85C, 0 V
CM
2.7 V
1.4
mV
40C
T
A
+125C, 0 V
CM
2.7 V
1.6
mV
AD8652
0 V
CM
2.7 V
90
300
V
40C
T
A
+125C, 0 V
CM
2.7 V
0.4
1.3
mV
Offset Voltage Drift
4
V/C
Input Bias Current
I
B
1
10
pA
40C
T
A
+125C
600
pA
Input Offset Current
I
OS
1
10
pA
40C
T
A
+85C
30
pA
40C
T
A
+125C
600
pA
Input Voltage Range
V
CM
0.1
+2.8
V
Common-Mode Rejection Ratio
CMRR
AD8651
V
+
= 2.7 V, 0.1 V < V
CM
< +2.8 V
75
95
dB
40C
T
A
+85C, 0.1 V < V
CM
< +2.8 V
70
88
dB
40C
T
A
+125C, 0.1 V < V
CM
< +2.8 V
65
85
dB
AD8652
V
+
= 2.7 V, 0.1 V < V
CM
< +2.8 V
77
95
dB
40C
T
A
+125C, 0.1 V < V
CM
< +2.8 V
73
90
dB
Large Signal Voltage Gain
A
VO
R
L
= 1 k, 200 mV < V
O
< 2.5 V
100
115
dB
R
L
= 1 k, 200 mV < V
O
< 2.5 V, T
A
= +85C
100
114
dB
R
L
= 1 k, 200 mV < V
O
< 2.5 V, T
A
= +125C
95
108
dB
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
I
L
= 250 A, 40C T
A
+125C
2.67
V
Output Voltage Low
V
OL
I
L
= 250 A, 40C T
A
+125C
30
mV
Short Circuit Limit
I
SC
Sourcing
80
mA
Sinking
80
mA
Output Current
I
O
+40
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= 2.7 V to 5.5 V, V
CM
= 0 V
76
94
dB
40C
T
A
+125C
74
93
dB
Supply Current
I
SY
AD8651
I
O
= 0
9
12
mA
40C
T
A
+125C
14.5
mA
AD8652
I
O
= 0
17.5
19.5
mA
40C
T
A
+125C
22.5
mA
INPUT CAPACITANCE
C
IN
Differential
6
pF
Common-Mode
9
pF
DYNAMIC PERFORMANCE
Slew Rate
SR
G = 1, R
L
= 10 k
41
V/s
Gain Bandwidth Product
GBP
G = 1
50
MHz
Settling Time, 0.01%
G = 1, 2 V Step
0.2
s
Overload Recovery Time
V
IN
G = 1.48 V
+
0.1
s
Total Harmonic Distortion + Noise
THD + N
G = 1, R
L
= 600 , f = 1 kHz, V
IN
= 2 V p-p
0.0006
%
NOISE PERFORMANCE
Voltage Noise Density
e
n
f = 10 kHz
5
nV/Hz
f = 100 kHz
4.5
nV/Hz
Current Noise Density
i
n
f = 10 kHz
4
fA/Hz
AD8651/AD8652
Rev. B | Page 4 of 20
ELECTRICAL CHARACTERISTICS
Table 2. V+ = 5 V, V = 0 V, VCM = V+/2, TA = 25C, unless otherwise specified
Parameter Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
OS
AD8651
0 V
CM
5 V
100
350
V
40C
T
A
+85C, 0 V
CM
5 V
1.4
mV
40C
T
A
+125C, 0 V
CM
5 V
1.7
mV
AD8652
0 V
CM
5 V
90
300
V
40C
T
A
+125C, 0 V
CM
5 V
0.4
1.4
mV
Offset Voltage Drift
4
V/C
Input Bias Current
I
B
1
10
pA
40C
T
A
+85C
30
pA
40C
T
A
+125C
600
pA
Input Offset Current
I
OS
1
10
pA
40C
T
A
+85C
30
pA
40C
T
A
+125C
600
pA
Input Voltage Range
V
CM
0.1
+5.1
V
Common-Mode Rejection Ratio
CMRR
AD8651
0.1 V < V
CM
< 5.1 V
80
95
dB
40C
T
A
+85C, 0.1 V < V
CM
< 5.1 V
75
94
dB
40C
T
A
+125C, 0.1 V < V
CM
< 5.1 V
70
90
dB
AD8652
0.1 V < V
CM
< 5.1 V
84
100
dB
40C
T
A
+125C, 0.1 V < V
CM
< 5.1 V
76
95
dB
Large Signal Voltage Gain
A
VO
R
L
= 1 k, 200 mV < V
O
< 4.8 V
100
115
dB
R
L
= 1 k, 200 mV < V
O
< 4.8 V, T
A
= +85C
98
114
dB
R
L
= 1 k, 200 mV < V
O
< 4.8 V, T
A
= +125C
95
111
dB
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
I
L
= 250 A, 40C T
A
+125C
4.97
V
Output Voltage Low
V
OL
I
L
= 250 A, 40C T
A
+125C
30
mV
Short Circuit Limit
I
SC
Sourcing
80
mA
Sinking
80
mA
Output Current
I
O
+40
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= 2.7 V to 5.5 V, V
CM
= 0 V
76
94
dB
40C
T
A
+125C
74
93
dB
Supply Current
I
SY
AD8651
I
O
= 0
9.5
14.0
mA
40C
T
A
+125C
15
mA
AD8652
I
O
= 0
17.5
20.0
mA
40C
T
A
+125C
23.5
mA
INPUT CAPACITANCE
C
IN
Differential
6
pF
Common-Mode
9
pF
DYNAMIC PERFORMANCE
Slew Rate
SR
G = 1, R
L
= 10 k
41
V/s
Gain Bandwidth Product
GBP
G = 1
50
MHz
Settling Time, 0.01%
G = 1, 2 V Step
0.2
s
Overload Recovery Time
V
IN
G = 1.2 V
+
0.1 s
Total Harmonic Distortion + Noise
THD + N
G = 1, R
L
= 600 , f = 1 kHz, V
IN
= 2 V p-p
0.0006
%
NOISE PERFORMANCE
Voltage Noise Density
e
n
f = 10 kHz
5
nV/Hz
f = 100 kHz
4.5
nV/Hz
Current Noise Density
I
n
f = 10 kHz
4
fA/Hz
AD8651/AD8652
Rev. B | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25C, unless otherwise noted.
Table 3.
Parameter Rating
Supply Voltage
6.0 V
Input Voltage
GND to V
S
+ 0.3 V
Differential Input Voltage
6.0 V
Output Short-Circuit Duration to GND
Indefinite
Electrostatic Discharge (HBM)
4000 V
Storage Temperature Range
RM, R Package
-65C to +150C
Operating Temperature Range
-40C to +125C
Junction Temperature Range
RM, R Package
-65C to +150C
Lead Temperature (Soldering, 10 s)
300C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Package Type
JA
1
JC
Unit
8-Lead MSOP (RM)
210
45
C/W
8-Lead SOIC (R)
158
43
C/W
1
JA
is specified for the worst-case conditions, i.e.,
JA
is specified for device
soldered in circuit board for surface-mount packages.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8651/AD8652
Rev. B | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
V
OS
(
V)
V
S
= 2.5V
V
CM
= 0V
NUMBE
R OF AMP
L
IFIE
RS
200
160
120
8
0
4
0
0
40
80
120
160
200
0
10
50
40
30
20
60
03301-B
-
005
Figure 5. Input Offset Voltage Distribution
V
OS
(
V)
300
200
200
100
0
100
300
TEMPERATURE (C)
50
0
50
100
150
V
S
= 2.5V
V
CM
= 0V
03301-B
-
006
Figure 6. Input Offset Voltage vs. Temperature
NUMBE
R OF AMP
L
IFIE
RS
0
10
50
40
30
20
60
TCV
OS
(
V/C)
0
1
2
3
4
5
6
7
8
9
10
11
V
S
= 2.5V
V
CM
= 0V
T: 40C TO 125C
03301-B
-
007
Figure 7. TCV
OS
Distribution
V
OS
(
V)
20
0
80
60
40
20
100
COMMON-MODE VOLTAGE (V)
0
1
2
3
4
5
6
V
S
= 5V
03301-B
-
008
Figure 8. Input Offset Voltage vs. Common-Mode Voltage
INP
U
T BAIS
CURRE
NT (pA)
0
500
400
300
200
100
TEMPERATURE (C)
0
40
140
120
100
80
60
20
V
S
= 2.5V
03301-B
-
009
Figure 9. Input Bias Current vs. Temperature
S
U
P
P
L
Y
CURRE
NT (mA)
0
10
8
6
4
2
SUPPLY VOLTAGE (V)
0
2
5
4
3
1
6
03301-B
-
010
Figure 10. Supply Current vs. Supply Voltage
AD8651/AD8652
Rev. B | Page 7 of 20
S
U
P
P
L
Y
CURRE
NT (mA)
6
7
11
10
9
8
12
TEMPERATURE (C)
50
0
50
100
150
V
S
= 2.5V
03301-B
-
011
Figure 11. Supply Current vs. Temperature
V
SY
V
OUT
(mV
)
0
100
400
300
200
500
CURRENT LOAD (mA)
0
20
40
60
100
80
V
S
= 2.5V
V
OH
V
OL
03301-B
-
012
Figure 12. Output Voltage to Supply Rail vs. Load Current
OUTPUT SW
ING HIGH (
V
)
4.990
4.991
4.995
4.996
4.994
4.993
4.992
4.997
TEMPERATURE (C)
50
0
50
100
150
V
S
= 5V
I
L
= 250
A
03301-B
-
013
Figure 13. Output Voltage Swing High vs. Temperature
OUTPUT SW
ING LOW
(
m
V)
0
0.50
2.50
2.00
1.50
1.00
TEMPERATURE (C)
50
0
50
100
150
V
S
= 5V
I
L
= 250
A
03301-B
-
014
Figure 14. Output Voltage Swing Low vs. Temperature
CMRR (dB)
0
100
80
60
40
20
FREQUENCY (Hz)
10
1k
10M
1M
100k
10k
100
V
S
= 2.5V
03301-B
-
015
Figure 15. CMRR vs. Frequency
CMRR (dB)
90
95
110
105
100
TEMPERATURE (C)
50
0
50
100
150
V
S
= 2.5V
03301-B
-
016
Figure 16. CMRR vs. Temperature
AD8651/AD8652
Rev. B | Page 8 of 20
CMRR (dB)
82
85
100
97
91
88
94
TEMPERATURE (C)
50
0
50
100
150
03301-B
-
017
Figure 17. CMRR vs. Temperature
P
S
RR (dB)
0
100
80
60
40
20
FREQUENCY (Hz)
1
10
100
1k
10k
100k
1M
10M
100M
V
S
= 2.5V
+PSRR
PSRR
03301-B
-
018
Figure 18. PSRR vs. Frequency
P
S
RR (dB)
80
85
100
95
90
TEMPERATURE (C)
50
0
50
100
150
V
S
= 2.5V
03301-B
-
019
Figure 19. PSRR vs. Temperature
VOLTA
GE N
O
ISE D
E
N
S
ITY (
n
V/
Hz)
1
100
10
FREQUENCY (Hz)
10
1k
100k
10k
100
V
S
= 2.5V
03301-B
-
020
Figure 20. Voltage Noise Density vs. Frequency
CURRE
NT NOIS
E
DE
NS
ITY
(fA/
Hz)
0
80
60
40
20
FREQUENCY (Hz)
100
1k
100k
10k
V
S
= 2.5V
03301-B
-
021
Figure 21. Current Noise Density vs. Frequency
V
S
= 2.5V
V
IN
= 6.4V
V
OUT
V
IN
VOLTA
GE (
1
V/D
I
V)
TIME (200
s/DIV)
0
03301-B
-
022
Figure 22. No Phase Reversal
AD8651/AD8652
Rev. B | Page 9 of 20
OPEN-
L
OOP GAIN (
d
B)
20
0
20
40
60
80
100
120
140
PH
A
SE (
D
egrees)
180
135
90
45
0
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
100M
V
S
= 2.5V
03301-B
-
023
Figure 23. Open-Loop Gain and Phase vs. Frequency
A
VO
(dB)
112
113
117
116
115
114
TEMPERATURE (C)
50
0
50
100
150
V
S
= 2.5V
R
L
= 1k
03301-B
-
024
Figure 24. Open-Loop Gain vs. Temperature
OPEN-
L
OOP GAIN (
d
B)
60
70
130
120
110
100
90
80
140
OUTPUT VOLTAGE SWING FROM THE RAILS (mV)
0
50
100
150
250
200
V
S
= 2.5V
4.2mA
I
L
= 250
A
2.5mA
03301-B
-
025
Figure 25. Open-Loop Gain vs. Output Voltage Swing
G = 100
G = 10
G = 1
V
S
= 2.5V
R
L
= 1M
C
L
= 47pF
FREQUENCY (Hz)
CLOSED-
L
OOP GAIN (
d
B)
5k
40
20
20
0
60
40
50k
5M
500k
50M
300M
03301-B
-
026
Figure 26. Closed-Loop Gain vs. Frequency
MAX
I
MUM O
U
TP
UT S
W
ING
(V
)
0
6
3
4
5
2
1
FREQUENCY (Hz)
100k
100M
10M
1M
V
S
= 5V
V
S
= 2.7V
03301-B
-
027
Figure 27. Maximum Output Swing vs. Frequency
V
S
= 2.5V
C
L
= 47pF
A
V
= 1
VOLTA
GE (
1
V/D
I
V)
TIME (100
s/DIV)
03301-B
-
028
Figure 28. Large Signal Response
AD8651/AD8652
Rev. B | Page 10 of 20
V
S
= 2.5V
V
IN
= 200mV
A
V
= 1
VOLTA
GE (
100mV/D
I
V)
TIME (10
s/DIV)
03301-B
-
029
Figure 29. Small Signal Response
SM
A
L
L SIGN
A
L
OVER
SH
OOT (
%
)
0
30
25
20
15
10
5
CAPACITANCE (pF)
0
20
60
50
40
30
10
+OS
OS
70
V
S
= 2.5V
V
IN
= 200mV
A
V
= 1
03301-B
-
030
Figure 30. Small Signal Overshoot vs. Load Capacitance
V
S
= 2.5V
V
IN
= 200mV
GAIN = 15
TIME (200ns/DIV)
200mV
2.5V
0V
0V
03301-B
-
031
Figure 31. Negative Overload Recovery Time
V
S
= 2.5V
V
IN
= 200mV
GAIN = 15
OUTPUT
INPUT
TIME (200ns/DIV)
0V
0V
200mV
2.5V
03301-B
-
032
Figure 32. Positive Overload Recovery Time
OUTP
UT IMP
E
DANCE
(
)
0
40
30
20
10
FREQUENCY (Hz)
10
1000
100000
10000
100
V
S
= 2.5V
GAIN = 100
GAIN = 10
GAIN = 1
03301-B
-
033
Figure 33. Output Impedance vs. Frequency
V
OS
(
V)
V
S
= 1.35V
V
CM
= 0V
NUMBE
R OF AMP
L
IFIE
RS
200
160
120
8
0
4
0
0
40
80
120
160
200
0
10
50
40
30
20
60
03301-B
-
034
Figure 34. Input Offset Voltage Distribution
AD8651/AD8652
Rev. B | Page 11 of 20
V
OS
(
V)
300
200
200
100
0
100
300
TEMPERATURE (C)
50
0
50
100
150
V
S
= 1.35V
V
CM
= 0V
03301-B
-
035
Figure 35. Input Offset Voltage vs. Temperature
IN
PU
T OFFSET VOLTA
G
E (
V)
20
0
60
40
20
80
INPUT COMMON-MODE VOLTAGE (V)
0
1
2
3
V
S
= 2.7V
03301-B
-
036
Figure 36. Input Offset Voltage vs. Common-Mode Voltage
S
U
P
P
L
Y
CURRE
NT (mA)
6
7
10
9
8
11
TEMPERATURE (C)
50
0
50
100
150
V
S
= 1.35V
03301-B
-
037
Figure 37. Supply Current vs. Temperature
V
SY
V
OUT
(mV
)
0
100
400
300
200
500
CURRENT LOAD (mA)
0
20
40
60
100
80
V
S
= 1.35V
V
OH
V
OL
03301-B
-
038
Figure 38. Output Voltage to Supply Rail vs. Load Current
OUTPUT SW
ING HIGH (
V
)
2.690
2.691
2.695
2.696
2.694
2.693
2.692
2.697
TEMPERATURE (C)
50
0
50
100
150
V
S
= 2.7V
I
L
= 250
A
03301-B
-
039
Figure 39. Output Voltage Swing High vs. Temperature
OUTPUT SW
ING LOW
(
m
V)
0
0.50
3.00
2.50
1.50
1.00
2.00
TEMPERATURE (C)
50
0
50
100
150
V
S
= 2.7V
I
L
= 250
A
03301-B
-
040
Figure 40. Output Voltage Swing Low vs. Temperature
AD8651/AD8652
Rev. B | Page 12 of 20
V
S
= 1.35V
A
V
= 1
VOLTA
GE (
1
V/D
I
V)
TIME (200
s/DIV)
03301-B
-
041
Figure 41. No Phase Reversal
V
S
= 1.35V
C
L
= 47pF
A
V
= 1
VOLTA
GE (
500mV/D
I
V)
TIME (100
s/DIV)
03301-B
-
042
Figure 42. Large Signal Response
V
S
= 1.35V
V
IN
= 200mV
C
L
= 47pF
A
V
= 1
VOLTA
GE (
100mV/D
I
V)
TIME (10
s/DIV)
03301-B
-
043
Figure 43. Small Signal Response
SM
A
L
L SIGN
A
L
OVER
SH
OOT (
%
)
0
30
25
20
15
10
5
CAPACITANCE (pF)
0
20
60
50
40
30
10
+OS
70
V
S
= 1.35V
V
IN
= 200mV
OS
03301-B
-
044
Figure 44. Small Signal Overshoot vs. Load Capacitance
V
S
= 1.35V
V
IN
= 200mV
GAIN = 10
TIME (200ns/DIV)
200mV
1.35V
0V
0V
03301-B
-
045
Figure 45. Negative Overload Recovery Time
V
S
= 1.35V
V
IN
= 200mV
GAIN = 10
TIME (200ns/DIV)
0V
0V
200mV
1.35V
03301-B
-
046
Figure 46. Positive Overload Recovery Time
AD8651/AD8652
Rev. B | Page 13 of 20
CMRR (dB)
0
100
80
60
40
20
FREQUENCY (Hz)
10
1k
10M
1M
100k
10k
100
V
S
= 1.35V
03301-B
-
047
Figure 47. CMRR vs. Frequency
P
S
RR (dB)
0
100
80
60
40
20
FREQUENCY (Hz)
1
10
100
1k
10k
100k
1M
10M
V
S
= 1.35V
+PSRR
PSRR
03301-B
-
048
Figure 48. PSRR vs. Frequency
OPEN-
L
OOP GAIN (
d
B)
20
0
20
40
60
80
100
120
140
PH
A
SE (
D
egrees)
180
135
90
45
0
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
100M
V
S
= 1.35V
03301-B
-
050
Figure 49. Open-Loop Gain and Phase vs. Frequency
A
VO
(dB)
108
110
120
118
116
114
112
TEMPERATURE (C)
50
0
50
100
150
V
S
= 1.35V
R
L
= 1k
03301-B
-
051
Figure 50. Open-Loop Gain vs. Temperature
G = 100
G = 10
G = 1
V
S
= 1.35V
R
L
= 1M
C
L
= 47pF
FREQUENCY (Hz)
CLOSED-
L
OOP GAIN (
d
B)
5k
40
20
20
0
60
40
50k
5M
500k
50M
300M
03301-B
-
052
Figure 51. Closed-Loop Gain vs. Frequency
03301-B
-
062
FREQUENCY (Hz)
10M
100
1k
10k
100k
1M
CHANNEL SEPARATION (dB)
0
20
40
60
80
100
120
140
V
IN
28mV p-p
V+
V
V
V+
2.5V
+2.5V
V
OUT
R1
10k
R2
100
V
S
= 2.5V
Figure 52. Channel Separation
AD8651/AD8652
Rev. B | Page 14 of 20
APPLICATIONS
THEORY OF OPERATION
The AD8651 amplifier is a voltage feedback, rail-to-rail input
and output precision CMOS amplifier that operates from 2.7 V
to 5.0 V of power supply voltage. This amplifier uses Analog
Devices' DigiTrim technology to achieve a higher degree of
precision than is available from most CMOS amplifiers.
DigiTrim technology, used in a number of ADI amplifiers, is a
method of trimming the offset voltage of the amplifier after it
has been assembled. The advantage of post-package trimming is
that it corrects any offset voltages caused by the mechanical
stresses of assembly.
The AD8651 is available in standard op amp pinout, making
DigiTrim completely transparent to the user. The input stage of
the amplifier is a true rail-to-rail architecture, allowing the
input common-mode voltage range of the op amp to extend to
both positive and negative supply rails. The open-loop gain of
the AD8651/AD8652 with a load of 1 k is typically 115 dB.
The AD8651 can be used in any precision op amp application.
The amplifier does not exhibit phase reversal for common-
mode voltages within the power supply. With voltage noise of
4.5 nV/Hz and 105 dB distortion for 10 kHz, 2 V p-p signals,
the AD8651/AD8652 is a great choice for high resolution data
acquisition systems. Its low noise, sub-pA input bias current,
precision offset, and high speed make it a superb preamp
for fast photodiode applications. The speed and output
drive capability of the AD8651 also make it useful in
video applications.
Rail-to-Rail Output Stage
The voltage swing of the output stage is rail-to-rail and is
achieved by using an NMOS and PMOS transistor pair con-
nected in a common source configuration. The maximum
output voltage swing is proportional to the output current, and
larger currents will limit how close the output voltage can get to
the proximity of the output voltage to the supply rail. This is a
characteristic of all rail-to-rail output amplifiers. With 40 mA of
output current, the output voltage can reach within 5 mV of the
positive and negative rails. At light loads of >100 k, the output
swings within ~1 mV of the supplies.
Rail-to-Rail Input Stage
The input common-mode voltage range of the AD8651 extends
to both positive and negative supply voltages. This maximizes
the usable voltage range of the amplifier, an important feature
for single-supply and low voltage applications. This rail-to-rail
input range is achieved by using two input differential pairs, one
NMOS and one PMOS, placed in parallel. The NMOS pair is
active at the upper end of the common-mode voltage range,
and the PMOS pair is active at the lower end of the common-
mode range.
The NMOS and PMOS input stages are separately trimmed
using DigiTrim to minimize the offset voltage in both differen-
tial pairs. Both NMOS and PMOS input differential pairs are
active in a 500 mV transition region when the input common-
mode voltage is approximately 1.5 V below the positive supply
voltage. A special design technique improves the input offset
voltage in the transition region that traditionally exhibits a
slight V
OS
variation. As a result, the common-mode rejection
ratio is improved within this transition band. Compared to the
Burr Brown OPA350 amplifier, shown in Figure 53 (A), the
AD8651, shown in Figure 53 (B), exhibits much lower offset
voltage shift across the entire input common-mode range,
including the transition region.
COMMON-MODE VOLTAGE (V)
V
OS
(
V)
0
600
200
200
600
400
0
400
2
1
4
3
5
6
03301-B
-
053
COMMON-MODE VOLTAGE (V)
V
OS
(
V)
0
600
200
200
600
400
0
400
2
1
4
3
5
6
03301-B
-
054
(A) OPA350 VOS vs. VCM (B) AD8651 VOS vs. VCM
Figure 53. Input Offset Distribution over Common-Mode Voltage
AD8651/AD8652
Rev. B | Page 15 of 20
Input Protection
As with any semiconductor device, if a condition could exist for
the input voltage to exceed the power supply, the device's input
overvoltage characteristic must be considered. The inputs of the
AD8651 are protected with ESD diodes to either power supply.
Excess input voltage will energize internal PN junctions in the
AD8651, allowing current to flow from the input to the
supplies. This results in an input stage with picoamps of input
current that can withstand up to 4000 V ESD events (human
body model) with no degradation.
Excessive power dissipation through the protection devices will
destroy or degrade the performance of any amplifier. Differen-
tial voltages greater than 7 V will result in an input current of
approximately (|V
CC
V
EE
| 0.7 V)/R
I
, where R
I
is the
resistance in series with the inputs. For input voltages beyond
the positive supply, the input current will be approximately (V
I
V
CC
0.7)/R
I
. For input voltages beyond the negative supply,
the input current will be about (V
I
V
EE
+ 0.7)/R
I
. If the inputs
of the amplifier sustain differential voltages greater than 7 V or
input voltages beyond the amplifier power supply, limit the
input current to 10 mA by using an appropriately sized input
resistor (R
I
), as shown in Figure 54.
+
(| V
CC
V
EE
| 0.7V)
30mA
FOR LARGE | V
CC
V
EE
|
FOR V
I
BEYOND
SUPPLY VOLTAGES
R
I
>
R
I
V
I
+
+ V
O
30mA
(V
I
V
EE
+ 0.7V)
R
I
>
30mA
(V
I
V
EE
0.7V)
R
I
>
AD8651
03301-B
-
055
Figure 54. Input Protection Method
Overdrive Recovery
Overdrive recovery is defined as the time it takes for the output
of an amplifier to come off the supply rail after an overload
signal is initiated. This is usually tested by placing the amplifier
in a closed-loop gain of 15 with an input square wave of
200 mV p-p while the amplifier is powered from either 5 V or
3 V. The AD8651 has excellent recovery time from overload
conditions (see Figure 31 and Figure 32). The output recovers
from the positive supply rail within 200 ns at all supply voltages.
Recovery from the negative rail is within 100 ns at 5 V supply.
LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Power Supply Bypassing
Power supply pins can act as inputs for noise, so care must be
taken that a noise-free, stable dc voltage is applied. The purpose
of bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering most
of the noise. Bypassing schemes are designed to minimize the
supply impedance at all frequencies with a parallel combination
of capacitors of 0.1 F and 4.7 F. Chip capacitors of 0.1 F
(X7R or NPO) are critical and should be as close as possible to
the amplifier package. The 4.7 F tantalum capacitor is less
critical for high frequency bypassing, and, in most cases, only
one is needed per board at the supply inputs.
Grounding
A ground plane layer is important for densely packed PC
boards to spread the current-minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of parasitic inductances and, therefore, the high
frequency impedance of the path. High speed currents in an
inductive ground return will create an unwanted voltage noise.
The length of the high frequency bypass capacitor leads is
critical. A parasitic inductance in the bypass grounding will
work against the low impedance created by the bypass capacitor.
Place the ground leads of the bypass capacitors at the same
physical location. Because load currents also flow from the
supplies, the ground for the load impedance should be at the
same physical location as the bypass capacitor grounds. For the
larger value capacitors, intended to be effective at lower fre-
quencies, the current return path distance is less critical.
Leakage Currents
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the AD8651/AD8652. Any voltage
differential between the inputs and nearby traces will set up
leakage currents through the PC board insulator, for example,
1 V/100 G = 10 pA. Similarly, any contaminants on the board
can create significant leakage (skin oils are a common problem).
To significantly reduce leakages, put a guard ring (shield)
around the inputs and input leads that are driven to the same
voltage potential as the inputs. This ensures that there is no
voltage potential between the inputs and the surrounding area
to set up any leakage currents. To be effective, the guard ring
must be driven by a relatively low impedance source and should
completely surround the input leads on all sides, above and
below, using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the
amount of material between the input leads and the guard
ring will help to reduce the absorption. Also, low absorption
materials, such as Teflon or ceramic, may be necessary in
some instances.
Input Capacitance
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and
ground. A few picofarads of capacitance will reduce the input
impedance at high frequencies, which in turn increases the
amplifier's gain, causing peaking in the frequency response or
AD8651/AD8652
Rev. B | Page 16 of 20
oscillations. With the AD8651, additional input damping is
required for stability with capacitive loads greater than 47 pF
with direct input to output feedback (see the next section).
Output Capacitance
When using high speed amplifiers, it is important to consider
the effects of the capacitive loading on the amplifier's stability.
Capacitive loading interacts with the output impedance of the
amplifier, causing reduction of the BW as well as peaking and
ringing of the frequency response. To reduce the effects of the
capacitive loading and allow higher capacitive loads, there are
two commonly used methods:
1) As shown in Figure 55, place a small value resistor (R
S
) in
series with the output to isolate the load capacitor from the
amplifier's output. Heavy capacitive loads can reduce the phase
margin of an amplifier and cause the amplifier response to peak
or become unstable. The AD8651 is able to drive up to 47 pF in
a unity gain buffer configuration without oscillation or external
compensation. However, if an application will require a higher
capacitive load drive when the AD8651 is in unity gain, then
the use of external isolation networks can be used. The effect
produced by this resistor is to isolate the op amp output from
the capacitive load. The required amount of series resistance has
been tabulated in Table 5 for different capacitive load. While
this technique will improve the overall capacitive load drive for
the amplifier, its biggest drawback is that it reduces the output
swing of the overall circuit.
+
V
+
V
V
IN
0
0
0
3
2
U1
RL
CL
R
S
V
OUT
V
CC
AD8651
03301-B
-
056
Figure 55. Driving Large Capacitive Loads
Table 5. Optimum Values for Driving Large Capacitive Loads
CL R
S
100 pF
50
500 pF
35
1.0 nF
25
2) Another way to stabilize an op amp driving a large capacitive
load is to use a snubber network, as shown in Figure 56.
Because there is not any isolation resistor in the signal path, this
method has the significant advantage of not reducing the output
swing. The exact values of R
S
and C
S
are derived experimentally.
In Figure 56, an optimum R
S
and C
S
combination for a
capacitive load drive ranging from 50 pF to 1 nF was chosen.
For this, R
S
= 3 and C
S
= 10 nF were chosen.
+
V
+
V
200mV
RL
CL
R
S
C
S
V
OUT
V
+
V
AD8651
03301-B
-
057
Figure 56. Snubber Network
Settling Time
The settling time of an amplifier is defined as the time it takes
for the output to respond to a step change of input and enter
and remain within a defined error band, as measured relative to
the 50% point of the input pulse. This parameter is especially
important in measurements and control circuits where amplifi-
ers are used to buffer A/D inputs or DAC outputs. The design of
the AD8651 combines a high slew rate and a wide gain band-
width product to produce an amplifier with very fast settling
time. The AD8651 is configured in the noninverting gain of 1
with a 2 V p-p step applied to its input. The AD8651 has a
settling time of about 130 ns to 0.01% (2 mV). The output is
monitored with a 10, 10 M, 11.2 pF scope probe.
THD Readings vs. Common-Mode Voltage
Total harmonic distortion of the AD8651 is well below 0.0004%
with any load down to 600 . The distortion is a function of the
circuit configuration, the voltage applied, and the layout, in
addition to other factors. The AD8651 outperforms its
competitor for distortion, especially at frequencies below
20 kHz, as shown in Figure 57.
THD + NOIS
E
(%
)
0.0001
0.0002
0.0005
0.001
0.002
0.005
0.01
0.02
0.05
0.1
FREQUENCY (Hz)
AD8651
V
SY
= +3.5V/1.5V
V
OUT
= 2.0V p-p
20
50
100
500
20k
5k
2k
1k
OPA350
03301-B
-
058
Figure 57. Total Harmonic Distortion
+
V
IN
2V p-p
47pF
600
V
OUT
3.5V
1.5V
AD8651
03301-B
-
059
Figure 58. THD + N Test Circuit
AD8651/AD8652
Rev. B | Page 17 of 20
1
F
+
V
+
V
3
2
U1
IN
2.7nF
33
V
CC
5V
1k
10k
10k
1k
AD8651
AD7685
V
IN
0V 5V
f
IN
= 45kHz
03301-B
-
061
Driving a 16-Bit ADC
The AD8651 is an excellent choice for driving high speed, high
precision ADCs. The driver amplifier for this type of
application needs to have low THD + N as well as quick settling
time. Figure 60 shows a complete single-supply data acquisition
solution. The AD8651 drives the AD7685, a 250 kSPS, 16-bit
data converter.
1
The AD8651 is configured in an inverting gain of 1 with a 5 V
single supply. Input of 45 kHz is applied, and the ADC samples
at 250 kSPS. The results of this solution are listed in Table 6.
The advantage of this circuit is that the amplifier and ADC can
be powered with the same power supply. For the case of a
noninverting gain of 1, the input common-mode voltage
encompasses both supplies.
Figure 60. AD8651 Driving a 16-Bit ADC
Table 6. Data Acquisition Solution of Figure 60
Parameter Reading
(dB)
THD + N
105.2
SFDR 106.6
2
nd
Harmonics
107.7
3
rd
Harmonics
113.6
f
SAMPLE
= 250kSPS
f
IN
= 45kHz
INPUT RANGE = 0 TO 5V
03301-B
-
060
FREQUENCY (kHz)
AMP
L
ITUDE
(dB of Full S
c
a
l
e
)
0
160
100
120
140
80
60
40
20
0
10
20
30 40
50
60
70
80
90 100 110 120
1
For more information about the AD7685 data converter, go to
http://www.analog.com/Analog_Root/productPage/productHome/0%2C21
21%2CAD7685%2C00.html
Figure 59. Frequency Response of AD8651 Driving a 16-Bit ADC
Rev. B | Page 18 of 20
OUTLINE DIMENSIONS
0.80
0.60
0.40
8
0
4
8
5
4.90
BSC
PIN 1
0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 61. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8
5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 62. 8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
Package Description Package
Option Branding
AD8651ARM-REEL
40C to +125C
8-Lead MSOP
RM-8
BEA
AD8651ARM-R2
40C to +125C
8-Lead MSOP
RM-8
BEA
AD8651AR
40C to +125C
8-Lead SOIC
R-8
AD8651AR-REEL
40C to +125C
8-Lead SOIC
R-8
AD8651AR-REEL7
40C to +125C
8-Lead SOIC
R-8
AD8652ARMZ-R2
*
40C to +125C
8-Lead MSOP
RM-8
A05
AD8652ARMZ-REEL
*
40C to +125C
8-Lead MSOP
RM-8
A05
AD8652ARZ
*
40C to +125C
8-Lead SOIC
R-8
AD8652ARZ-REEL
*
40C to +125C
8-Lead SOIC
R-8
AD8652ARZ-REEL7
*
40C to +125C
8-Lead SOIC
R-8
*
Z = Pb-free part.
AD8651/AD8652
Rev. B | Page 19 of 20
NOTES
Rev. B | Page 20 of 20
NOTES
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03301-0-9/04(B)
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