REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
10-Bit 60 MSPS
A/D Converter
AD9020
FUNCTIONAL BLOCK DIAGRAM
V
S
+V
S
2
56
1
512
C
O
M
P
A
R
A
T
O
R
L
A
T
C
H
E
S
OVERFLOW
OVERFLOW
1024
10
7
59
61
128
129
256
257
384
385
51
50
49
48
47
46
23
22
21
20
19
OVERFLOW
R
R/2
R
R/2
R
R/2
R
R/2
R
R/2
R
R/2
R
R
11
L
A
T
C
H
63
12
57
14
ENCODE
ANALOG IN
GROUND
OVERFLOW
D
9
D
8
(MSB)
(LSB)
LSBS
INVERT
MSB
INVERT
R/2
R/2
1
3/4
REF
8
9
+V
REF
+V
SENSE
D
E
C
O
D
E
L
O
G
I
C
1/2
REF
1/4
REF
V
REF
V
SENSE
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
FEATURES
Monolithic 10-Bit/60 MSPS Converter
TTL Outputs
Bipolar ( 1.75 V) Analog Input
56 dB SNR @ 2.3 MHz Input
Low (45 pF) Input Capacitance
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Digital Oscilloscopes
Medical Imaging
Professional Video
Radar Warning/Guidance Systems
Infrared Systems
GENERAL DESCRIPTION
The AD9020 A/D converter is a 10-bit monolithic converter
capable of word rates of 60 MSPS and above. Innovative archi-
tecture using 512 input comparators instead of the traditional
1024 required by other flash converters reduces input capaci-
tance and improves linearity.
Encode and outputs are TTL-compatible, making the AD9020
an ideal candidate for use in low power systems. An overflow
bit is provided to indicate analog input signals greater than
+V
SENSE
.
Voltage sense lines are provided to insure accurate driving of the
V
REF
voltages applied to the units. Quarter-point taps on the
resistor ladder help optimize the integral linearity of the unit.
Either 68-pin ceramic leaded (gull wing) packages or ceramic
LCCs are available and are specifically designed for low thermal
impedances. Two performance grades for temperatures of both
0
C to +70
C and 55
C to +125
C ranges are offered to allow
the user to select the linearity best suited for each application.
Dynamic performance is fully characterized and production
tested at +25
C. MIL-STD-883 units are available.
The AD9020 A/D Converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Prod-
ucts Databook or current AD9020/883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A
.Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1997
REV. A
2
AD9020SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Test
AD9020JE/JZ
AD9020KE/KZ
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Min
Typ
Max
Units
RESOLUTION
10
10
Bits
DC ACCURACY
3
Differential Nonlinearity
+25
C
I
1.0
1.25
0.75
1.0
LSB
Full
VI
1.5
1.25
LSB
Integral Nonlinearity
+25
C
I
1.25
2.0
1.0
1.5
LSB
Full
VI
2.5
2.0
LSB
No Missing Codes
Full
VI
Guaranteed
ANALOG INPUT
Input Bias Current
4
+25
C
I
0.4
1.0
0.4
1.0
mA
Full
VI
2.0
2.0
mA
Input Resistance
+25
C
I
2.0
7.0
2.0
7.0
k
Input Capacitance
4
+25
C
V
45
45
pF
Analog Bandwidth
+25
C
V
175
175
MHz
REFERENCE INPUT
Reference Ladder Resistance
+25
C
I
22
37
56
22
37
56
Full
VI
14
66
14
66
Ladder Tempco
Full
V
0.1
0.1
/
C
Reference Ladder Offset
Top of Ladder
+25
C
I
45
90
45
90
mV
Full
VI
90
90
mV
Bottom of Ladder
+25
C
I
45
90
45
90
mV
Full
VI
90
90
mV
Offset Drift Coefficient
Full
V
50
50
V/
C
SWITCHING PERFORMANCE
Conversion Rate
+25
C
I
60
60
MSPS
Aperture Delay (t
A
)
+25
C
V
1
1
ns
Aperture Uncertainty (Jitter)
+25
C
V
5
5
ps, rms
Output Delay (t
OD
)
5
+25
C
I
6
10
13
6
10
13
ns
Output Time Skew
5
+25
C
I
3
5
3
5
ns
DYNAMIC PERFORMANCE
Transient Response
+25
C
V
10
10
ns
Overvoltage Recovery Time
+25
C
V
10
10
ns
Effective Number of Bits (ENOB)
f
IN
= 2.3 MHz
+25
C
I
8.6
9.0
8.6
9.0
Bits
f
IN
= 10.3 MHz
+25
C
IV
8.0
8.4
8.0
8.4
Bits
f
IN
= 15.3 MHz
+25
C
IV
7.5
8.0
7.5
8.0
Bits
Signal-to-Noise Ratio
6
f
IN
= 2.3 MHz
+25
C
I
54
56
54
56
dB
f
IN
= 10.3 MHz
+25
C
I
50
53
50
53
dB
f
IN
= 15.3 MHz
+25
C
I
47
50
47
50
dB
Signal-to-Noise Ratio
6
(Without Harmonics)
f
IN
= 2.3 MHz
+25
C
I
54
56
54
56
dB
f
IN
= 10.3 MHz
+25
C
I
51
54
51
54
dB
f
IN
= 15.3 MHz
+25
C
I
48
52
48
52
dB
( V
S
= 5 V; V
SENSE
= 1.75 V; ENCODE = 40 MSPS unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS
1
+V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V to +2 V
+V
REF
, V
REF
, 3/4
REF
, 1/2
REF
, 1/4
REF
. . . . . . . . . . 2 V to +2 V
+V
REF
to V
REF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
DIGITAL INPUTS . . . . . . . . . . . . . . . . . . . . . . .0.5 V to +V
S
3/4
REF
, 1/2
REF
, 1/4
REF
Current . . . . . . . . . . . . . . . . . . .
10 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature
AD9020JE/KE/JZ/KZ . . . . . . . . . . . . . . . . . . 0
C to +70
C
Storage Temperature . . . . . . . . . . . . . . . . . . . 65
C to +150
C
Maximum Junction Temperature
2
. . . . . . . . . . . . . . . . +175
C
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300
C
Test
AD9020JE/JZ
AD9020KE/KZ
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Min
Typ
Max
Units
DYNAMIC PERFORMANCE (continued)
Harmonic Distortion
f
IN
= 2.3 MHz
+25
C
I
61
67
61
67
dBc
f
IN
= 10.3 MHz
+25
C
I
55
59
55
59
dBc
f
IN
= 15.3 MHz
+25
C
I
49
53
49
53
dBc
Two-Tone Intermodulation
Distortion Rejection
7
+25
C
V
70
70
dBc
Differential Phase
+25
C
V
0.5
0.5
Degree
Differential Gain
+25
C
V
1
1
%
ENCODE INPUT
Logic "1" Voltage
Full
VI
2.0
2.0
V
Logic "0" Voltage
Full
VI
0.8
0.8
V
Logic "1" Current
Full
VI
20
20
A
Logic "0" Current
Full
VI
800
800
A
Input Capacitance
+25
C
V
5
5
pF
Pulse Width (High)
+25
C
I
6
6
ns
Pulse Width (Low)
+25
C
I
6
6
ns
DIGITAL OUTPUTS
Logic "1" Voltage (I
OH
= 2 mA)
Full
VI
2.4
2.4
V
Logic "0" Voltage (I
OL
= 6 mA)
Full
VI
0.4
V
POWER SUPPLY
+V
S
Supply Current
+25
C
I
440
530
440
530
mA
Full
VI
542
542
mA
V
S
Supply Current
+25
C
I
140
170
140
170
mA
Full
VI
177
177
mA
Power Dissipation
+25
C
I
2.8
3.3
2.8
3.3
W
Full
VI
3.4
3.4
W
Power Supply Rejection
Ratio (PSRR)
8
Full
VI
6
10
6
10
mV/V
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and beyond which the service ability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances (part soldered onto board): 68-pin leaded ceramic chip carrier:
JC
= 1
C/W;
JA
= 17
C/W (no air flow);
JA
= 15
C/W
(air flow = 500 LFM). 68-pin ceramic LCC:
JC
= 2.6
C/W;
JA
= 15
C/W (no air flow);
JA
= 13
C/W (air flow = 500 LFM).
3
3/4
REF
, 1/2
REF
, and 1/4
REF
reference ladder taps are driven from dc sources at +0.875 V, 0 V, and 0.875 V, respectively. Accuracy of the overflow comparator is not
tested and not included in linearity specifications.
4
Measured with ANALOG IN = +V
SENSE
.
5
Output delay measured as worst-case time from 50% point of the rising edge of ENCODE to 50% point of the slowest rising or falling edge of D
0
D
9
. Output skew
measured as worst-case difference in output delay among D
0
D
9
.
6
RMS signal to rms noise with analog input signal 1 dB below full scale at specified frequency.
7
Intermodulation measured with analog input frequencies of 2.3 MHz and 3.0 MHz at 7 dB below full scale.
8
Measured as the ratio of the worst-case change in transition voltage of a single comparator for a 5% change in +V
S
or V
S
.
Specifications subject to change without notice.
REV. A
3
AD9020
AD9020
4
REV. A
ORDERING GUIDE
Temperature
Package
Device
Range
Description
Option*
AD9020JZ
0
C to +70
C
68-Pin Leaded Ceramic
Z-68
AD9020JE
0
C to +70
C
68-Terminal Ceramic LCC E-68A
AD9020KZ
0
C to +70
C
68-Pin Leaded Ceramic
Z-68
AD9020KE
0
C to +70
C
68-Terminal Ceramic LCC E-68A
AD9020SZ/883 55
C to +125
C
68-Pin Leaded Ceramic
Z-68
AD9020SE/883 55
C to +125
C
68-Terminal Ceramic LCC E-68A
AD9020TZ/883 55
C to +125
C
68-Pin Leaded Ceramic
Z-68
AD9020TE/883 55
C to +125
C
68-Terminal Ceramic LCC E-68A
AD9020/PCB
0
C to +70
C
Evaluation Board
*E = Ceramic Leadless Chip Carrier; Z = Ceramic Leaded Chip Carrier.
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . . 206 140 15 (
2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
S
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
AD9020
4,5,13,17,
27,31,32,
36,38,39,
43,53,66,67
100
510
ANALOG IN
ENCODE
GROUND
2,16,28,29,35,
41,42,54,64
0.1
F
0.1
F
510
510
AD1
AD2
3,6,15,18,25,30,33,34,
37,40,45,52,55,65,68
STATIC:
DYNAMIC:
AD1 = 2V; AD2 = +2.4V
AD1 =
2V TRIANGLE WAVE
AD2 = TTL PULSE TRAIN
9
46
19
14
23
51
12
8
56
59
61
+2V
2V
REF
V
+
REF
V
_
S
V
D
5
9
D
D
0
4
D
S
+V
5.0V
+
5.2V
LSBs INVERT
MSB INVERT
AD9020 Burn-In Circuit
EXPLANATION OF TEST LEVELS
Test Level
I
100% production tested.
II 100% production tested at +25
C, and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V
Parameter is a typical value only.
VI All devices are 100% production tested at +25
C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
AD9020
5
REV. A
NC = NO CONNECT
60
9
10
61
44
43
27
26
AD9020
TOP VIEW
(Not to Scale)
NC
+V
SENSE
+V
REF
GND
ENCODE
GND
(LSB) D
0
D
1
D
2
NC
NC
ANALOG IN
ANALOG IN
3/4
REF
+V
S
GND
GND
V
S
1/2
REF
1/4
REF
NC
GND
GND
MSB INVERT
NC
LSBs INVERT
NC
GND
OVERFLOW
D
9
(MSB)
NC
GND
GND
GND
GND
GND
GND
GND
+V
S
+V
S
+V
S
V
S
+V
S
+V
S
V
S
D
3
D
4
+V
S
V
SENSE
V
REF
+V
S
V
S
+V
S
D
8
D
7
D
6
D
5
+V
S
V
S
V
S
+V
S
+V
S
+V
S
V
S
+V
S
+V
S
V
S
V
S
AD9020 PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Function
1
1/2
REF
Midpoint of internal reference ladder.
2, 16, 28, 29, 35, 41, 42,
V
S
Negative supply voltage; nominally 5.0 V
5%.
54, 64
3, 6, 15, 18, 25, 30, 33, 34,
+V
S
Positive supply voltage; nominally +5 V
5%.
37, 40, 45, 52, 55, 65, 68
4, 5, 13, 17, 27, 31, 32,
GROUND
All ground pins should be connected together and to low impedance ground
36, 38, 39, 43, 53, 66, 67
plane.
7
3/4
REF
Three-quarter point of internal reference ladder.
8, 9
ANALOG IN
Analog input; nominally between
1.75 V.
11
+V
SENSE
Voltage sense line to most positive point on internal resistor ladder.
Normally +1.75 V.
12
+V
REF
Voltage force connection for top of internal reference ladder. Normally driven
to provide +1.75 V at +V
SENSE
.
14
ENCODE
TTL-compatible convert command used to begin digitizing process.
1923, 4650
D
0
D
9
TTL-compatible digital output data.
51
OVERFLOW
TTL-compatible output indicating ANALOG IN > +V
SENSE
.
56
V
REF
Voltage force connection for bottom of internal reference ladder. Normally
driven to provide 1.75 V at V
SENSE
.
57
V
SENSE
Voltage sense line to most negative point on internal resistor ladder.
Normally 1.75 V.
59
LSBs INVERT
Normally grounded. When connected to +V
S
, lower order bits (D
0
D
8
) are
inverted.
61
MSB INVERT
Normally grounded. When connected to +V
S
, most significant bit (MSB; D
9
)
is inverted.
63
1/4
REF
One-quarter point of internal reference ladder.
AD9020
6
REV. A
THEORY OF OPERATION
Refer to the AD9020 block diagram. As shown, the AD9020
uses a modified "flash," or parallel, A/D architecture. The ana-
log input range is determined by an external voltage reference
(+V
REF
and V
REF
), nominally
1.75 V. An internal resistor lad-
der divides this reference into 512 steps, each representing two
quantization levels. Taps along the resistor ladder (1/4
REF
,
1/2
REF
and 3/4
REF
) are provided to optimize linearity. Rated per-
formance is achieved by driving these points at 1/4, 1/2 and 3/4,
respectively, of the voltage reference range.
The A/D conversion for the nine most significant bits (MSBs) is
performed by 512 comparators. The value of the least signifi-
cant bit (LSB) is determined by a unique interpolation scheme
between adjacent comparators. The decoding logic processes
the comparator outputs and provides a 10-bit code to the output
stage of the converter.
Flash architecture has an advantage over other A/D architec-
tures because conversion occurs in one step. This means the
performance of the converter is primarily limited by the speed
and matching of the individual comparators. In the AD9020, an
innovative interpolation scheme takes advantage of flash archi-
tecture but minimizes the input capacitance, power and device
count usually associated with that method of conversion.
These advantages occur by using only half the normal number
of input comparator cells to accomplish the conversion. In addi-
tion, a proprietary decoding scheme minimizes error codes. In-
put control pins allow the user to select from among Binary,
Inverted Binary, Twos Complement and Inverted Twos
Complement coding (see AD9020 Truth Table).
APPLICATIONS
Many of the specifications used to describe analog/digital con-
verters have evolved from system performance requirements in
these applications. Different systems emphasize particular speci-
fications, depending on how the part is used. The following ap-
plications highlight some of the specifications and features that
make the AD9020 attractive in these systems.
Wideband Receivers
Radar and communication receivers (baseband and direct IF
digitization), ultrasound medical imaging, signal intelligence
and spectral analysis all place stringent ac performance require-
ments on analog-to-digital converters (ADCs). Frequency do-
main characterization of the AD9020 provides signal-to-noise
ratio (SNR) and harmonic distortion data to simplify selection
of the ADC.
Receiver sensitivity is limited by the Signal-to-Noise Ratio of the
system. The SNR for an ADC is measured in the frequency do-
main and calculated with a Fast Fourier Transform (FFT). The
SNR equals the ratio of the fundamental component of the sig-
nal (rms amplitude) to the rms value of the noise. The noise is
the sum of all other spectral components, including harmonic
distortion, but excluding dc.
Good receiver design minimizes the level of spurious signals in
the system. Spurious signals developed in the ADC are the re-
sult of imperfections in the device transfer function (non-
linearities, delay mismatch, varying input impedance, etc.). In
the ADC, these spurious signals appear as Harmonic Distortion.
Harmonic Distortion is also measured with an FFT and is speci-
fied as the ratio of the fundamental component of the signal
(rms amplitude) to the rms value of the worst case harmonic
(usually the 2nd or 3rd).
Two-Tone Intermodulation Distortion (IMD) is a frequently cited
specification in receiver design. In narrow-band receivers, third-
order IMD products result in spurious signals in the pass band
of the receiver. Like mixers and amplifiers, the ADC is charac-
terized with two, equal-amplitude, pure input frequencies. The
IMD equals the ratio of the power of either of the two input sig-
nals to the power of the strongest third-order IMD signal. Un-
like mixers and amplifiers, the IMD does not always behave as it
does in linear devices (reduced input levels do not result in pre-
dictable reductions in IMD).
Performance graphs provide typical harmonic and SNR data for
the AD9020 for increasing analog input frequencies. In choos-
ing an A/D converter, always look at the dynamic range for the
analog input frequency of interest. The AD9020 specifications
provide guaranteed minimum limits at three analog test
frequencies.
Aperture Delay is the delay between the rising edge of the EN-
CODE command and the instant at which the analog input is
sampled. Many systems require simultaneous sampling of more
than one analog input signal with multiple ADCs. In these situ-
ations, timing is critical and the absolute value of the aperture
delay is not as critical as the matching between devices.
Aperture Uncertainty, or jitter, is the sample-to-sample variation
in aperture delay. This is especially important when sampling
high slew rate signals in wide bandwidth systems. Aperture un-
certainty is one of the factors that degrade dynamic performance
as the analog input frequency is increased.
AD9020
7
REV. A
Digitizing Oscilloscopes
Oscilloscopes provide amplitude information about an observed
waveform with respect to time. Digitizing oscilloscopes must ac-
curately sample this signal, without distorting the information to
be displayed.
One figure of merit for the ADC in these applications is Effective
Number of Bits (ENOBs). ENOB is calculated with a sine wave
curve fit and equals:
ENOB = N LOG
2
[Error (measured)/Error (ideal)]
N is the resolution (number of bits) of the ADC. The measured
error is the actual rms error calculated from the converter out-
puts with a pure sine wave input.
The Analog Bandwidth of the converter is the analog input fre-
quency at which the spectral power of the fundamental signal is
reduced 3 dB from its low frequency value. The analog band-
width is a good indicator of a converter's stewing capabilities.
The Maximum Conversion Rate is defined as the encode rate at
which the SNR for the lowest analog signal test frequency tested
drops by no more than 3 dB below the guaranteed limit.
Imaging
Visible and infrared imaging systems both require similar char-
acteristics from ADCs. The signal input (from a CCD camera,
or multiplexer) is a time division multiplexed signal consisting of
a series of pulses whose amplitude varies in direct proportion to
the intensity of the radiation detected at the sensor. These vary-
ing levels are then digitized by applying encode commands at
the correct times, as shown below.
ENCODE
A
IN
AD9020
FS
+
FS
Imaging Application Using AD9020
The actual resolution of the converter is limited by the thermal
and quantization noise of the ADC. The low frequency test for
SNR or ENOB is a good measure of the noise of the AD9020.
At this frequency, the static errors in the ADC determine the
useful dynamic range of the ADC.
Although the signal being sampled does not have a significant
slew rate, this does not imply dynamic performance is not im-
portant. The Transient Response and Overvoltage Recovery Time
specifications insure that the ADC can track full-scale changes
in the analog input sufficiently fast to capture a valid sample.
Transient Response is the time required for the AD9020 to
achieve full accuracy when a step function is applied. Overvolt-
age Recovery Time is the time required for the AD9020 to re-
cover to full accuracy after an analog input signal 150% of full
scale is reduced to the full-scale range of the converter.
Professional Video
Digital Signal Processing (DSP) is now common in television
production. Modern studios rely on digitized video to create
state-of-the-art special effects. Video instrumentation also re-
quires high resolution ADCs for studio quality measurement
and frame storage.
The AD9020 provides sufficient resolution for these demanding
applications. Conversion speed, dynamic performance and ana-
log bandwidth are suitable for digitizing both composite and
RGB video sources.
AD9020
8
REV. A
USING THE AD9020
Voltage References
The AD9020 requires that the user provide two voltage refer-
ences: +V
REF
and V
REF
. These two voltages are applied across
an internal resistor ladder (nominally 37
) and set the analog
input voltage range of the converter. The voltage references
should be driven from a stable, low impedance source. In addi-
tion to these two references, three evenly spaced taps on the re-
sistor ladder (1/4
REF
, 1/2
REF
, 3/4
REF
) are available. Providing a
reference to these quarter points on the resistor ladder will im-
prove the integral linearity of the converter and improve ac per-
formance. (AC and dc specifications are tested while driving the
quarter points at the indicated levels.) The figure below is not
intended to show the transfer function of the ADC, but illus-
trates how the linearity of the device is affected by reference
voltages applied to the ladder.
Effect of Reference Taps on Linearity
Resistance between the reference connections and the taps of
the first and last comparators causes offset errors. These errors,
called "top and bottom of the ladder offsets," can be nulled by
using the voltage sense lines, +V
SENSE
and V
SENSE
, to adjust the
reference voltages. Current through the sense lines should be
limited to less than 100
A. Excessive current drawn through
the voltage sense lines will affect the accuracy of the sense line
voltage.
The next page shows a reference circuit which nulls out the off-
set errors using two op amps and provides appropriate voltage
references to the quarter-point taps. Feedback from the sense
lines causes the op amps to compensate for the offset errors.
The two transistors limit the amount of current drawn directly
from the op amps; resistors at the base connections stabilize
their operation. The 10 k
resistors (R1R4) between the volt-
age sense lines form an external resistor ladder; the quarter
point voltages are taken off this external ladder and buffered by
an op amp. The actual values of resistors R1R4 are not critical,
but they should match well and be large enough (
10 k
) to
limit the amount of current drawn from the voltage sense lines.
The select resistors (R
S
) shown in the schematic (each pair can
be a potentiometer) are chosen to adjust the quarter-point volt-
age references, but are not necessary if R1R4 match within
0.05%.
An alternative approach for defining the quarter-point refer-
ences of the resistor ladder is to evaluate the integral linearity
error of an individual device, and adjust the voltage at the
quarter-points to minimize this error. This may improve the low
frequency ac performance of the converter.
Performance of the AD9020 has been optimized with an analog
input voltage of
1.75 V (as measured at
V
SENSE
). If the ana-
log input range is reduced below these values, relatively larger
differential nonlinearity errors may result because of comparator
mismatches. As shown in the figure below, performance of the
converter is a function of
V
SENSE
.
EFFECTIVE NUMBER OF BITS (ENOB)
SIGNAL-TO-NOISE (SNR) dB
32
38
44
50
56
62
10.0
9.0
8.0
7.0
6.0
5.0
0.4
0.8
1.0
1.4
1.8
2.0
V
SENSE
Volts
0.6
1.2
1.6
AD9020 SNR and ENOB vs. Reference Voltage
Applying a voltage greater than 4 V across the internal resistor
ladder will cause current densities to exceed rated values, and
may cause permanent damage to the AD9020. The design of
the reference circuit should limit the voltage available to the
references.
Analog Input Signal
The signal applied to ANALOG IN drives the inputs of 512
parallel comparator cells (see Equivalent Analog Input figure).
This connection typically has an input resistance of 7 k
, and
input capacitance of 45 pF. The input capacitance is nearly
constant over the analog input voltage range, as shown in the
graph which illustrates that characteristic.
The analog input signal should be driven from a low distortion,
low noise amplifier. A good choice is the AD9617, a wide band-
width, monolithic operational amplifier with excellent ac and dc
performance. The input capacitance should be isolated by a
small series resistor (24
for the AD9617) to improve the ac
performance of the amplifier (see AD9020/PCB Evaluation
Board Block Diagram).
AD9020
9
REV. A
ANALOG INPUT
3/4
REF
1/2
REF
1/4
REF
+V
SENSE
V
SENSE
AD9020 Equivalent Analog Input
DIGITAL BITS
AND OVERFLOW
S
V
+
AD9020 Equivalent Digital Outputs
13k
14
ENCODE
5.0V
+
AD9020 Equivalent Encode Circuit
0.875V
= WIRING
TO COMPARATORS
1.75V
0.1
F
R3
R4
0.1
F
AD580
0V
10k
R1
R
S
0.1
F
10k
R2
0.1
F
150
AD9020
+V
REF
V
REF
R
R/2
R
R/2
R
R/2
R
R/2
R
R/2
R
R/2
R
R
12
V
SENSE
+V
SENSE
R/2
R/2
*
*
3/4
REF
1/2 AD708
1/2 AD708
1/2 AD708
1/2 AD708
1/2 AD708
0.1
F
+5V
+1.75V
*
RESISTANCE = < 5
+0.875V
5V
R
S
1/2
REF
R
S
R
S
150
+2.5V
+1.75V
356
10k
1/4
REF
10k
20k
20k
150
11
7
1
63
56
57
AD9020 Reference Circuit
AD9020
10
REV. A
DATA FOR N
DATA FOR N + 1
DATA
OUTPUT
N
N + 1
N
N + 1
ANALOG
INPUT
ENCODE
Aperture Delay
Output Delay
t
OD
t
a
t
OD
t
a
AD9020 Timing Diagram
Timing
In the AD9020, the rising edge of the ENCODE signal triggers
the A/D conversion by latching the comparators. (See the
AD9020 Timing Diagram.)
The ENCODE is TTL/CMOS compatible and should be driven
from a low jitter (phase noise) source. Jitter on the ENCODE
signal will raise the noise floor of the converter. Fast, clean
edges will reduce the jitter in the signal and allow optimum ac
performance. Locking the system clock to a crystal oscillator
also helps reduce jitter. The AD9020 is designed to operate with
a 50% duty cycle; small (10%) variations in duty cycle should
not degrade performance.
Data Format
The format of the output data (D
0
D
9
) is controlled by the
MSB INVERT and LSBs INVERT pins. These inputs are dc
control inputs, and should be connected to GROUND or +V
S
.
The AD9020 Truth Table gives information to choose from
among Binary, Inverted Binary, Twos Complement and In-
verted Twos Complement coding.
The OVERFLOW output is an indication that the analog input
signal has exceeded the voltage at +V
SENSE
. The accuracy of the
overflow transition voltage and output delay are not tested or in-
cluded in the data sheet limits. Performance of the overflow in-
dicator is dependent on circuit layout and slew rate of the
encode signal. The operation of this function does not affect the
other data bits (D
0
D
9
). It is not recommended for applications
requiring a critical measure of the analog input voltage.
Layout and Power Supplies
Proper layout of high speed circuits is always critical but is par-
ticularly important when both analog and digital signals are
involved.
Analog signal paths should be kept as short as possible and be
properly terminated to avoid reflections. The analog input volt-
age and the voltage references should be kept away from digital
signal paths; this reduces the amount of digital switching noise
that is capacitively coupled into the analog section of the circuit.
Digital signal paths should also be kept short, and run lengths
should be matched to avoid propagation delay mismatch.
In high speed circuits, layout of the ground circuit is a critical
factor. A single, low impedance ground plane, on the compo-
nent side of the board, will reduce noise on the circuit ground.
Power supplies should be capacitively coupled to the ground
plane to reduce noise in the circuit. Multilayer boards allow
designers to lay out signal traces without interrupting the
ground plane and provide low impedance power planes.
It is especially important to maintain the continuity of the
ground plane under and around the AD9020. In systems with
dedicated digital and analog grounds, all grounds of the
AD9020 should be connected to the analog ground plane.
The power supplies (+V
S
and V
S
) of the AD9020 should be iso-
lated from the supplies used for external devices; this further re-
duces the amount of noise coupled into the A/D converter.
Sockets limit the dynamic performance and should be used only
for prototypes or evaluation--PCK Elastomerics Part # CCS-68-
55 is recommended for the LCC package. (Tel. 215-672-0787)
An evaluation board is available to aid designers and provide a
suggested layout.
AD9020
11
REV. A
1
2
4
6 8 10
20
60
100
200
40
EFFECTIVE NUMBER OF BITS (ENOB)
INPUT FREQUENCY MHz
SIGNAL-TO-NOISE (SNR) dB
20
26
32
38
44
50
56
62
10.0
9.0
8.0
7.0
6.0
5.0
4.0
ENCODE RATE = 40MSPS
+25
C
+55
C & +125
C
AD9020 SNR and ENOB vs. Input Frequency
1
2
4
6
8 10
20
60
100
40
HARMONICS dBc
40
45
50
55
60
65
70
INPUT FREQUENCY MHz
35
30
+125 C
55 C
+25 C
AD9020 Harmonics vs. Input Frequency
EFFECTIVE NUMBER OF BITS (ENOB)
SIGNAL-TO-NOISE (SNR) dB
20
26
32
38
44
50
56
62
10.0
9.0
8.0
7.0
6.0
5.0
4.0
1
2
4
6
8 10
20
40
100
CONVERSION RATE MSPS
60
ANALOG INPUT = 2.3MHz
AD9020 SNR and ENOB vs. Conversion Rate
INPUT CAPACITANCE pF
ANALOG INPUT Volts
(A )
IN
48
47
45
44
1.8
1.2
0.6
0
10
70
60
50
40
30
20
INPUT RESISTANCE k
0.6
+
1.2
+
1.8
+
46
RESISTANCE
CAPACITANCE
Input Capacitance/Resistance vs. Input Voltage
AD9020 Truth Table
Offset Binary
Twos Complement
Step
Range
True
Inverted
True
Inverted
0 = 1.75 V
MSB INV = "0"
MSB INV = "1"
MSB INV = "1"
MSB INV = "0"
FS = +1.75 V
LSBs INV = "0"
LSBs INV = "1"
LSBs INV = "0"
LSBs INV = "1"
1024
> +1.7500
(1)1111111111
(1)0000000000
(1)0111111111
(1)1000000000
1023
+1.7466
1111111111
0000000000
0111111111
1000000000
1022
+1.7432
1111111110
0000000001
0111111110
1000000001
512
+0.0034
1000000000
0111111111
0000000000
1111111111
511
0.000
0111111111
1000000000
1111111111
0000000000
510
0.0034
0111111110
1000000001
1111111110
0000000001
02
1.7432
0000000010
1111111101
1000000010
0111111101
01
1.7466
0000000001
1111111110
1000000001
0111111110
00
<1.7466
0000000000
1111111111
1000000000
0111111111
The overflow bit is always 0 except where noted in parentheses ( ). MSB INVERT and LSBs INVERT are considered dc controls.
AD9020
12
REV. A
C1348b06/97
PRINTED IN U.S.A.
AD9020/PCB EVALUATION BOARD
The AD9020/PCB Evaluation Board is available from the fac-
tory and is shown here in block diagram form. The board in-
cludes a reference circuit that allows the user to adjust both
references and the quarter-point voltages. The AD9617 is in-
cluded as the drive amplifier, and the user can configure the
gain from 1 to 15.
On-board reconstruction of the digital data is provided through
the AD9713, a 12-bit monolithic DAC. The analog and recon-
structed waveforms can be summed on the board to allow the
user to observe the linearity of the AD9020 and the effects of
the quarterpoint voltages. The digital data and an adjustable
Data Ready signal are available through a 37-pin edge connector.
AD9020/PCB Evaluation Board Block Diagram
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Leaded Ceramic Chip Carrier
68-Terminal
(Z-68)
Leadless Chip Carrier (LCC)
(E-68A)
REFERENCE
CIRCUIT
AD9020
DUT
ANALOG
INPUT
50
DUT
ANALOG
INPUT
J2
200
400
24
BUFFERED
ANALOG
INPUT
TO ERROR
WAVEFORM
CIRCUIT
OUTPUT
DATA
CONNECTOR
TTL
LATCHES
TTL CLK
ENCODE
TIMING
CIRCUIT
CLK
Q
DATA
READY
50
DAC
OUT
TO ERROR
WAVEFORM
CIRCUIT
AD9617
U5
+V
S
V
S
AD9713 DAC
I
OUT
D
+V
REF
+V
SENSE
V
SENSE
V
REF
3/4
REF
1/2
REF
1/4
REF
MSB INVERT
5V
5V
+
LSBs INVERT
(LSB) D
0
D
1
D
8
(MSB) D
9
OVERFLOW
D
D
D
D
D
D
D
D
D
D
D
GND
+5V
D
2
D
3
D
4
D
5
D
6
D
7
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