FUNCTIONAL BLOCK DIAGRAM
ENCODE
AD9050
T/H
ADC
SUM
AMP
DAC
ADC
+5V
DECODE
LOGIC
TIMING
AIN
AINB
+5V
GND
REFERENCE CKTS
10
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD9050
FEATURES
Low Power: 315 mW @ 40 MSPS, 345 mW @ 60 MSPS
On-Chip T/H, Reference
Single +5 V Power Supply Operation
Selectable 5 V or 3 V Logic I/O
SNR: 53 dB Minimum at 10 MHz w/40 MSPS
APPLICATIONS
Medical Imaging
Instrumentation
Digital Communications
Professional Video
PRODUCT DESCRIPTION
The AD9050 is a complete 10-bit monolithic sampling analog-
to-digital converter (ADC) with an onboard track-and-hold and
reference. The unit is designed for low cost, high performance
applications and requires only +5 V and an encode clock to
achieve 40 MSPS or 60 MSPS sample rates with 10-bit resolution.
The encode clock is TTL compatible and the digital outputs
are CMOS; both can operate with 5 V/3 V logic, selected by the
user. The two-step architecture used in the AD9050 is opti-
mized to provide the best dynamic performance available while
maintaining low power consumption.
A 2.5 V reference is included onboard, or the user can provide
an external reference voltage for gain control or matching of
multiple devices. Fabricated on an advanced BiCMOS pro-
cess, the AD9050 is packaged in space saving surface mount
packages (SOIC, SSOP) and is specified over the industrial
(40
C to +85
C) temperature range. The 60 MSPS version
(AD9050BRS-60) is only available in the SSOP package.
+5V
10 BITS
0.1F
0.1F
0.1F
ENCODE
(2)
74AC574
3
4
10
5
6
9
1, 7, 12,
21, 23
13
2, 8, 11,
20, 22
AD9050
AIN
(+3.3V
0.512V)
+5V
Figure 1. Typical Connections
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1997
10-Bit, 40 MSPS/60 MSPS
A/D Converter
AD9050SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Test
AD9050BR/BRS
AD9050BRS-60
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Units
RESOLUTION
10
10
Bits
DC ACCURACY
Differential Nonlinearity
+25
C
I
0.75
1.75
0.85
1.85
LSB
Full
V
1.0
1.1
LSB
Integral Nonlinearity
+25
C
I
1.0
1.75
1.25
2.0
LSB
Full
V
1.25
1.50
LSB
No Missing Codes
Full
IV
GUARANTEED
GUARANTEED
Gain Error
+25
C
I
1.0
7.5
1.0
8.5
% FS
Gain Tempco
1
Full
V
100
100
ppm/
C
ANALOG INPUT
Input Voltage Range
+25
C
V
1.024
1.024
V p-p
Input Offset Voltage
+25
C
I
10
+7
+25
10
+7
+25
mV
Full
IV
32
+51
32
+51
mV
Input Resistance
+25
C
I
3.5
5.0
6.5
3.5
5.0
6.5
k
Input Capacitance
+25
C
V
5
5
pF
Analog Bandwidth
+25
C
V
100
100
MHz
BANDGAP REFERENCE
Output Voltage
+25
C
I
2.4
2.5
2.6
2.4
2.5
2.6
V
Temperature Coefficient
1
Full
V
50
50
ppm/
C
SWITCHING PERFORMANCE
Maximum Conversion Rate
+25
C
I
40
60
MSPS
Minimum Conversion Rate
+25
C
IV
1.5
3
1.5
3
MSPS
Aperture Delay (t
A
)
+25
C
V
2.7
2.7
ns
Aperture Uncertainty (Jitter)
+25
C
V
5
5
ps, rms
Output Propagation Delay (t
PD
)
2
Full
IV
5
15
5
15
ns
DYNAMIC PERFORMANCE
Transient Response
+25
C
V
10
10
ns
Overvoltage Recovery Time
+25
C
V
10
10
ns
ENOBS
f
IN
= 2.3 MHz
+25
C
V
8.93
8.93
ENOBs
f
IN
= 10.3 MHz
+25
C
I
8.51
8.85
8.15
8.51
ENOBs
Signal-to-Noise Ratio (SINAD)
3
f
IN
= 2.3 MHz
+25
C
V
55.5
55.5
dB
f
IN
= 10.3 MHz
+25
C
I
53
55
51
53
dB
Signal-to-Noise Ratio
(Without Harmonics)
f
IN
= 2.3 MHz
+25
C
V
56
56
dB
f
IN
= 10.3 MHz
+25
C
I
53.5
55.5
51.5
54.0
dB
2nd Harmonic Distortion
f
IN
= 2.3 MHz
+25
C
V
69
69
dBc
f
IN
= 10.3 MHz
+25
C
I
67
60
64
58.5
dBc
3rd Harmonic Distortion
f
IN
= 2.3 MHz
+25
C
V
75
75
dBc
f
IN
= 10.3 MHz
+25
C
I
70
58
62
57.5
dBc
Two-Tone Intermodulation
Distortion (IMD)
4
+25
C
V
65
65
dBc
Differential Phase
+25
C
V
0.15
0.15
Degrees
Differential Gain
+25
C
V
0.25
0.25
%
REV. B
2
(V
D
, V
DD
= +5 V; internal reference; ENCODE = 40 MSPS for BR/BRS, 60 MSPS for BRS-60
unless otherwise noted)
Test
AD9050BR/BRS
AD9050BRS-60
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Units
ENCODE INPUT
Logic "1" Voltage
Full
IV
2.0
2.0
V
Logic "0" Voltage
Full
IV
0.8
0.8
V
Logic "1" Current
Full
IV
1
1
A
Logic "0" Current
Full
IV
1
1
A
Input Capacitance
+25
C
V
10
10
pF
Encode Pulse Width High (t
EH
)
+25
C
IV
10
166
6.7
166
ns
Encode Pulse Width Low (t
EL
)
+25
C
IV
10
166
6.7
166
ns
DIGITAL OUTPUTS
Logic "1" Voltage
Full
IV
4.95
4.95
V
Logic "0" Voltage
Full
IV
0.05
0.05
V
Logic "1" Voltage (3.0 V
DD
)
Full
IV
2.95
2.95
V
Logic "0" Voltage (3.0 V
DD
)
Full
IV
0.05
0.05
V
Output Coding
Offset
Binary
Code
Offset
Binary
Code
POWER SUPPLY
V
D
, V
DD
Supply Current
5
Full
IV
40
63
80
40
69
87.2
mA
Power Dissipation
5
Full
IV
315
400
345
486
mW
Power Supply Rejection Ratio
(PSRR)
6
+25
C
I
10
10
mV/V
NOTES
1
"Gain Tempco" is for converter only; "Temperature Coefficient" is for bandgap reference only.
2
Output propagation delay (t
PD
) is measured from the 50% point of the rising edge of the encode command to the midpoint of the digital outputs with 10 pF maximum
loads.
3
RMS signal to rms noise with analog input signal 0.5 dB below full scale at specified frequency for BR/BRS, 1.0 dB below full scale for BRS-60.
4
Intermodulation measured relative to either tone with analog input frequencies of 9.5 MHz and 9.9 MHz at 7 dB below full scale.
5
Power dissipation is measured at full update rate with AIN of 10.3 MHz and digital outputs loaded with 10 pF maximum. See Figure 4 for power dissipation at other
conditions.
6
Measured as the ratio of the change in offset voltage for 5% change in +V
D
.
Specifications subject to change without notice.
AD9050
EXPLANATION OF TEST LEVELS
Test Level
I
100% Production Tested.
IV
Parameter is guaranteed by design and characteriza-
tion testing.
V
Parameter is a typical value only.
ABSOLUTE MAXIMUM RATINGS*
V
D
, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V
ANALOG IN . . . . . . . . . . . . . . . . . . . . . . 1.0 V to V
D
+ 1.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V
D
V
REF
Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to V
D
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature
AD9050BR/BRS/BRS-60 . . . . . . . . . . . . . . . 40
C to +85
C
Storage Temperature . . . . . . . . . . . . . . . . . . . 65
C to +150
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Option*
AD9050BR
40
C to +85
C
R-28
AD9050BRS
40
C to +85
C
RS-28
AD9050BRS-60
40
C to +85
C
RS-28
*R = Small Outline (SO); RS = Shrink Small Outline (SSOP).
REV. B
3
AD9050
4
REV. B
Table I. AD9050 Digital Coding (Single Ended Input AIN, AINB Bypassed to GND)
OR
Digital Output
Analog Input
Voltage Level
(Out of Range)
MSB . . . LSB
3.813
Positive Full Scale + 1 LSB
1
1111111111
3.300
Midscale
0
0111111111
2.787
Negative Full Scale 1 LSB
1
0000000000
PIN FUNCTION DESCRIPTIONS
Pin No
Name
Function
1, 7, 12, 21, 23
GND
Ground.
2, 8, 11
V
D
Analog +5 V
5% power supply.
3
VREF
OUT
Internal bandgap voltage reference (nominally +2.5 V).
4
VREF
IN
Input to reference amplifier. Voltage reference for ADC is connected here.
5
COMP
Internal compensation pin, 0.1
F bypass connected here to V
D
(+5 V).
6
REF
BP
External connection for (0.1
F) reference bypass capacitor.
9
AINB
Complementary analog input pin (Analog input bar).
10
AIN
Analog input pin.
13
ENCODE
Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding)
on rising edge of encode signal.
14
OR
Out of range signal. Logic "0" when analog input is in nominal range. Logic "1" when
analog input is out of nominal range.
15
D9 (MSB)
Most significant bit of ADC output.
1619
D8D5
Digital output bits of ADC.
20, 22
V
DD
Digital output power supply (only used by digital outputs).
2427
D4D1
Digital output bits of ADC.
28
D0 (LSB)
Least significant bit of ADC output.
PIN CONFIGURATION
14
13
12
11
10
9
8
1
2
3
4
7
6
5
17
16
15
20
19
18
28
27
26
25
24
23
22
21
TOP VIEW
(Not to Scale)
AD9050
GND
D3
D2
D1
D0 (LSB)
V
D
VREF
OUT
VREF
IN
V
DD
GND
D4
COMP
REF
BP
GND
V
D
AINB
AIN
D5
V
DD
GND
V
D
GND
ENCODE
OR
D6
D9 (MSB)
D8
D7
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9050 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD9050
5
REV. B
N
N + 1
N + 2
N + 3
N + 4
N + 5
AIN
ENCODE
DIGITAL
OUTPUTS
t
A
t
EH
t
EL
t
PD
N 5
N 4
N 3
N 2
N 1
N
MIN
TYP
MAX
t
A
APERTURE DELAY
2.7ns
t
EH
PULSE WIDTH HIGH
10ns*
166ns
t
EL
PULSE WIDTH LOW
10ns*
166ns
t
PD
OUTPUT PROP DELAY
5.0ns
8.2ns
15.0ns
*FOR BR/BRS, SEE SPECIFICATION TABLE
Figure 2. Timing Diagram
8k
16k
8k
16k
AINB (Pin 9)
AIN (Pin 10)
INPUT
BUFFER
V
D
V
D
VREF
IN
(Pin 4)
A
V
VREF
BF
(Pin 6)
V
DD
(Pins 20, 22)
+3V to +5V
D0D9, OR
V
D
ENCODE
(Pin 13)
V
D
VREF
OUT
(Pin 3)
Figure 3. Equivalent Circuits
Output Stage
Encode Input
Analog Input
V
REF
Output
Reference Circuit
AD9050Typical Performance Curves
REV. B
6
TEMPERATURE
C
60
55
40
20
SIGNAL-TO-NOISE RATIO dB
(SINAD)
0
20
40
60
80
59
56
54
53
58
57
ENCODE = 40 MSPS
A
IN
= 10.3 MHz
52
51
50
Figure 7. SNR vs. Temperature
FREQUENCY MHz
0
20
2.5
5
7.5
10
12.5
15
17.5
0
10
dB
50
60
70
30
40
20
100
110
120
80
90
ENCODE = 40 MSPS
f1 IN = 9.5 MHz @ 7 dBFS
f2 IN = 9.9 MHz @ 7 dBFS
2f1f2 = 65.4 dBc
2f2f1 = 65.0 dBc
Figure 8. Two-Tone IMD
0.50
0.25
0.50
0.00
0.25
DIFF PHASE Degrees
0.50
0.25
0.50
0.00
0.25
DIFF GAIN %
1
2
3
4
5
6
1
2
3
4
5
6
Figure 9. Differential Gain/Differential Phase
CLOCK RATE MSPS
350
290
260
0
10
DISSIPATION mW
20
30
40
50
60
340
300
280
270
330
310
250
320
5V
3V
Figure 4. Power Dissipation vs. Clock Rate
1
10
100
80
74
68
62
56
50
44
38
dB
ANALOG INPUT FREQUENCY MHz
HD 40
SNR 40
HD 60
SNR 60
Figure 5. SNR/Distortion vs. Frequency
CLOCK RATE MSPS
58
50
0
SNR dB
10
20
30
40
60
56
48
46
54
52
50
SNR
Figure 6. SNR vs. Clock Rate
AD9050
7
REV. B
FREQUENCY MHz
0
20
2.5
5
7.5
10
12.5
15
17.5
0
10
dB
50
60
70
30
40
20
100
110
120
80
90
ENCODE = 40 MSPS
ANALOG IN = 2.3 MHz
SNR = 55.1 dB
SNR (W/O HAR) = 55.5 dB
2ND HARMONIC = 69.3 dB
3RD HARMONIC = 72.9 dB
Figure 10. FFT Plot 40 MSPS, 2.3 MHz
FREQUENCY MHz
0
20
5
10
15
0
10
dB
50
60
70
30
40
20
100
80
90
ENCODE = 60 MSPS
ANALOG IN = 10.3 MHz
SNR = 55.8 dB
SNR (W/O HAR) = 56.2 dB
2ND HARMONIC = 67.2 dB
3RD HARMONIC = 73.2 dB
25
30
Figure 11. FFT Plot 60 MSPS, 10.3 MHz
FREQUENCY MHz
0
20
2.5
5
7.5
10
12.5
15
17.5
0
10
dB
50
60
70
30
40
20
100
110
120
80
90
ENCODE = 40 MSPS
ANALOG IN = 10.3 MHz
SNR = 54.6 dB
SNR (W/O HAR) = 55.2 dB
2ND HARMONIC = 66.4 dB
3RD HARMONIC = 70.5 dB
Figure 12. FFT Plot 40 MSPS, 10.3 MHz
DUTY CYCLE %
60
42
25
45
40
50
55
36
54
48
A
IN
= 10.3 MHz
30
60
65
SIGNAL-TO-NOISE dB
(SINAD)
SINAD_60
SINAD_40
Figure 13. SNR vs. Clock Pulse Width
1
10
100
1.0
0.5
0.5
1.0
2.0
3.0
3.5
4.0
ADC GAIN dB
ANALOG INPUT FREQUENCY MHz
1000
0.0
1.5
2.5
4.5
Figure 14. ADC Gain vs. AIN Frequency
TEMPERATURE
C
15.0
10.0
40
20
t
PD
ns
0
20
40
60
80
14.0
11.0
9.0
8.0
13.0
12.0
[1] - 5V DATA RISING EDGE
[2] - 5V DATA FALLING EDGE
[3] - 3V DATA RISING EDGE
[4] - 3V DATA FALLING EDGE
7.0
6.0
5.0
100
[3]
[1]
[4]
[2]
Figure 15. t
PD
vs. Temperature 3 V/5 V
AD9050
8
REV. B
THEORY OF OPERATION
Refer to the block diagram on the front page.
The AD9050 employs a subranging architecture with digital
error correction. This combination of design techniques en-
sures true 10-bit accuracy at the digital outputs of the converter.
At the input, the analog signal is buffered by a high speed differ-
ential buffer and applied to a track-and-hold (T/H) that holds
the analog value present when the unit is strobed with an
ENCODE command. The conversion process begins on the
rising edge of this pulse. The two stage architecture completes a
coarse and then a fine conversion of the T/H output signal.
Error correction and decode logic correct and align data from
the two conversions and present the result as a 10-bit parallel
digital word. Output data are strobed on the rising edge of the
ENCODE command. The subranging architecture results in
five pipeline delays for the output data. Refer to the AD9050
Timing Diagram.
USING THE AD9050
3 V System
The digital input and outputs of the AD9050 can be easily
configured to directly interface to 3 V logic systems. The en-
code input (Pin 13) is TTL compatible with a logic threshold of
1.5 V. This input is actually a CMOS stage (refer to Equivalent
Encode Input Stage) with a TTL threshold, allowing operation
with TTL, CMOS and 3 V CMOS logic families. Using 3 V
CMOS logic allows the user to drive the encode directly without
the need to translate to +5 V. This saves the user power and
board space. As with all high speed data converters, the clock
signal must be clean and jitter free to prevent the degradation of
dynamic performance.
The AD9050 outputs can also directly interface to 3 V logic
systems. The digital outputs are standard CMOS stages (refer
to AD9050 Output Stage) with isolated supply pins (Pins 20, 22
V
DD
). By varying the voltage on the V
DD
pins, the digital output
levels vary respectively. By connecting Pins 20 and 22 to the
3 V logic supply, the AD9050 will supply 3 V output levels.
Care should be taken to filter and isolate the output supply of
the AD9050 as noise could be coupled into the ADC, limiting
performance.
Analog Input
The analog input of the AD9050 is a differential input buffer
(refer to AD9050 Equivalent Analog Input). The differential
inputs are internally biased at +3.3 V, obviating the need for
external biasing. Excellent performance is achieved whether the
analog inputs are driven single-ended or differential (for best
dynamic performance, impedances at AIN and AINB should
match).
Figure 16 shows typical connections for the analog inputs when
using the AD9050 in a dc coupled system with single ended
signals. All components are powered from a single +5 V supply.
The AD820 is used to offset the ground referenced input signal
to the level required by the AD9050.
AC coupling of the analog inputs of the AD9050 is easily ac-
complished. Figure 17 shows capacitive coupling of a single
ended signal while Figure 18 shows transformer coupling differ-
entially into the AD9050.
+5V
AD8041
1k
1k
+5V
AD9050
9
10
+5V
1k
AD820
V
IN
0.5V to +0.5V
1k
0.1F
0.1F
Figure 16. Single Supply, Single Ended, DC Coupled
AD9050
+5V
AD8011
1k
1k
+5V
AD9050
9
10
5V
V
IN
0.5V to +0.5V
0.1F
0.1F
Figure 17. Single Ended, Capacitively Coupled AD9050
+5V
AD8011
1k
1k
+5V
9
10
5V
V
IN
0.5V to +0.5V
0.1F
AD9050
T1-1T
50
Figure 18. Differentially Driven AD9050 Using Trans-
former Coupling
The AD830 provides a unique method of providing dc level shift
for the analog input. Using the AD830 allows a great deal of
flexibility for adjusting offset and gain. Figure 19 shows the
AD830 configured to drive the AD9050. The offset is provided
by the internal biasing of the AD9050 differential input (Pin 9).
For more information regarding the AD830, see the AD830
data sheet.
V
I N
0.5V to +0.5V
1
2
3
4
AD830
+15V
5V
7
10
9
0.1
F
+5V
AD9050
Figure 19. Level Shifting with the AD830
AD9050
9
REV. B
Overdrive of the Analog Input
Special care was taken in the design of the analog input section
of the AD9050 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is +2.788 V to
3.812 V (1.024 V p-p centered at 3.3 V). Out-of-range com-
parators detect when the analog input signal is out of this range
and shut the T/H off. The digital outputs are locked at their
maximum or minimum value (i.e., all "0" or all "1"). This pre-
cludes the digital outputs from changing to an invalid value
when the analog input is out of range.
When the analog input signal returns to the nominal range, the
out-of-range comparators switch the T/H back to the active
mode and the device recovers in approximately 10 ns.
The input is protected to one volt outside the power supply
rails. For nominal power (+5 V and ground), the analog input
will not be damaged with signals from +6.0 V to 1.0 V.
Timing
The performance of the AD9050 is very insensitive to the duty
cycle of the clock. Pulse width variations of as much as
10%
will cause no degradation in performance. (see Figure 13, SNR
vs. Clock Pulse Width).
The AD9050 provides latched data outputs, with five pipeline
delays. Data outputs are available one propagation delay (t
PD
)
after the rising edge of the encode command (refer to the
AD9050 Timing Diagram). The length of the output data lines
and loads placed on them should be minimized to reduce tran-
sients within the AD9050; these transients can detract from the
converter's dynamic performance.
The minimum guaranteed conversion rate of the AD9050 is
3 MSPS. Below a nominal of 1.5 MSPS the internal T/H
switches to a track function only. This precludes the T/H from
drooping to the rail during the conversion process and mini-
mizes saturation issues. At clock rates below 3 MSPS dynamic
performance degrades. The AD9050 will operate in burst mode
operation, but the user must flush the internal pipeline each
time the clock stops. This requires five clock pulses each time
the clock is restarted for the first valid data output (refer to Fig-
ure 2 Timing Diagram).
Power Dissipation
The power dissipation specification in the parameter table is
measured under the following conditions: encode is 40 MSPS
or 60 MSPS, analog input is 0.5 dBFS at 10.3 MHz, the digi-
tal outputs are loaded with approximately 7 pF (10 pF maxi-
mum) and V
DD
is 5 V. These conditions intend to reflect actual
usage of the device.
As shown in Figure 4, the actual power dissipation varies based
on these conditions. For instance, reducing the clock rate will
reduce power as expected for CMOS-type devices. Also the
loading determines the power dissipated in the output stages.
From an ac standpoint, the capacitive loading will be the key
(refer to Equivalent Output Stage).
The analog input frequency and amplitude in conjunction with
the clock rate determine the switching rate of the output data
bits. Power dissipation increases as more data bits switch at
faster rates. For instance, if the input is a dc signal that is out of
range, no output bits will switch. This minimizes power in the
output stages, but is not realistic from a usage standpoint.
The dissipation in the output stages can be minimized by inter-
facing the outputs to 3 V logic (refer to USING THE AD9050,
3 V System). The lower output swings minimize consumption.
Refer to Figure 4 for performance characteristics.
Voltage Reference
A stable and accurate +2.5 V voltage reference is built into the
AD9050 (Pin 3, V
REF
Output). In normal operation the internal
reference is used by strapping Pins 3 and 4 of the AD9050 to-
gether. The internal reference has 500
A of extra drive current
that can be used for other circuits.
Some applications may require greater accuracy, improved tem-
perature performance, or adjustment of the gain of the AD9050,
which cannot be obtained by using the internal reference. For
these applications, an external +2.5 V reference can be used to
connect to Pin 4 of the AD9050. The VREF
IN
requires 5
A of
drive current.
The input range can be adjusted by varying the reference volt-
age applied to the AD9050. No appreciable degradation in per-
formance occurs when the reference is adjusted
5%. The
full-scale range of the ADC tracks reference voltage changes
linearly.
AD9050
10
REV. B
Figure 20. Evaluation Board Top Layer
Figure 21. Evaluation Board Ground Layer
Figure 22. Evaluation Board Bottom Layer
Figure 23. Silkscreen
AD9050
11
REV. B
Figure 24. Evaluation Board Schematic
J2
IN
IN OUT
R4
1k
R3
50
2
3
6
R5
1k
U2
AD9631Q
TP3
C9
0.1
F
8D
7D
6D
5D
4D
3D
2D
1D
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
CK
OE
U3
74AC574R
VREF
OUT
VREF
IN
COMP
REF
BP
AINB
AIN
ENC
OR
D9/MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
+5V
+5V
U1
AD9050R
J3
HDR20
TP1
3
4
5
6
10
13
14
9
U6:B
74AC00R
4
5
6
R1
50
C1
0.1
F
C2
0.1
F
C3
0.1
F
9
8
7
6
5
4
3
2
8D
7D
6D
5D
4D
3D
2D
1D
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
CK
OE
U4
74AC574R
9
8
7
6
5
4
3
2
TP2
E1
+5V
11
1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
12
13
14
15
16
17
18
19
11
1
+5V
12
13
14
15
16
17
18
19
15
16
17
18
19
24
25
26
27
28
20
22
U6:A
74AC00R
U6:C
74AC00R
3
8
OUT
GND
VCC
Y1
SW41
3
2
4
R2
2k
1
2
9
10
+5V
+5V
12
13
11
U6:D
74AC00R
J6
C5
10
F
C7
0.1
F
+5V
J1
+
C6
10
F
C8
0.1
F
5.2V
J5
+
+5V
C10
0.1
F
C12
0.1
F
C13
0.1
F
C14
0.1
F
C15
0.1
F
C16
0.1
F
C17
0.1
F
C22
0.1
F
C23
0.1
F
C24
0.1
F
5.2V
C20
0.1
F
J7
+5V
AD9050
12
REV. B
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SOIC
(R-28)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
x 45
0.7125 (18.10)
0.6969 (17.70)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
28
15
14
1
28-Lead SSOP
(RS-28)
28
15
14
1
0.407 (10.34)
0.397 (10.08)
0.311 (7.9)
0.301 (7.64)
0.212 (5.38)
0.205 (5.21)
PIN 1
SEATING
PLANE
0.008 (0.203)
0.002 (0.050)
0.07 (1.79)
0.066 (1.67)
0.0256
(0.65)
BSC
0.078 (1.98)
0.068 (1.73)
0.015 (0.38)
0.010 (0.25)
0.009 (0.229)
0.005 (0.127)
0.03 (0.762)
0.022 (0.558)
8
0
C2048b23/97
PRINTED IN U.S.A.
PDF 
ZIP