REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD9071
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
10-Bit, 100 MSPS
A/D Converter
FUNCTIONAL BLOCK DIAGRAM
T/H
DAC
ADC
VREF
IN
V
CC
2.5V
VREF
OUT
ADC
SUM
AMP
TIMING
AIN
ENCODE
AIN
AD9071
ENCODE
LOGIC
10
V
CC
GND
V
DD
D0D9
OR
FEATURES
10-Bit, 100 MSPS ADC
Low Power: 450 mW at 100 MSPS
On-Chip Track/Hold
280 MHz Analog Bandwidth
SINAD = 54 dB @ 41 MHz
On-Chip Reference
1 V p-p Analog Input Range
Single +5 V Supply Operation
+5 V/+3.3 V Outputs
APPLICATIONS
Digital Communications
Signal Intelligence
Digital Oscilloscopes
Spectrum Analyzers
Medical Imaging
Sonar
HDTV
GENERAL DESCRIPTION
The AD9071 is a monolithic sampling analog-to-digital con-
verter with an on-chip track-and-hold circuit and TTL/CMOS
digital interfaces. The product operates at a 100 MSPS conver-
sion rate with outstanding dynamic performance over its full
operating range.
The ADC requires only a single 5 V supply and an encode clock
for full performance operation. The digital outputs are TTL
compatible. Separate output power supply pins support
interfacing with 3.3 V or 5 V logic. An out-of-range output
(OR) is available that indicates a conversion result is outside the
operating range. The output data are held at saturation levels
during an out-of-range condition.
The input amplifier supports differential or single-ended inter-
faces. An internal reference is included.
Fabricated on an advanced BiCMOS process, the AD9071 is
available in a plastic SOIC package specified over the industrial
temperature range (40
C to +85
C).
2
REV. B
AD9071SPECIFICATIONS
(V
CC
= +5 V, V
DD
= +3.3 V, Differential Analog Input, ENCODE = 100 MSPS unless
otherwise noted)
Test
AD9071BR
Parameter
Temp
Level
Min
Typ
Max
Units
RESOLUTION
10
Bits
DC ACCURACY
Differential Nonlinearity
1
+25
C
I
0.8
+1.5/1.0
LSB
Full
VI
1.0
+1.75/1.0
LSB
Integral Nonlinearity
1
+25
C
I
0.8
1.5
LSB
Full
VI
1.25
1.75
LSB
No Missing Codes
1
+25
C
I
Guaranteed
Gain Error
2
+25
C
I
1
4
% FS
Full
VI
2
8
% FS
Gain Tempco
2
Full
V
150
ppm/
C
ANALOG INPUT
Input Voltage Range
(With Respect to
AIN)
Full
V
512
mV p-p
Common-Mode Voltage
Full
V
2.5
0.2
V
Input Offset Voltage
+25
C
I
4
18
mV
Full
VI
5
20
mV
Input Resistance
Full
VI
15
35
k
Input Capacitance
+25
C
V
3
pF
Input Bias Current
+25
C
I
55
90
A
Full
VI
65
115
A
Analog Bandwidth, Full Power
+25
C
V
280
MHz
REFERENCE OUTPUT
Output Voltage
Full
VI
V
CC
2.6
V
CC
2.5
V
CC
2.4
V
Temperature Coefficient
Full
V
130
ppm/
C
SWITCHING PERFORMANCE
Maximum Conversion Rate
Full
VI
100
MSPS
Minimum Conversion Rate
Full
IV
40
MSPS
Encode Pulsewidth High (t
EH
)
+25
C
IV
4.5
13
ns
Encode Pulsewidth Low (t
EL
)
+25
C
IV
4.5
13
ns
Aperture Delay (t
A
)
+25
C
V
1.1
ns
Aperture Uncertainty (Jitter)
+25
C
V
3.0
ps, rms
Output Valid Time (t
V
)
3
Full
VI
2.0
4.0
ns
Output Propagation Delay (t
PD
)
3
Full
VI
5.0
7.0
ns
Output Rise Time (t
R
)
Full
V
1.4
ns
Output Fall Time (t
F
)
Full
V
1.0
ns
DIGITAL INPUT
Logic "1" Voltage
Full
VI
2.0
V
Logic "0" Voltage
Full
VI
0.8
V
Logic "1" Current
Full
VI
10
A
Logic "0" Current
Full
VI
500
A
Input Capacitance
+25
C
V
3
pF
DIGITAL OUTPUTS
Logic "1" Voltage
Full
VI
V
DD
0.5
V
Logic "0" Voltage
Full
VI
0.05
V
Output Coding
Offset Binary
POWER SUPPLY
V
CC
Supply Current
(V
CC
= 5 V)
4
Full
VI
85
115
mA
V
DD
Supply Current (V
DD
= 3.3 V)
4
Full
VI
7.5
14
mA
Power Dissipation
4
Full
VI
450
620
mW
Power Supply Sensitivity
5
+25
C
I
0.002
0.010
V/V
3
REV. B
AD9071
Test
AD9071BR
Parameter
Temp
Level
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
6
Transient Response
+25
C
V
4
ns
Overvoltage Recovery Time
+25
C
V
5
ns
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
f
IN
= 10.3 MHz
+25
C
I
54
56
dB
Full
V
55
dB
f
IN
= 41 MHz
+25
C
I
53
55
dB
Full
V
54
dB
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
f
IN
= 10.3 MHz
+25
C
I
54
56
dB
Full
V
55
dB
f
IN
= 41 MHz
+25
C
I
52
54
dB
Full
V
53
dB
Effective Number of Bits
f
IN
= 10.3 MHz
+25
C
I
8.8
9.2
Bits
f
IN
= 41 MHz
+25
C
I
8.5
8.8
Bits
2nd Harmonic Distortion
f
IN
= 10.3 MHz
+25
C
I
63
75
dBc
f
IN
= 41 MHz
+25
C
I
60
66
dBc
3rd Harmonic Distortion
f
IN
= 10.3 MHz
+25
C
I
65
75
dBc
f
IN
= 41 MHz
+25
C
I
57
65
dBc
Two-Tone Intermodulation (IMD)
f
IN
= 10.3 MHz
+25
C
V
70
dBc
f
IN
= 41 MHz
+25
C
V
60
dBc
NOTES
1
Differential and integral nonlinearity based on F
S
= 80 MSPS.
2
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference).
3
t
V
and t
PD
are measured from the threshold crossing of the ENCODE input to the 50% levels of the digital outputs. The output ac load during test is 5 pF.
4
Power dissipation is measured under the following conditions: F
S
@ 100 MSPS, analog input is 1 dBFS at 10.3 MHz.
5
A change in input offset voltage with respect to a change in V
CC
.
6
SNR/harmonics based on an analog input voltage of 1.0 dBFS referenced to a 1.024 V full-scale input range.
Typical thermal impedance for the R style (SOIC) 28-lead package:
JC
= 23
C/W,
CA
= 48
C/W,
JA
= 71
C/W.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
to 0.0 V
VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . . V
CC
to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Operating Temperature . . . . . . . . . . . . . . . . . 40
C to +85
C
Storage Temperature . . . . . . . . . . . . . . . . . . 65
C to +150
C
Maximum Junction Temperature . . . . . . . . . . . . . . . . +175
C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . +150
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
EXPLANATION OF TEST LEVELS
Test Level
I.
100% production tested.
II.
100% production tested at +25
C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V.
Parameter is a typical value only.
VI. 100% production tested at +25
C; guaranteed by design
and characterization testing for industrial temperature range.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9071 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD9071
4
REV. B
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9071BR
40
C to +85
C
28-Lead Wide Body (SOIC)
R-28
AD9071/PCB
+25
C
Evaluation Board
Table I. Output Coding
Offset
Code
AIN
AIN
Binary
OR
1023
0.512 V
11 1111 1111
1
1023
0.511 V
11 1111 1111
0
1022
0.510 V
11 1111 1110
0
513
0.001 V
10 0000 0001
0
512
0.000 V
10 0000 0000
0
511
0.001 V
01 1111 1111
0
1
0.511 V
00 0000 0001
0
0
0.512 V
00 0000 0000
0
0
0.513 V
00 0000 0000
1
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Function
1, 7, 12, 21, 23
GND
Ground.
2, 8, 11
V
CC
Analog Power Supply. Nominally 5.0 V. (Tie together to prevent a possible latch-up condition.)
3
VREF OUT
Internal Reference Output (V
CC
2.5 V typical); Bypass with 0.1
F to V
CC
.
4
VREF IN
Reference Input for ADC (V
CC
2.5 V typical).
5, 6
DNC
Do Not Connect.
9
AIN
Analog Input Complementary.
10
AIN
Analog Input True.
13
ENCODE
Encode clock for ADC. (ADC Samples on Rising Edge of ENCODE.)
14
OR
Out-of-Range Output. Goes HIGH when the converted sample is more positive than
3FF
H
or more negative than 000
H
(offset binary coding).
1519, 2428
D9D0
Digital outputs of ADC. D9 is the MSB. Data is offset binary.
20, 22
V
DD
Digital Output Power Supply. User selectable range from 3 V to 5 V.
PIN CONFIGURATION
14
13
12
11
10
9
8
2
3
4
7
6
5
1
TOP VIEW
(Not to Scale)
17
16
15
20
19
18
28
27
26
25
24
23
22
21
AD9071BR
D0
D1
D2
D3
D4
V
DD
GND
V
DD
GND
D5
D6
D7
D8
D9 (MSB)
V
CC
GND
VREF OUT
VREF IN
DNC
DNC
V
CC
GND
AIN
AIN
GND
V
CC
ENCODE
OR
DNC = DO NOT CONNECT
AD9071
5
REV. B
SAMPLE N1
t
EH
t
EL
1/f
s
t
A
t
PD
t
V
SAMPLE N
SAMPLE N+3
SAMPLE N+4
SAMPLE N+2
SAMPLE N+1
DATA N4
DATA N3
DATA N2
DATA N1
DATA N
DATA N+1
AIN
ENCODE
D9D0
Figure 1. Timing Diagram
AIN
AIN
V
CC
Figure 2. Equivalent Analog Input Circuit
VREF IN
V
CC
Figure 3. Equivalent Reference Input Circuit
ENCODE
V
CC
Figure 4. Equivalent Encode Input Circuit
D
90
, OR
V
DD
Figure 5. Equivalent Digital Output Circuit
VREF
OUT
V
CC
Figure 6. Equivalent Reference Output Circuit
AD9071
6
REV. B
Typical Performance Characteristics
MHz
0
60
100
0
50
dB
10
50
70
90
30
40
80
20
FUNDAMENTAL = 1.0dBFS
SNR = 56.75dB
SINAD = 56.56dB
2ND HARMONIC = 71.88dB
3RD HARMONIC = 77.28dB
Figure 7. Spectrum: F
S
= 100 MSPS, f
IN
= 10.3 MHz
MHz
0
60
100
0
50
dB
10
50
70
90
30
40
80
20
FUNDAMENTAL = 1.0dBFS
SNR = 55.23dB
SINAD = 54.35dB
2ND HARMONIC = 68.28dB
3RD HARMONIC = 62.83dB
Figure 8. Spectrum: F
S
= 100 MSPS, f
IN
= 41 MHz
MHz
0
60
100
0
50
dB
10
50
70
90
30
40
80
20
F1 = 9.63MHz
F2 = 10.63MHz
F1 = F2 = 7.0dBFS
Figure 9. Two-Tone Intermodulation Distortion
MHz
0
60
100
0
50
dB
10
50
70
90
30
40
80
20
F1 = 41.1MHz
F2 = 42.1MHz
F1 = F2 = 7.0dBFS
Figure 10. Two-Tone Intermodulation Distortion
f
IN
MHz
60
40
10
100
20
dB
40
60
80
58
50
46
44
42
56
54
48
52
120
140
SNR
SINAD
Figure 11. SINAD/SNR vs. f
IN
: F
S
= 100 MSPS
58
10
120
dB
40
60
80
57
50
56
55
48
51
49
52
53
54
20
100
140
SNR
SINAD
F
S
MSPS
Figure 12. SINAD/SNR vs. F
S
: f
IN
= 10.3 MHz
AD9071
7
REV. B
T
C
40
40
85
dB
15
5
25
55
SINAD
SNR
55
45
50
60
Figure 13. Differential SNR vs. T
C
: f
IN
= 10.3 MHz
T
C
60
50
40
85
dB
15
5
25
52
48
58
SINAD
SNR
55
40
42
44
46
54
56
Figure 14. Single-Ended SNR vs. T
C
: f
IN
= 10.3 MHz
ENCODE PULSEWIDTH ns
60
50
2.5
7.5
dB
3.5
4.5
5.5
56
54
58
SINAD
SNR
6.5
52
40
46
44
48
42
Figure 15. SNR vs. Clock Pulsewidth (t
EH
): f
IN
= 10.3 MHz
f
IN
MHz
2
15
dB
0
1
7
4
5
3
6
60
105
3dB ROLLOFF POINT
150
195
240
285
330
375
420
Figure 16. Frequency Response
f
IN
MHz
70
dBc
90
80
20
50
40
60
30
10
20
30
40
SINGLE-ENDED
10
0
DIFFERENTIAL INPUT
Figure 17. Second Harmonic Performance: Single-
Ended vs. Differential Input
AD9071
8
REV. B
APPLICATION NOTES
THEORY OF OPERATION
The AD9071 employs a two-step subranging architecture with
digital error correction.
The sampling and conversion process is initiated by a rising edge
at the ENCODE input. The analog input signal is buffered by a
high speed differential amplifier and applied to a track-and-hold
(T/H) circuit, which captures the value of the input at the sam-
pling instant and maintains it for the duration of the conversion.
The coarse quantizer (ADC) produces a 5-bit estimate of the
input value. Its digital output is reconverted to analog form by
the reconstruction DAC and subtracted from the input signal in
the SUM AMP. The second stage quantizer generates a 6-bit
representation of the difference signal. The eleven bits are pre-
sented to the ENCODE LOGIC, which corrects for range over-
lap errors and produces an accurate 10-bit result.
Data are strobed to the output on the rising edge of the ENCODE
input, with the data from sample N appearing on the output
following ENCODE rising edge N+3.
USING THE AD9071
ENCODE Input
Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A track/hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at
the A/D output. For that reason, considerable care has been
taken in the design of the ENCODE input of the AD9071, and
the user is advised to give commensurate thought to the clock
source. The lowest jitter clock source is a crystal oscillator pro-
ducing a pure sine wave.
The ENCODE input is fully TTL/CMOS compatible.
Digital Outputs
The digital outputs are CMOS compatible for lower power
consumption. 200
series resistors are recommended between
the AD9071 and the receiving logic to reduce transients and
improve SNR.
Analog Input
The analog input has been optimized for differential signal
input.
AD9071
T1A
T1 - 1T
50
V
REF
(+2.5V)
0.1 F
0.1 F
100
100
AIN
AIN
Figure 18. Differential Analog Input Configuration
If driven single-endedly, the
AIN should be connected to a
clean reference and bypassed to ground. For best dynamic
performance, impedances at AIN and
AIN should match.
Special care was taken in the design of the analog input section
of the AD9071 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is +1.988 V to
+3.012 V (1.024 V p-p centered at +2.5 V). Out-of-range
comparators detect when the analog input signal is out of this
range, and set the OR output signal HIGH. The digital outputs
are locked at plus or minus full scale (3FF
H
or 200
H
) for volt-
ages that are out of range, but between 1 V and 5 V. Input volt-
ages outside of this range may result in invalid codes at the
ADC's output.
25
AD9071
50
V
REF
(+2.5V)
0.1 F
0.1 F
100
100
AIN
AIN
Figure 19. Single-Ended Analog Input Configuration
When the analog input signal returns to the nominal range, the
out-of-range comparators return the ADC to its active mode
and the device recovers in the overvoltage recovery time.
Voltage Reference
A stable and accurate 2.5 V voltage reference (V
CC
2.5 V) is
built into the AD9071 (VREF OUT). In normal operation, the
internal reference is used by strapping Pins 3 and 4 of the AD9071
together. The internal reference can provide 100
A of extra
drive current that may be used for other circuits.
Some applications may require greater accuracy, improved
temperature performance, or adjustment of the gain of the
AD9071, which cannot be obtained by using the internal refer-
ence. For these applications, an external 2.5 V reference can be
connected to VREF IN, which requires 5
A of drive current
(see Figure 20).
AD9071
V
REF
IN
0.1 F
AD780
V
OUT
+V
IN
GND
1 F
+5V
TRIM
+5V
25k
1M
O/P SELECT
NC
NC = NO CONNECT
Figure 20. Using the AD780 Voltage Reference
The input range can be adjusted by varying the reference volt-
age applied to the AD9071. No appreciable degradation in
performance occurs when the reference is adjusted
4%. The
full-scale range of the ADC tracks reference voltage changes
linearly.
Timing
The performance of the AD9071 is insensitive to the duty
cycle of the clock over a wide range of operating conditions
(see Figure 15).
The AD9071 provides latched data outputs, with three pipeline
delays. Data outputs are available one propagation delay (t
PD
)
after the rising edge of the encode command (see Figure 1). The
length of the output data lines, and loads placed on them, should
be minimized to reduce transients within the AD9071; these
transients can detract from the converter's dynamic performance.
AD9071
9
REV. B
The minimum guaranteed conversion rate of the AD9071 is
40 MSPS. At clock rates below 40 MSPS, dynamic performance
may degrade. The AD9070 will operate in bursts, but the user
must flush the internal pipeline each time the clock restarts.
Valid data will be produced on the fourth rising edge of the
ENCODE signal after the clock is restarted.
EVALUATION BOARD
The AD9071 evaluation board is a convenient and easy way to
evaluate the performance of the AD9071 in the SOIC package.
The board consists of an internal voltage reference or an op-
tional external reference, two 74LCX574 latches for capturing
data from the A/D converter, and an AD9760 DAC for viewing
reconstructed A/D data. The AD9071 output logic can be driven
at 5 V and 3.3 V levels. The latches are set up at 3.3 V but are
5 V tolerant. Test points are provided at Encode, DB9, DB0,
Data Ready, and Data Clock. All are clearly labeled.
Analog Input
The evaluation board can be driven single-ended or differen-
tially. Differential input requires using a 1:1 transformer. For
single-ended operation (J2), Jumper S5 is connected to S8 and
S6 is connected to S7. For differential input operation (J3), S5
is connected to S3 and S4 is connected to S6. The board is
shipped in the differential configuration.
Encode
The AD9071 encode inputs are driven single-ended into J1 and
are at TTL logic levels.
Data Out
The data delivered out of the AD9071 is in offset binary format
at TTL levels. The Data Ready signal can be inverted by open-
ing the S1 and S2 connections. An optional series termination
resistor on Data Ready (R33), normally 0 ohms, is provided to
support various user output impedance configurations. The
AD9760 DAC supports viewing reconstructed A/D data at J4.
Voltage Reference
The AD9071 can be operated using its internal voltage refer-
ence (connect E2 to E3) or an optional external reference (con-
nect E1 to E2). The board is shipped utilizing the internal
voltage reference.
Layout
The AD9071 is not layout sensitive if some important guidelines
are met. The evaluation board layout provides an example where
these guidelines have been followed to optimize performance.
Provide a good ground plane connecting the analog and
digital sections.
Excellent bypassing is essential. Chip capacitors with 0.1
F
values and 0803 dimensions are placed flush against the pins.
Placing any of the capacitors on the bottom of the board can
degrade performance. These techniques reduce the amount
of parasitic inductance that can impact the bypassing ability
of the caps.
Separate power planes and supplies for the analog and digital
sections are recommended.
The AD9071 evaluation board is provided as a design example
for customers of Analog Devices. ADI makes no warranties
express, statutory, or implied regarding merchantability or fit-
ness for a particular purpose.
Figure 21. Printed Circuit Board Top Side Silkscreen
Figure 22. Printed Circuit Board Bottom Side Silkscreen
AD9071
10
REV. B
Figure 23. Printed Circuit Board Top Side Copper
Figure 24. Printed Circuit Board Ground Layer
Figure 25. Printed Circuit Board "Split" Power Layer
Figure 26. Printed Circuit Board Bottom Side Copper
AD9071
11
REV. B
12
13
11
C20
10
F
VREF EXT
+VD
V
DD
V
CC
GND
2
1
3
4
5
6
TB1
TB6
C21
10
F
C11
0.1
F
C12
0.1
F
V
DD
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SLEEP
REFLO
REFIO
FSADJ
COMP1
COMP2
AVDD
DVDD
IOUTA
IOUTB
AD9760
CLK
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
VREF IN
DNC
DNC
AIN
AIN
3
5
6
9
10
28
OR
R27
100
DATABIT 0
ENCODE
13
J3
1
1
C1
0.1
F
C17
0.1
F
C6
0.1
F
C18
10
F
V
CC
+VD
C15
0.1
F
C17
0.1
F
C8
0.1
F
C19
10
F
C2
0.1
F
C3
0.1
F
VREF OUT
27
26
25
24
19
18
17
16
15
14
4
1
J2
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
19
DB0
DB1
DB2
DB3
DB4
OUT EN
D0
D1
D2
D3
D4
D5
D6
D7
R13 200
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLOCK
1
2
11
12
13
14
15
16
17
18
19
OUT EN
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLOCK
GND : 10
+VD : 20
U2
74LCX574
3
4
5
6
7
8
9
DB5
DB6
DB7
DB8
R12 200
R11
200
R10 200
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
R14
200
R9
200
R15
200
R16 200
R17
200
R18
200
R3
200
15
16
17
18
19
23
24
27
DATABIT 1
DATABIT 2
DATABIT 3
DATABIT 4
DATABIT
5
DATABIT
6
DATABIT 7
DATABIT 8
DATABIT 9
OVERRANGE
4
5
6
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB9
OR
R34
150
+VD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
OR
R35
150
J4
R8
50
2, 3, 4,
5, - GND
SNS
DAC OUT
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
J5
DATABIT 0
DATABIT 1
DATABIT 2
DATABIT 3
DATABIT 4
DATABIT 5
DATABIT 6
DATABIT 7
DATABIT 8
DATABIT 9
OVERRANGE
DATA READY
GND
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
GND
R37
150
R36
150
R33
0
DATA READY
+VD
C14
0.1
F
C10
0.1
F
R2 2k
S13
S11
S12
C9
0.1
F
+VD
+VD
R7
50
28
+VD
1
2
3
9
10
8
S2
TP4
TP5
DATA READY
C4
0.1
F
R3
1
4.99k
S1
SMB
2, 3, 4,
5 - GND
R6
50
ENCODE IN
U5
74LCX86
ENCODE
TP1
V
CC
: 2, 8, 11
V
DD
: 20, 22
GND : 1, 7 12, 21, 23
TP2
R32
25
S7
S6
S4
R19 100
R1
100
S1
0
S9
3
2
1
4
6
T1
T1
1T
ANALOG IN
ANALOG IN
S5
S3
S8
C7
0.1
F
A IN
SMB
2, 3, 4,
5 - GND
SMB
2, 3, 4,
5 - GND
A IN DIF
C5
0.1
F
E1
E2
E3
VREF EXT
VREF INT
V
CC
C13
0.1
F
U3
AD9071
GND : 10
+VD : 20
U1
74LCX574
R26
100
R25
100
R24
100
R23
100
R22
100
R21
100
R20
100
R29
100
R28
100
R30
100
+ VD : 14
GND : 7
TP3
C22
0.1
F
GND
R5 50
R4 50
VREF
DATA CLK
1
0
987
6
5
432
1
P2
C37DPPF
J1
Figure 27. Printed Circuit Board Schematic
12
AD9071
C3331b05/99
PRINTED IN U.S.A.
Table II. Printed Circuit Board Bill of Materials
Item #
Quantity
Reference
Description
1
18
C1, C2, C3, C4, C5, C6, C7, C8, C9, C10,
Ceramic Chip Capacitor, 0603, 0.1
F
C11, C12, C13, C14, C15, C16, C17, C22
2
4
C18, C19, C20, C21
Tantalum Chip Capacitor, 10
F
3
3
E1, E2, E3
Jumpers
4
4
J1, J2, J3, J4
SMB-P Connector
5
1
J5
20-Pin Male Header
6
1
P2
37-Pin Connector (Amp 747462-4)
7
13
R1, R19, R20, R21, R22, R23, R24, R25,
Surface Mount Resistor, 1206, 100
R26, R27, R28, R29, R30
8
1
R2
Surface Mount Resistor, 1206, 2000
9
11
R3, R9, R10, R11, R12, R13, R14, R15,
Surface Mount Resistor, 1206, 200
R16, R17, R18
10
5
R4, R5, R6, R7, R8
Surface Mount Resistor, 1206, 50
11
1
R31
Surface Mount Resistor, 1206, 5000
12
1
R32
Surface Mount Resistor, 1206, 25
13
1
R33
Surface Mount Resistor, 1206, 0
14
4
R34, R35, R36, R37
Surface Mount Resistor, 1206, 150
15
13
S1, S2, S3, S4, S5, S6, S7, S8, S9, S10,
Jumpers
S11, S12, S13
16
1
T1
Surface Mount Transformer Mini-Circuit T1-T1, 1:1 Ratio
17
1
TB1
6-Pin Wieland Connector (P/N # 25,602, 2653.0; 25.530
3625.0)
18
5
TP1, TP2, TP3, TP4, TP5
Test Points
19
2
U1, U2
74LCX574 Octal Latch
20
1
U3
AD9071BR, 10-Bit, 100 MSPS, ADC
21
1
U4
AD9760AR, 10-Bit, 125 MSPS, DAC
22
1
U5
74LCX86, XOR
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Wide Body SOIC
(R-28)
28
15
14
1
0.7125 (18.10)
0.6969 (17.70)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
45
REV. B
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