REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD9202

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

Complete 10-Bit, 32 MSPS, 90 mW

CMOS A/D Converter

FUNCTIONAL BLOCK DIAGRAM

A/D

AIN

REFTF

REFBF

REFSENSE

OTR

D9
(MSB)

D0
(LSB)

VREF

DRVDD

AVDD

CLK

DRVSS

AD9202

SHA

GAIN

SHA

GAIN

D/A

A/D

D/A

A/D

D/A

CORRECTION LOGIC

OUTPUT BUFFERS

REFTS

AVSS

REFBS

THREE-

STATE

MODE

STBY

CLAMP

SHA

GAIN

A/D

D/A

FEATURES
CMOS 10-Bit, 32 MSPS Sampling A/D Converter
Power Dissipation: 90 mW (3 V Supply)
Operation Between 2.7 V and 5.5 V Supply
Differential Nonlinearity: 0.5 LSB
Power-Down (Sleep) Mode
Three-State Outputs
Out-of-Range Indicator
Built-In Clamp Function (DC Restore)
Adjustable On-Chip Voltage Reference
IF Undersampling to 135 MHz
Pin-Compatible with the AD9200

PRODUCT DESCRIPTION

The AD9202 is a monolithic, single supply, 10-bit, 32 MSPS
analog-to-digital converter with an on-chip sample-and-hold
amplifier and voltage reference. The AD9202 uses a multistage
differential pipeline architecture at 32 MSPS data rates and
guarantees no missing codes over the full operating tempera-
ture range.

The input of the AD9202 has been designed to ease the devel-
opment of both imaging and communications systems. The
user can select a variety of input ranges and offsets and can
drive the input either single-ended or differentially.

The sample-and-hold (SHA) amplifier is equally suited for
both multiplexed systems that switch full-scale voltage levels in
successive channels and sampling single-channel inputs at
frequencies up to and beyond the Nyquist rate. AC coupled
input signals can be shifted to a predetermined level, with an
onboard clamp circuit. The dynamic performance is excellent.

The AD9202 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of the application.

A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal (OTR) indicates an over-
flow condition that can be used with the most significant bit to
determine low or high overflow.

The AD9202 can operate with supply range from 2.7 V to
5.5 V, ideally suiting it for low power operation in high speed
portable applications.

The AD9202 is specified over the commercial (0

C to +70

temperature range.

PRODUCT HIGHLIGHTS
Low Power

The AD9202 consumes 90 mW on a 3 V supply (excluding the
reference power). In sleep mode, power is reduced to below
5 mW.

Very Small Package

The AD9202 is available in a 28-lead SSOP package.

300 MHz Onboard Sample-and-Hold

The versatile SHA input can be configured for either single-
ended or differential inputs.

Out-of-Range Indicator

The OTR output bit indicates when the input signal is beyond
the input range of the AD9202.

Built-In Clamp Function

Allows dc restoration of video signals.

Pin Compatible with AD9200

The AD9202 allows "drop-in" upgrade for AD9200 users.

REV. C

AD9202SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Units

Conditions

RESOLUTION

Bits

CONVERSION RATE

MHz

DC ACCURACY

Differential Nonlinearity @ 32 MHz

DNL

0.5

LSB

REFTS = 2.5 V, REFBS = 0.5 V

@ 27 MHz

0.5

Integral Nonlinearity @ 32 MHz

INL

1.0

2.9

LSB

@ 27 MHz

0.5

Offset Error @ 32 MHz

0.8

2.3

% FSR

@ 27 MHz

0.5

Gain Error @ 32 MHz

0.5

2.1

% FSR

@ 27 MHz

0.5

REFERENCE VOLTAGES

Top Reference Voltage

REFTS

AVDD

Bottom Reference Voltage

REFBS

GND

AVDD-1

Differential Reference Voltage

V p-p

Reference Input Resistance

REFTS, REFBS: MODE = AVDD

4.2

Between REFTF & REFBF: MODE = AVSS

ANALOG INPUT

Input Voltage Range

AIN

REFBS

REFTS

REFBS Min = GND: REFTS Max = AVDD

Input Capacitance

Switched

Aperture Delay

Aperture Uncertainty (Jitter)

Full Power Bandwidth

FPBW

300

MHz

DC Leakage Current

Input =

INTERNAL REFERENCE

Output Voltage

(1 V Mode)

VREF

REFSENSE = VREF

Output Voltage Tolerance

(1 V Mode)

Output Voltage

(2 V Mode)

VREF

REFSENSE = GND

Load Regulation

(1 V Mode)

0.5

1.0

1 mA Load Current

POWER SUPPLY

Operating Voltage

AVDD

2.7

5.5

DRVDD

2.7

5.5

Supply Current

IAVDD

29.9

AVDD = 3 V, MODE = AVSS

Power Consumption

@ 32 MSPS

115

AVDD = DRVDD = 3 V, MODE = AVSS

@ 27 MSPS

Power-Down

3.5

STBY = AVDD, MODE = AVSS

Gain Error Power Supply Rejection

PSRR

0.3

% F

DIGITAL INPUTS

High Input Voltage

2.4

Low Input Voltage

0.3

DIGITAL OUTPUTS

High-Z Leakage

+10

Output = GND to VDD

Data Valid Delay

= 20 pF

Data Enable Delay

DEN

Data High-Z Delay

DHZ

(AVDD = +3 V, DRVDD = +3 V, F

= 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input

Span from 0.5 V to 2.5 V, External Reference, T

MIN

to T

MAX

unless otherwise noted)

REV. C

AD9202

Parameter

Symbol

Min

Typ

Max

Units

Conditions

LOGIC OUTPUT (with DRVDD = +3 V)

High Level Output Voltage (I

= 50

+2.95

High Level Output Voltage (I

= 0.5 mA)

+2.80

Low Level Output Voltage (I

= 1.6 mA)

+0.4

Low Level Output Voltage (I

= 50

+0.5

LOGIC OUTPUT (with DRVDD = +5 V)

High Level Output Voltage (I

= 50

+4.5

High Level Output Voltage (I

= 0.5 mA)

+2.4

Low Level Output Voltage (I

= 1.6 mA)

+0.4

Low Level Output Voltage (I

= 50

+0.5

CLOCKING

Clock Pulsewidth High

14.7

Clock Pulsewidth Low

14.7

Pipeline Latency

Cycles

CLAMP

Clamp Error Voltage

CLAMPIN = 0.5 V2.7 V, R

= 10

Clamp Pulsewidth

CPW

= 1

F (Period = 63.5

NOTES

See Figures 1a and 1b.

Specifications subject to change without notice.

AD9202

REFTS

REFBS

MODE

10k

0.4 V

AD9202

REFTS

REFBF

MODE

REFTF

REFBS

4.2k

Figure 1. REFT and REFB Equivalent Circuits

REV. C

AD9202SPECIFICATIONS

(AVDD = +3 V, DRVDD = +3 V, MODE = AVDD, 2 V Input Span from 0.5 V to 2.5 V,
External Reference, T

MIN

to T

MAX

unless otherwise noted)

Parameter

Symbol

Min

Typ

Max

Min

Typ

Max

Units

Conditions

CONVERSION RATE

MSPS

DYNAMIC PERFORMANCE
(AIN = 0.5 dBFS)

Signal-to-Noise and Distortion

SINAD

f = 3.58 MHz

53.7

55.7

f = 13.5 MHz

55.4

f = 16 MHz

54.3

Effective Bits

f = 3.58 MHz

9.3

8.6

9.0

Bits

f = 13.5 MHz

8.9

Bits

f = 16 MHz

8.7

Bits

Signal-to-Noise Ratio

SNR

f = 3.58 MHz

58.9

54.2

56.4

f = 13.5 MHz

58.8

f = 16 MHz

56.4

Total Harmonic Distortion

THD

f = 3.58 MHz

65.6

64.5 57.6

f = 13.5 MHz

55.8

f = 16 MHz

Spurious Free Dynamic Range

SFDR

f = 3.58 MHz

68.3

f = 10 MHz

f = 16 MHz

58.8

Two-Tone Intermodulation

Distortion

IMD

Differential Phase

0.1

Degree NTSC 40 IRE Mode Ramp

Differential Gain

0.05

NOTES

At F

= 27 MHz, f

= 69.5 MHz and 70.5 MHz; at F

= 32 MHz, f

= 44.5 MHz and 45.5 MHz; REFBS = 1 V, REFTS = 2 V (Figure 16a).

Specifications subject to change without notice.

AD9202

REV. C

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9202 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

With
Respect

Parameter

Min Max

Units

AVDD

AVSS

0.3 +6.5

DRVDD

DRVSS

0.3 +6.5

AVSS

DRVSS

0.3 +0.3

AVDD

DRVDD

6.5 +6.5

MODE

AVSS

0.3 AVDD + 0.3

CLK

AVSS

0.3 AVDD + 0.3

Digital Outputs

DRVSS

0.3 DRVDD + 0.3 V

AIN

AVSS

0.3 AVDD + 0.3

VREF

AVSS

0.3 AVDD + 0.3

REFSENSE

AVSS

0.3 AVDD + 0.3

REFTF, REFTB

AVSS

0.3 AVDD + 0.3

REFTS, REFBS

AVSS

0.3 AVDD + 0.3

Junction Temperature

+150

Storage Temperature

65 +150

Lead Temperature

10 sec

+300

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Options*

AD9202JRS

C to +70

28-Lead SSOP

RS-28

AD9202JRSRL

C to +70

28-Lead SSOP (Reel) RS-28

AD9202-EVAL

Evaluation Board

*RS = Shrink Small Outline.

DRVDD

AVSS

DRVSS

AVDD

AVSS

AVDD

REFTF

REFTS

AVDD

AVSS

AVDD

AVSS

REFBS

REFBF

AVSS

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

AVDD

AVSS

Figure 2. Equivalent Circuits

a. D0D9, OTR

b. Three-State, Standby, Clamp

c. CLK

d. AIN

e. Reference

f. CLAMPIN

g. MODE

h. REFSENSE

i. VREF

AD9202

REV. C

PIN CONFIGURATION

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

Description

AVSS

Analog Ground

DRVDD

Digital Driver Supply

Bit 0, Least Significant Bit

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9, Most Significant Bit

OTR

Out-of-Range Indicator

DRVSS

Digital Ground

CLK

Clock Input

THREE-STATE

HI: High Impedance State. LO: Normal Operation

STBY

HI: Power-Down Mode. LO: Normal Operation

REFSENSE

Reference Select

CLAMP

HI: Enable Clamp Mode. LO: No Clamp

CLAMPIN

Clamp Reference Input

REFTS

Top Reference

REFTF

Top Reference Decoupling

MODE

Mode Select

REFBF

Bottom Reference Decoupling

REFBS

Bottom Reference

VREF

Internal Reference Output

AIN

Analog Input

AVDD

Analog Supply

28-Lead Wide Body (SSOP)

TOP VIEW

(Not to Scale)

AD9202

AVSS

REFBS

VREF

AIN

AVDD

DRVDD

REFTF

MODE

REFBF

CLAMP

CLAMPIN

REFTS

OTR

DRVSS

REFSENSE

CLK

THREE-STATE

STBY

AD9202

REV. C

DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity (INL)

Integral nonlinearity refers to the deviation of each individual
code from a line drawn from "zero" through "full scale." The
point used as "zero" occurs 1/2 LSB before the first code transi-
tion. "Full scale" is defined as a level 1 1/2 LSB beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.

Differential Nonlinearity (DNL, No Missing Codes)

An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.

1.0

768

256

512

0.5

CODE OFFSET

0.5

640

128

384

DNL

896

1024

Figure 3. Typical DNL

1.0

768

256

512

0.5

CODE OFFSET

0.5

640

128

384

INL

896

1024

Figure 4. Typical INL

Offset Error

The first transition should occur at a level 1/2 LSB above "zero."
Offset is defined as the deviation of the actual first code transi-
tion from that point.

Gain Error

The first code transition should occur for an analog value 1/2 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 1/2 LSB below the nominal positive
full scale. Gain error is the deviation of the actual difference
between first and last code transitions and the ideal difference
between the first and last code transitions.

Pipeline Delay (Latency)

The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising edge.

INPUT FREQUENCY Hz

1.0E+05

SNR dB

1.0E+06

1.0E+07

1.0E+08

0.5dB

6dB

20dB

Figure 5. SNR vs. Input Frequency

INPUT FREQUENCY Hz

1.0E+05

SINAD dB

1.0E+06

1.0E+07

1.0E+08

0.5dB

6dB

20dB

Figure 6. SINAD vs. Input Frequency

(AVDD = +3 V, DRVDD = +3 V, F

= 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input

Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted)

Typical Characterization Curves

AD9202

REV. C

INPUT FREQUENCY Hz

30

1.0E+05

THD dB

35

40

45

50

55

60

65

70

1.0E+06

1.0E+07

1.0E+08

0.5dB

6dB

20dB

75

80

Figure 7. THD vs. Input Frequency

CLOCK FREQUENCY MHz

75

THD dB

70

65

60

55

50

45

100

Figure 8. THD vs. Clock Frequency

TEMPERATURE 

1.005

1.004

0.998

40

100

20

REF

 V

1.003

1.002

0.999

1.001

1.000

Figure 9. Voltage Reference Error vs. Temperature

100

CLOCK FREQUENCY MHz

POWER CONSUMPTION mW

Figure 10. Power Consumption vs. Clock Frequency
(MODE = AVSS)

1.2E+07

N1

CODE

HITS

N+1

1.0E+07

8.0E+06

6.0E+06

4.0E+06

2.0E+06

0.0E+00

1125000

10000000

887500

Figure 11. Grounded Input Histogram

2ND

140

0.0E+0

2.0E+6

4.0E+6

6.0E+6

8.0E+6

10.0E+6

12.0E+6

14.0E+6

16.0E+6

120

100

80

60

40

20

3RD

4TH

5TH

7TH

9TH

FUND

8TH

6TH

FREQUENCY Hz

Figure 12. Single-Tone Frequency Domain
(A

= 2.5 MHz, F

= 32 MHz)

AD9202

REV. C

1.0E+6

1.0E+9

10.0E+6

SIGNAL AMPLITUDE dB

100.0E+6

FREQUENCY Hz

12

15

18

21

24

27

Figure 13. Large Signal Frequency Response

25

3.0

1.0

2.0

10

15

INPUT VOLTAGE V

20

2.5

0.5

1.5

REFBS = 0.5V
REFTS = 2.5V
CLOCK = 32MHz

Figure 14. Input Bias Current vs. Input Voltage

APPLYING THE AD9202

THEORY OF OPERATION

The AD9202 implements a pipelined multistage architecture to
achieve high sample rate with low power. The AD9202 distrib-
utes the conversion over several smaller A/D subblocks, refining
the conversion with progressively higher accuracy as it passes
the results from stage to stage. As a consequence of the distrib-
uted conversion, the AD9202 requires a small fraction of the
1023 comparators used in a traditional flash type A/D. A
sample-and-hold function within each of the stages permits the
first stage to operate on a new input sample while the second,
third and fourth stages operate on the three preceding samples.

OPERATIONAL MODES

The AD9202 is designed to allow optimal performance in a
wide variety of imaging, communications and instrumentation
applications, including pin compatibility with the AD9200. To
realize this flexibility, internal switches on the AD9202 are used
to reconfigure the circuit into different modes. These modes are
selected by appropriate pin strapping. There are three parts of
the circuit affected by this modality: the voltage reference, the
reference buffer, and the analog input. The nature of the appli-
cation will determine which mode is appropriate: the descrip-
tions in the following sections, as well as in Table I, should
assist in choosing the desired mode.

Table I. Mode Selection

Input

MODE

REFSENSE

Modes

Connect

Span

Pin

REF

REFTS

REFBS

Figure

TOP/BOTTOM

AIN

1 V

AVDD

Short REFSENSE, REFTS and VREF Together

AGND

AIN

2 V

AVDD

AGND

Short REFTS and VREF Together

AGND

CENTER SPAN

AIN

1 V

AVDD/2

Short VREF and REFSENSE Together

AVDD/2

AIN

2 V

AVDD/2

AGND

No Connect

AVDD/2

Differential

AIN Is Input 1

1 V

AVDD/2

Short VREF and REFSENSE Together

AVDD/2

REFTS and
REFBS Are
Shorted Together
for Input 2

2 V

AVDD/2

AGND

No Connect

AVDD/2

External Ref

AIN

2 V max AVDD

AVDD

No Connect

Span = REFTS

21, 22

REFBS (2 V max)

AGND

Short to

VREFTF

VREFBF

AD9202

REV. C

SUMMARY OF MODES

VOLTAGE REFERENCE

1 V Mode The internal reference may be set to 1 V by connect-
ing REFSENSE and VREF together.

2 V Mode The internal reference my be set to 2 V by connecting
REFSENSE to analog ground

External Divider Mode The internal reference may be set to a
point between 1 V and 2 V by adding external resistors. See
Figure 16f.

External Reference Mode enables the user to apply an external
reference to REFTS, REFBS and VREF pins. This mode
is attained by tying REFSENSE to VDD.

REFERENCE BUFFER

Center Span Mode midscale is set by shorting REFTS and
REFBS together and applying the midscale voltage to that point
The MODE pin is set to AVDD/2. The analog input will swing
about that midscale point.

Top/Bottom Mode sets the input range between two points.
The two points are between 1 V and 2 V apart. The Top/Bottom
Mode is enabled by tying the MODE pin to AVDD.

ANALOG INPUT

Differential Mode is attained by driving the AIN pin as one
differential input and shorting REFTS and REFBS together and
driving them as the second differential input. The MODE pin
is tied to AVDD/2. Preferred mode for optimal distortion
performance.

Single-Ended is attained by driving the AIN pin while the
REFTS and REFBS pins are held at dc points. The MODE pin is
tied to AVDD.

Single-Ended/Clamped (AC Coupled) The input may be
clamped to some dc level by ac coupling the input. This is done
by tying the CLAMPIN to some dc point and applying a pulse to
the CLAMP pin. MODE pin is tied to AVDD.

SPECIAL

Users of the AD9200 may upgrade their system by dropping the
AD9202 right into their socket.

INPUT AND REFERENCE OVERVIEW

Figure 15, a simplified model of the AD9202, highlights the
relationship between the analog input, AIN, and the reference
voltages, REFTS, REFBS and VREF. Like the voltages applied
to the resistor ladder in a flash A/D converter, REFTS and
REFBS define the maximum and minimum input voltages to the
A/D.

The input stage is normally configured for single-ended opera-
tion, but allows for differential operation by shorting REFTS
and REFBS together to be used as the second input.

SHA

AIN

REFTS

REFBS

A/D

CORE

AD9202

Figure 15. Equivalent Functional Input Circuit

In single-ended operation, the input spans the range,

REFBS

AIN

REFTS

where REFBS can be connected to GND and REFTS con-
nected to VREF. If the user requires a different reference range,
REFBS and REFTS can be driven to any voltage within the
power supply rails, so long as the difference between the two is
between 1 V and 2 V.

In differential operation, REFTS and REFBS are shorted to-
gether, and the input span is set by VREF,

(REFTS VREF/2)

AIN

(REFTS + VREF/2)

where VREF is determined by the internal reference or brought
in externally by the user.

The best noise performance may be obtained by operating the
AD9202 with a 2 V input range. The best distortion perfor-
mance may be obtained by operating the AD9202 with a 1 V
input range.

REFERENCE OPERATION

The AD9202 can be configured in a variety of reference topolo-
gies. The simplest configuration is to use the AD9202's onboard
bandgap reference, which provides a pin-strappable option to
generate either a 1 V or 2 V output. If the user desires a refer-
ence voltage other than those two, an external resistor divider
can be connected between VREF, REFSENSE and analog
ground to generate a potential anywhere between 1 V and 2 V.
Another alternative is to use an external reference for designs
requiring enhanced accuracy and/or drift performance. A
third alternative is to bring in top and bottom references,
bypassing VREF altogether.

Figures 16d, 16e, 16f and 16g illustrate the reference architec-
ture of the AD9202. In tailoring a desired arrangement, the user
can select an input configuration to match drive circuit. Then,
moving to the reference modes at the bottom of the figure,
select a reference circuit to accommodate the offset and ampli-
tude of a full-scale signal.

Table I outlines pin configurations to match user requirements.

AD9202

REV. C

SHA

10k

A/D

CORE

4.2k
TOTAL

REFTS

REFBS

10 F

0.1 F

REFTF

REFBF

0.1 F

AIN

+F/S RANGE OBTAINED

FROM VREF PIN OR

EXTERNAL REF

F/S RANGE OBTAINED

FROM VREF PIN OR

EXTERNAL REF

0.1 F

MODE
(AVDD)

+FS

FS

AD9202

10k

a. Top/Bottom Mode

MAXIMUM MAGNITUDE OF V
IS DETERMINED BY INTERNAL
REFERENCE AND TURNS RATIO

MODE

INTERNAL

REF

AVDD/2

SHA

10k

A/D

CORE

4.2k
TOTAL

10 F

0.1 F

REFTF

REFBF

0.1 F

AIN

0.1 F

AD9202

10k

REFTS

REFBS

AVDD/2

c. Differential Mode

AVSS

REFSENSE

VREF
(1V)

AD9202

d. 1 V Reference

10k

AVSS

REFSENSE

VREF
(2V)

AD9202

e. 2 V Reference

AVSS

REFSENSE

VREF
(= 1 + R

)

INTERNAL 10K REF RESISTORS ARE
SWITCHED OPEN BY THE PRESENSE
OF R

AND R

AD9202

f. Variable Reference

(Between 1 V and 2 V)

Figure 16. Operational Modes

REFSENSE
AVDD

VREF

AD9202

g. Internal Reference Disable
(Power Reduction)

MODE

INTERNAL

REF

MIDSCALE OFFSET
VOLTAGE IS DERIVED
FROM INTERNAL OR
EXTERNAL REF

MIDSCALE

AVDD/2

*MAXIMUM MAGNITUDE OF V IS DETERMINED

BY INTERNAL REFERENCE

10k

A/D

CORE

4.2k
TOTAL

REFTS

REFBS

10 F

0.1 F

REFTF

REFBF

0.1 F

AIN

0.1 F

AD9202

10k

SHA

b. Center Span Mode

AD9202

REV. C

The actual reference voltages used by the internal circuitry of
the AD9202 appear on REFTF and REFBF. For proper opera-
tion, it is necessary to add a capacitor network to decouple these
pins. The REFTF and REFBF should be decoupled for all
internal and external configurations as shown in Figure 17.

AD9202

REFTF

REFBF

0.1 F

10 F

0.1 F

Figure 17. Reference Decoupling Network

Note: REFTF = reference top, force

REFBF = reference bottom, force
REFTS = reference top, sense
REFBS = reference bottom, sense

INTERNAL REFERENCE OPERATION

Figures 18, 19 and 20 show example hookups of the AD9202
internal reference in its most common configurations. (Figures
18 and 19 illustrate top/bottom mode while Figure 20 illustrates
center span mode). Figure 29 shows how to connect the AD9202
for 1 V p-p differential operation. Shorting the VREF pin di-
rectly to the REFSENSE pin places the internal reference
amplifier, A1, in unity-gain mode and the resultant reference
output is 1 V. In Figure 18 REFBS is grounded to give an input
range from 0 V to 1 V. These modes can be chosen when the
supply is either +3 V or +5 V. The VREF pin must be bypassed
to AVSS (analog ground) with a 1.0

F tantalum capacitor in

parallel with a low inductance, low ESR, 0.1

F ceramic capacitor.

MODE

AVDD

10k

A/D

CORE

4.2k
TOTAL

REFTS

REFBS

10 F

0.1 F

REFTF

REFBF

0.1 F

AIN

0.1 F

AD9202

10k

REF

SENSE

VREF

SHA

Figure 18. Internal Reference--1 V p-p Input Span
(Top/Bottom Mode)

Figure 19 shows the single-ended configuration for 2 V p-p
operation. REFSENSE is connected to GND, resulting in a 2 V
reference output.

MODE

AVDD

10k

A/D

CORE

4.2k
TOTAL

REFTS

REFBS

10 F

0.1 F

REFTF

REFBF

0.1 F

AIN

0.1 F

AD9202

10k

REF

SENSE

VREF

SHA

Figure 19. Internal Reference, 2 V p-p Input Span
(Top/Bottom Mode)

Figure 20 shows the single-ended configuration that gives the
good high frequency dynamic performance (SINAD, SFDR).
To optimize dynamic performance, center the common-mode
voltage of the analog input at approximately 1.5 V. Connect the
shorted REFTS and REFBS inputs to a low impedance 1.5 V
source. In this configuration, the MODE pin is driven to a volt-
age at midsupply (AVDD/2).

Maximum reference drive is 1 mA. An external buffer is re-
quired for heavier loads.

AVDD/2

+1.5V

MODE

10k

A/D

CORE

4.2k
TOTAL

REFTS

REFBS

10 F

0.1 F

REFTF

REFBF

0.1 F

AIN

0.1 F

AD9202

10k

REF

SENSE

VREF

SHA

Figure 20. Internal Reference 1 V p-p Input Span

(Center Span Mode)

EXTERNAL REFERENCE OPERATION

Using an external reference may provide more flexibility and
improve drift and accuracy. Figures 21 through 23 show ex-
amples of how to use an external reference with the AD9202.
To use an external reference, the user must disable the internal
reference amplifier by connecting the REFSENSE pin to VDD.
The user then has the option of driving the VREF pin, or driv-
ing the REFTS and REFBS pins.

AD9202

REV. C

The AD9202 contains an internal reference buffer (A2), that
simplifies the drive requirements of an external reference. The
external reference must simply be able to drive a 10 k

load.

Figure 21 shows an example of the user driving the top and
bottom references. REFTS is connected to a low impedance 2 V
source and REFBS is connected to a low impedance 1 V source.
REFTS and REFBS may be driven to any voltage within the
supply as long as the difference between them is between 1 V
and 2 V.

AVDD

MODE

10k

A/D

CORE

4.2k
TOTAL

REFTS

REFBS

10 F

0.1 F

REFTF

REFBF

0.1 F

AIN

0.1 F

AD9202

10k

REF

SENSE

SHA

Figure 21. External Reference Mode--1 V p-p Input Span

Figure 22 shows an example of an external reference generating
2.5 V at the shorted REFTS and REFBS inputs. In this in-
stance, a REF43 2.5 V reference drives REFTS and REFBS. A
resistive divider generates a 1 V VREF signal that is buffered by
A3. A3 must be able to drive a 10 k

, capacitive load. Choose

this op amp based on noise and accuracy requirements.

3.0V

2.0V

2.5V

AVDD

AIN

REFTS

REFTF

REFBF

REFBS

VREF

REFSENSE

MODE

AD9202

0.1 F

1.5k

10 F

0.1 F

REF43

+5V

0.1 F

10 F

AVDD

0.1 F

AVDD

0.1 F

AVDD/2

Figure 22. External Reference Mode--1 V p-p Input
Span 2.5 V

Figure 23a shows an example of the external references driving
the REFTF and REFBF pins. REFTS is shorted to REFTF
and driven by an external 4 V low impedance source. REFBS is
shorted to REFBF and driven by a 2 V source. The MODE pin
is connected to GND in this configuration.

0.1 F

AVDD

10 F

0.1 F

VIN

REFTS

REFTF

REFBF

REFBS

VREF

REFSENSE

MODE

AD9202

Figure 23a. External Reference ~ 2 V p-p Input Span

+5V

C3
0.1 F

C4
0.1 F

REFTS

REFTF

C2
10 F

C6
0.1 F

C5
0.1 F

REFBS

REFBF

C1
0.1 F

AD9202

REFT

REFB

Figure 23b. Kelvin Connected Reference Using the AD9202

CLAMP OPERATION

The AD9202 feature a clamp circuit for dc restoration of video
or ac coupled signals. Figure 24 shows the internal clamp cir-
cuitry and the external control signals needed for clamp opera-
tion. To enable the clamp, apply a logic high to the CLAMP
pin. This will close the switch SW1. The clamp amplifier will
then servo the voltage at the AIN pin to be equal to the clamp
voltage applied at the CLAMPIN pin. After the desired clamp
level is attained, SW1 is opened by taking CLAMP back to a
logic low. Ignoring the droop caused by the input bias current,
the input capacitor CIN will hold the dc voltage at AIN con-
stant until the next clamp interval. The input resistor RIN has a
minimum recommended value of 10

, to maintain the closed-

loop stability of the clamp amplifier.

The allowable voltage range that can be applied to CLAMPIN
depends on the operational limits of the internal clamp ampli-
fier. When operating off of 3 volt supplies, the recommended
clamp range is between 0.5 volts and 2.0 volts.

STANDBY OPERATION

The ADC may be placed into a powered down (sleep) mode by
driving the STBY (standby) pin to logic high potential and
holding the clock at logic low. In this mode the typical power
drain is approximately 3.5 mW. If there is no connection to the
STBY pin, an internal pull-down circuit will keep the ADC in a
"wake-up" mode of operation.

AD9202

REV. C

The ADC will "wake up" in 400 ns (typ) after the standby pulse
goes low.

The input capacitor should be sized to allow sufficient acquisi-
tion time of the clamp voltage at AIN within the CLAMP inter-
val, but also be sized to minimize droop between clamping
intervals. Specifically, the acquisition time when the switch is
closed will equal:

ACQ

where V

is the voltage change required across C

, and V

the error voltage. V

is calculated by taking the difference be-

tween the initial input dc level at the start of the clamp interval
and the clamp voltage supplied at CLAMPIN. V

is a system

dependent parameter, and equals the maximum tolerable devia-
tion from V

. For example, if a 2-volt input level needs to be

clamped to 1 volt at the AD9202's input within 10 millivolts,
then V

equals 2 1 or 1 volt, and V

equals 10 mV. Note that

once the proper clamp level is attained at the input, only a very
small voltage change will be required to correct for droop.

The voltage droop is calculated with the following equation:

BIAS

( )

where t = time between clamping intervals.

The bias current of the AD9202 will depend on the sampling
rate, F

. The switched capacitor input AIN appears resistive

over time, with an input resistance equal to 1/C

. Given a

sampling rate of 32 MSPS and an input capacitance of 1 pF, the
input resistance is 31.2 k

. This input resistance is equivalently

terminated at the midscale voltage of the input range. The worst
case bias current will thus result when the input signal is at the
extremes of the input range, that is, the furthest distance from
the midscale voltage level. For a 1-volt input range, the maxi-
mum bias current will be

0.5 volts divided by 50 k

, which is

If droop is a critical parameter, the minimum value of C

should

be calculated first based on the droop requirement. Acquisi-
tion time--the width of the CLAMP pulse--can be adjusted
accordingly once the minimum capacitor value is chosen. A
tradeoff will often need to be made between droop and acquisi-
tion time, or error voltage V

Clamp Circuit Example

A single supply video amplifier outputs a level-shifted video
signal between 2 and 3 volts with the following parameters:

horizontal period = 63.56

horizontal sync interval = 10.9

horizontal sync pulse = 4.7

sync amplitude = 0.3 volts,
video amplitude of 0.7 volts,
reference black level = 2.3 volts

The video signal must be dc restored from a 2- to 3-volt range
down to a 1- to 2-volt range. Configuring the AD9202 for a
one volt input span with an input range from 1 to 2 volts (see
Figure 24), the CLAMPIN voltage can be set to 1 volt with an
external voltage or by direct connection to REFBS. The CLAMP

pulse may be applied during the SYNC pulse, or during the
back porch to truncate the SYNC below the AD9202's mini-
mum input voltage. With a C

= 1

F, and R

= 20

, the

acquisition time needed to set the input dc level to 1 volt with
1 mV accuracy is about 140

s, assuming a full 1 volt V

With a 1

F input coupling capacitor, the droop across one

horizontal can be calculated:

BIAS

= 10

A, and t = 63.5

s, so dV = 0.635 mV, which is less

than one LSB.

After the input capacitor is initially charged, the clamp pulse
width only needs to be wide enough to correct small voltage
errors such as the droop. The fine scale settling characteristics
of the clamp circuitry are shown in Table II.

Depending on the required accuracy, a CLAMP pulse width of
1

s should work in most applications. The OFFSET val-

ues ignore the contribution of offset from the clamp amplifier;
they simply compare the output code with a "final value" mea-
sured with a much longer CLAMP pulse duration.

Table II.

CLAMP

OFFSET

<1 LSB

5 LSBs

7 LSBs

11 LSBs

19 LSBs

42 LSBs

CLAMP IN

AD9202

CLAMP

AIN

CIN

RIN

TO
SHA

SW1

Figure 24a. Clamp Operation

0.1 F

10 F

AIN

REFTF

REFBS

MODE

AD9202

REFTS

0.1 F

REFBF

CLAMP

CLAMPIN

AVDD

SHORT TO REFBS
OR EXTERNAL DC

0.1 F

Figure 24b. Video Clamp Circuit

AD9202

REV. C

DRIVING THE ANALOG INPUT

Figure 25 shows the equivalent analog input of the AD9202, a
sample-and-hold amplifier (switched capacitor input SHA).
Bringing CLK to a logic low level closes Switches 1 and 2 and
opens Switch 3. The input source connected to AIN must
charge capacitor CH during this time. When CLK transitions
from logic "low" to logic "high," Switches 1 and 2 open, placing
the SHA in hold mode. Switch 3 then closes, forcing the output
of the op amp to equal the voltage stored on CH. When CLK
transitions from logic "high" to logic "low," Switch 3 opens
first. Switches 1 and 2 close, placing the SHA in track mode.

AIN

(REFTS

REFBS)

SHA

AD9202

Figure 25. Equivalent Input Structure

The structure of the input SHA places certain requirements on
the input drive source. The combination of the pin capacitance,
CP, and the hold capacitance, CH, is typically less than 5 pF.
The input source must be able to charge or discharge this ca-
pacitance to 10-bit accuracy in one half of a clock cycle. When
the SHA goes into track mode, the input source must charge or
discharge capacitor CH from the voltage already stored on CH
to the new voltage. In the worst case, a full-scale voltage step on
the input, the input source must provide the charging current
through the R

(50

) of Switch 1 and quickly (within 1/2 CLK

period) settle. This situation corresponds to driving a low input
impedance. On the other hand, when the source voltage equals
the value previously stored on CH, the hold capacitor requires
no input current and the equivalent input impedance is ex-
tremely high.

Adding series resistance between the output of the source and
the AIN pin reduces the drive requirements placed on the
source. Figure 26 shows this configuration. The bandwidth of
the particular application limits the size of this resistor. To
maintain the performance outlined in the data sheet specifica-
tions, the resistor should be limited to 20

or less. For applica-

tions with signal bandwidths less than 10 MHz, the user may
proportionally increase the size of the series resistor. Alterna-
tively, adding a shunt capacitance between the AIN pin and
analog ground can lower the ac load impedance. The value of
this capacitance will depend on the source resistance and the
required signal bandwidth.

The input span of the AD9202 is a function of the reference
voltages. For more information regarding the input range, see
the Internal and External Reference sections of the data sheet.

AIN

AD9202

Figure 26. Simple Drive Configuration

In many cases, particularly in single-supply operation, ac cou-
pling offers a convenient way of biasing the analog input signal
at the proper signal range. Figure 27 shows a typical configura-
tion for ac-coupling the analog input signal to the AD9202.
Maintaining the specifications outlined in the data sheet re-
quires careful selection of the component values. The most
important is the f

3 dB

high-pass corner frequency. It is a func-

tion of R2 and the parallel combination of C1 and C2. The
f

3 dB

point can be approximated by the equation:

3 dB

= 1/(2

[R2] C

)

where C

is the parallel combination of C1 and C2. Note that

C1 is typically a large electrolytic or tantalum capacitor that
becomes inductive at high frequencies. Adding a small ceramic
or polystyrene capacitor (on the order of 0.01

F) that does not

become inductive until negligibly higher frequencies, maintains
a low impedance over a wide frequency range.

NOTE: AC-coupled input signals may also be shifted to a desired
level with the AD9202's internal clamp. See Clamp Operation.

AIN

AD9202

BIAS

Figure 27. AC-Coupled Input

There are additional considerations when choosing the resistor
values. The ac-coupling capacitors integrate the switching tran-
sients present at the input of the AD9202 and cause a net dc
bias current, I

, to flow into the input. The magnitude of the

bias current increases as the signal magnitude deviates from
V midscale and the clock frequency increases; i.e., minimum
bias current flow when AIN = V midscale. This bias current
will result in an offset error of (R1 + R2)

. If it is necessary

to compensate this error, consider making R2 negligibly small or
modifying VBIAS to account for the resultant offset.

In systems that must use dc coupling, use an op amp to level-shift a
ground-referenced signal to comply with the input requirements
of the AD9202. Figure 28 shows an AD8041 configured in
noninverting mode.

AIN

AD9202

0.1 F

MIDSCALE

OFFSET

VOLTAGE

1V p-p

AD8041

Figure 28. Bipolar Level Shift

AD9202

REV. C

DIFFERENTIAL INPUT OPERATION

The AD9202 will accept differential input signals. This function
may be used by shorting REFTS and REFBS and driving them
as one leg of the differential signal (the top leg is driven into
AIN). In the configuration below, the AD9202 is accepting a
1 V p-p signal. See Figure 29.

AIN

REFTS

REFTF

REFBF

REFBS

AD9202

0.1 F

10 F

0.1 F

AVDD/2

VREF

REFSENSE

MODE

AVDD/2

Figure 29. Differential Input

CLOCK INPUT

The AD9202 clock input is buffered internally with an inverter
powered from the AVDD pin. This feature allows the AD9202
to accommodate either +5 V or +3.3 V CMOS logic input sig-
nal swings with the input threshold for the CLK pin nominally
at AVDD/2.

The pipelined architecture of the AD9202 operates on both
rising and falling edges of the input clock. To minimize duty
cycle variations the recommended logic family to drive the clock
input is high speed or advanced CMOS (HC/HCT, AC/ACT)
logic. CMOS logic provides both symmetrical voltage threshold
levels and sufficient rise and fall times to support 32 MSPS
operation. The AD9202 is designed to support a conversion rate
of MSPS; running the part at slightly faster clock rates may be
possible, although at reduced performance levels. Conversely,
some slight performance improvements might be realized by
clocking the AD9202 at slower clock rates.

25ns

DATA 1

DATA

OUTPUT

INPUT

CLOCK

ANALOG

INPUT

Figure 30. Timing Diagram

The power dissipated by the output buffers is largely propor-
tional to the clock frequency; running at reduced clock rates
provides a reduction in power consumption.

DIGITAL INPUTS AND OUTPUTS

Each of the AD9202 digital control inputs, THREE-STATE
and STBY are reference to analog ground. The clock is also
referenced to analog ground.

The format of the digital output is straight binary (see Figure
31). A low power mode feature is provided such that for STBY
= HIGH and the clock disabled, the static power of the AD9202
will drop below 5 mW.

OTR

FS

FS+1LSB

+FS1LSB

+FS

OTR

DATA OUTPUTS

1
0
0

0
0
1

11111 11111
11111 11111
11111 11110

00000 00001
00000 00000
00000 00000

Figure 31. Output Data Format

HIGH

IMPEDANCE

DHZ

DEN

THREE-

STATE

DATA

(D0D9)

Figure 32. Three-State Timing Diagram

APPLICATIONS

DIRECT IF DOWN CONVERSION USING THE AD9202

Sampling IF signals above an ADC's baseband region (i.e., dc
to F

/2) is becoming increasingly popular in communication

applications. This process is often referred to as Direct IF Down
Conversion or Undersampling. There are several potential ben-
efits in using the ADC to alias (i.e., or mix) down a narrowband
or wideband IF signal. First and foremost is the elimination of a
complete mixer stage with its associated amplifiers and filters,
reducing cost and power dissipation. Second is the ability to
apply various DSP techniques to perform such functions as
filtering, channel selection, quadrature demodulation, data
reduction, detection, etc. A detailed discussion on using this
technique in digital receivers can be found in Analog Devices
Application Notes AN-301 and AN-302.

In Direct IF Down Conversion applications, one exploits the
inherent sampling process of an ADC in which an IF signal
lying outside the baseband region can be aliased back into the
baseband region in a similar manner that a mixer will down-
convert an IF signal. Similar to the mixer topology, an image
rejection filter is required to limit other potential interfering
signals from also aliasing back into the ADC's baseband region.
A tradeoff exists between the complexity of this image rejection
filter and the sample rate as well as dynamic range of the ADC.

The AD9202 is well suited for various narrowband IF sampling
applications. The AD9202's low distortion input SHA has a
full-power bandwidth extending to 300 MHz thus encompassing
many popular IF frequencies. A DNL of

0.5 LSB (typ) com-

bined with low thermal input referred noise allows the AD9202 in
the 2 V span to provide 60 dB of SNR for a baseband input sine
wave. Also, its low aperture jitter of 2 ps rms ensures minimum
SNR degradation at higher IF frequencies. In fact, the AD9202
is capable of still maintaining 50 dB of SNR at an IF of 135 MHz
with a 1 V (i.e., 4 dBm) input span. Note, although the AD9202
will typically yield a 3 to 4 dB improvement in SNR when con-
figured for the 2 V span, the 1 V span provides the optimum
full-scale distortion performance. Furthermore, the 1 V span
reduces the performance requirements of the input driver cir-
cuitry and thus may be more practical for system implementa-
tion purposes.

AD9202

REV. C

Figure 33 shows a simplified schematic of the AD9202 config-
ured in an IF sampling application. To reduce the complexity of
the digital demodulator in many quadrature demodulation ap-
plications, the IF frequency and/or sample rate are selected such
that the bandlimited IF signal aliases back into the center of the
ADC's baseband region (i.e., F

/4). For example, if an IF sig-

nal centered at 45 MHz is sampled at 20 MSPS, an image of
this IF signal will be aliased back to 5.0 MHz which corre-
sponds to one quarter of the sample rate (i.e., F

/4). This

demodulation technique typically reduces the complexity of the
post digital demodulator ASIC which follows the ADC.

To maximize its distortion performance, the AD9202 is config-
ured in the differential mode with a 1 V span using a transformer.
The center tap of the transformer is biased at midsupply via a
resistor divider. Preceding the AD9202 is a bandpass filter as
well as a 32 dB gain stage. A large gain stage may be required
to compensate for the high insertion losses of a SAW filter used
for image rejection. The gain stage will also provide adequate
isolation for the SAW filter from the charge "kick back" currents
associated with AD9202's input stage.

The gain stage can be realized using one or two cascaded
AD8009 op amps amplifiers. The AD8009 is a low cost, 1 GHz,
current-feedback op amp having a 3rd order intercept character-
ized up to 250 MHz. A passive bandpass filter following the
AD8009 attenuates its dominant 2nd order distortion products
which would otherwise be aliased back into the AD9202's
baseband region. Also, it reduces any out-of-band noise which
would also be aliased back due to the AD9202's noise band-
width of 220+ MHz. Note, the bandpass filters specifications
are application dependent and will affect both the total distor-
tion and noise performance of this circuit.

The distortion and noise performance of an ADC at the given
IF frequency is of particular concern when evaluating an ADC
for a narrowband IF sampling application. Both single-tone and
dual-tone SFDR vs. amplitude are very useful in an assessing an
ADC's noise performance and noise contribution due to aper-
ture jitter. In any application, one is advised to test several units
of the same device under the same conditions to evaluate the
given applications sensitivity to that particular device.

Figures 3437 combine the dual-tone SFDR as well as single
tone SFDR and SNR performance at IF frequencies of 45 MHz,
70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. ampli-
tude data is referenced to dBFS while the single tone SNR data
is referenced to dBc. The performance characteristics in these
figures are representative of the AD9202 without the AD8009.
The AD9202 was operated in the differential mode (via trans-
former) with a 1 V span.

40

35

INPUT POWER LEVEL dBFS

SFDR dBFS, SNR dBc

30

25

20

15

10

SNR

SINGLE-TONE SFDR

DUAL-TONE SFDR

Figure 34. SNR/SFDR for IF @ 45 MHz (Clock = 27.5 MHz)

40

35

INPUT POWER LEVEL dBFS

SFDR dBFS, SNR dBc

30

25

20

15

10

SNR

SINGLE-TONE SFDR

DUAL-TONE SFDR

Figure 35. SNR/SFDR for IF @ 70 MHz (Clock = 31.1 MHz)

0.1 F

AIN

REFTS

AD9202

REFBS

REFSENSE

VREF

AVDD

200

93.1

280

22.1

200

SAW

FILTER

OUTPUT

BANDPASS

FILTER

= 20dB

= 12dB

L-C

MINI CIRCUITS

T4 - 6T

1:4

Figure 33. Simplified IF Sampling Circuit

AD9202

REV. C

40

35

INPUT POWER LEVEL dBFS

SFDR dBFS, SNR dBc

30

25

20

15

10

SNR

SINGLE-TONE SFDR

DUAL-TONE SFDR

Figure 36. SNR/SFDR for IF @ 85 MHz (Clock = 30.9 MHz)

40

35

SFDR dBFS, SNR dBc

30

25

20

15

10

SNR

INPUT POWER LEVEL dBFS

SINGLE-TONE SFDR

DUAL-TONE SFDR

Figure 37. SNR/SFDR for IF @ 135 MHz (Clock = 32 MHz)

Although not presented, data was also taken with the insertion
of an AD8009 gain stage of 32 dB in the signal path. No
degradation in two-tone SFDR vs. amplitude was noted at an
IF of 45 MHz, 70 MHz and 85 MHz. However, at 135 MHz,
the AD8009 became the limiting factor in the distortion perfor-
mance until the two input tones were decreased to 15 dBFS
from their full-scale level of 6.5 dBFS. Note: the SNR perfor-
mance in each case degraded by approximately 0.5 dB due to
the AD8009's in-band noise contribution.

GROUNDING AND LAYOUT RULES

As is the case for any high performance device, proper ground-
ing and layout techniques are essential in achieving optimal
performance. The analog and digital grounds on the AD9202
have been separated to optimize the management of return
currents in a system. Grounds should be connected near the
ADC. It is recommended that a printed circuit board (PCB) of
at least four layers, employing a ground plane and power planes,
be used with the AD9202. The use of ground and power planes
offers distinct advantages:

1. The minimization of the loop area encompassed by a signal

and its return path.

2. The minimization of the impedance associated with ground

and power paths.

3. The inherent distributed capacitor formed by the power plane,

PCB insulation and ground plane.

These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.

It is important to design a layout that prevents noise from cou-
pling onto the input signal. Digital signals should not be run in
parallel with the input signal traces and should be routed away
from the input circuitry. Separate analog and digital grounds
should be joined together directly under the AD9202 in a solid
ground plane. The power and ground return currents must be
carefully managed. A general rule of thumb for mixed signal
layouts dictates that the return currents from digital circuitry
should not pass through critical analog circuitry.

DIGITAL OUTPUTS

Each of the on-chip buffers for the AD9202 output bits
(D0D9) is powered from the DRVDD supply pins, separate
from AVDD. The output drivers are sized to handle a variety
of logic families while minimizing the amount of glitch energy
generated. In all cases, a fan-out of one is recommended to keep
the capacitive load on the output data bits below the specified
20 pF level.

For DRVDD = 5 V, the AD9202 output signal swing is compat-
ible with both high speed CMOS and TTL logic families. For
TTL, the AD9202 on-chip, output drivers were designed to
support several of the high speed TTL families (F, AS, S). For
applications where the clock rate is below MSPS, other TTL
families may be appropriate. For interfacing with lower voltage
CMOS logic, the AD9202 sustains MSPS operation with
DRVDD = 3 V. In all cases, check your logic family data sheets
for compatibility with the AD9202 Digital Specification table.

THREE-STATE OUTPUTS

The digital outputs of the AD9202 can be placed in a high
impedance state by setting the THREE-STATE pin to HIGH.
This feature is provided to facilitate in-circuit testing or evaluation.

AD9202

REV. C

AD822

JP5

JP17

JP18

GND

R53
49.9

R37
1k

R38
1k

R39
1k

DRVDD

S3 2

3
A

TP11

CLAMP

THREE-STATE

STBY

R14

10k

C9
10/10V

+35A

C10

0.1 F

R18
316k

R16

C29

0.1 F

Q2
2N3904

C14
0.1 F

C15
10/10V

TP17

EXTB

R20
178

R19
178

C12
0.1 F

C13
10/10V

TP16

EXTT

Q1
2N3906

0.626V TO 4.8V

R17
316

R15

C11

0.1 F

+35A

R13

11k

R12

10k

C8
10/10V

0.1 F

+35A

R10

R11

15k

XXXX

ADJ.

TP14

10k

R9
1.5k

AD1580

+35A

5.49k

XXXX

ADJ.

DUTCLK

THREE-STATE

STBY

REFSENSE

CLAMP

CLAMPIN

REFTS
REFTF

MODE

REFBF
REFBS

VREF

AIN

C33

10/10V

AD9202

CLK
THREE-STATE
STBY
REFSENSE
CLAMP
CLAMPIN
REFTS
REFTF
MODE
REFBF
REFBS
VREF
AIN

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

AVSS

DRVSS

AVDD

C17
10/10V

AVDD

C16
0.1 F

C18
10/10V

C19
0.1 F

DRVDD

OTR

TP19

3
4
5
6
7
8
9
10
11
12

15
16
17
18
19
20
21
22
23
24
25
26
27

RN1
22

RN2
22

RN1
22

RN2
22

CLK

CLK_OUT

+35D

GND

+35D

GND

C20
0.1 F

JP21

C21
0.1 F

C43
0.1 F

GND

JP20

GND

C41
0.1 F

74LVXC4245WM

C40

0.1 F

GND

DRVDD

CLK

DRVDD

D5
D6
D7
D8
D9

D0
D1
D2
D3
D4

16
15
21
20
19
18
17
14
24
23
22
13

19
20
21
18
17
16
15
14

24
23
22
13

5
4
3
6
7
8
9
10
1
2
11
12

8
9
3
4
5
6
7
10
1
2
11
12

VCCB VCCA
NC1

T/R

GD2

GD1 U4 GD3

VCCB VCCA
NC1

T/R

GD2

GD1 U5 GD3

OTR

DRVDD

WHITE

AD822

C42
0.1 F

Figure 38a. Evaluation Board Schematic

AD9202

REV. C

C32
0.1 F

TP29

+35D

C31
10/10V

C22
0.1 F

TP20

DRVDD

C23
10/10V

C24
0.1 F

TP21

AVDD

C25
33/16V

C26
0.1 F

TP22

+35A

C27
10/10V

GND J6

TP23

TP24 TP25 TP26 TP27 TP28

GND J10

C28
0.1 F

U6 DECOUPLING

AVDDCLK

74AHC14

PWR

GND

TP1

AVDD

VREF

TP5

TP6

JP1

JP2

JP3

JP4

JP6

JP9

TP7

C35
10/10V

C36
0.1 F

C37
0.1 F

C38
0.1 F

GND

JP12

JP11

GND

JP13

JP7

C6
0.1 F

C3
0.1 F

TP3

TP4

JP10

C4
0.1 F

10/10V

REFSENSE

EXTB

REFBF

REFTF

EXTT

CLAMPIN

EXTT

REFTS

REFBS

EXTB

TP8

JP8

JP26

TP10

DCIN

TP9

100

A
3

0.1 F

47/10V

AIN

REFBS

T11T

1 B

R1
49.9

TP12

R51
49.9

CLK

TP13

DUTCLK

R52

49.9

R4
49.9

ADC_CLK

C30

0.1 F

JP22

AVDD

AVDDCLK

R35
4.99k

R36

4.99k

R34

AVDD

MODE

10k

JP14

JP15

JP16

GND

Figure 38b. Evaluation Board Schematic

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD9202

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD9202