REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD9617
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
Low Distortion, Precision,
Wide Bandwidth Op Amp
FEATURES
Usable Closed-Loop Gain Range: 1 to 40
Low Distortion: 67 dBc (2nd) at 20 MHz
Small Signal Bandwidth: 190 MHz (A
V
= +3)
Large Signal Bandwidth: 150 MHz at 4 V p-p
Settling Time: 10 ns to 0.1%; 14 ns to 0.02%
Overdrive and Output Short Circuit Protected
Fast Overdrive Recovery
DC Nonlinearity 10 ppm
APPLICATIONS
Driving Flash Converters
D/A Current-to-Voltage Converters
IF, Radar Processors
Baseband and Video Communications
Photodiode, CCD Preamps
PIN CONFIGURATION
1
2
3
4
NC
*
AD9617
INPUT
+INPUT
V
S
+V
S
OUTPUT
**
NC = NO CONNECT
*
OPTIONAL +V
S
**
OPTIONAL V
S
NOTE:
FOR BEST SETTLING TIME AND DISTORTION
PERFORMANCE, USE OPTIONAL SUPPLY
CONNECTIONS. PERFORMANCE INDICATED
IN SPECIFICATIONS IS BASED ON SUPPLY
CONNECTIONS TO THESE PINS.
8
7
6
5
GENERAL DESCRIPTION
The AD9617 is a current feedback amplifier which utilizes a
proprietary architecture to produce superior distortion and dc
precision. It achieves this along with fast settling, very fast slew
rate, wide bandwidth (both small signal and large signal) and
exceptional signal fidelity. The device achieves 67 dBc 2nd
harmonic distortion at 20 MHz while maintaining 190 MHz
small signal and 150 MHz large signal bandwidths.
These attributes position the AD9617 as an ideal choice for
driving flash ADCs and buffering the latest generation of
DACs. Optimized for applications requiring gain between
1
to
15, the AD9617 is unity gain stable without external
compensation.
The AD9617 offers outstanding performance in high fidelity,
wide bandwidth applications in instrumentation ranging from
network and spectrum analyzers to oscilloscopes, and in military
systems such as radar, SIGINT and ESM systems. The superior
slew rate, low overshoot and fast settling of the AD9617 allow the
device to be used in pulse applications such as communications
receivers and high speed ATE. Most monolithic op amps suffer
in these precision pulse applications due to slew rate limiting.
The AD9617J operates over the range of 0
C to +70
C and is
available in either an 8-lead plastic DIP or an 8-1ead plastic
small outline package (SOIC).
2
REV. B
AD9617SPECIFICATIONS
DC ELECTRICAL CHARACTERISTICS
Test
AD9617JN/JR
AD9617AQ/SQ*
AD9617BQ/TQ*
Parameter
Conditions
Temp
Level
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
Units
Input Offset Voltage
1, 2
+25
C I
1.1
+0.5
+2.2
1.1
+0.5
+2.2
+0.0
+0.5
+1.35 mV
Input Offset Voltage TC
2
Full
IV
4
+3
+25
4
+3
+25
4
+3
+25
V/
C
Input Bias Current
2
Inverting
+25
C I
50
0
+50
50
0
+50
25
0
+25
A
Noninverting
+25
C I
25
+5
+35
25
+5
+35
15
+5
+20
A
Input Bias Current TC
2
Noninverting
Full
IV
50
+30
+125 50
+30
+125
50
+30
+125
nA/
C
Inverting
Full
IV
50
+50
+150 50
+50
+150
50
+50
+150
nA/
C
Input Resistance
Noninverting
+25
C V
60
60
60
k
Input Capacitance
Noninverting
+25
C V
1.5
1.5
1.5
pF
Common-Mode Input Range
3
T = T
MAX
II
1.4
1.5
1.4
1.5
1.4
1.5
V
T = T
MIN
to +25
C
II
1.7
1.8
1.7
1.8
1.7
1.8
V
Common-Mode Rejection Ratio
4
T = T
MIN
to T
MAX
II
44
48
44
48
44
48
dB
T = T
MIN
to +25
C
II
48
51
48
51
48
51
dB
Power Supply Rejection Ratio
V
S
=
5%
Full
II
48
51
48
51
48
51
dB
Open Loop Gain
T
O
At DC
+25
C V
500
500
500
k
Nonlinearity
At DC
+25
C IV
10
10
10
ppm
Output Voltage Range
+25
C II
3.4
3.8
3.4
3.8
3.4
+3.8
V
Output Impedance
At DC
+25
C V
0.07
0.07
0.07
Output Current (50
Load)
T = +25
C to T
MAX
II
60
60
60
mA
T = T
MIN
II
50
50
50
mA
NOTES
*Pending obsoletion: last-time buy October 25, 1999.
1
Measured with respect to the inverting input.
2
Typical is defined as the mean of the distribution.
3
Measured in voltage follower configuration.
4
Measured with V
IN
= +0.25 V.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltages (
V
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . .
Vs
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3 V
Continuous Output Current
2
. . . . . . . . . . . . . . . . . . . . . 70 mA
Operating Temperature Ranges
AD9617JN/JR . . . . . . . . . . . . . . . . . . . . . . . . 0
C to +70
C
Storage Temperature
AD9617JN/JR . . . . . . . . . . . . . . . . . . . . . 65
C to +125
C
Junction Temperature
3
AD9617JN/JR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
C
Lead Soldering Temperature (10 Seconds) . . . . . . . . . +300
C
NOTES
1
Absolute maximum ratings are limiting values to be applied individually and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Output is short circuit protected to ground, but not to supplies. Continuous
short circuit to ground may affect device reliability.
3
Typical thermal impedances (part soldered onto board):
Plastic DIP:
JA
= 140
C/W;
JC
= 30
C/W. SOIC Package:
JA
= 155
C/W;
JC
= 40
C/W.
(Unless otherwise noted, A
V
= +3; V
S
= 5 V; R
F
= 400
; R
LOAD
= 100
)
3
REV. B
AD9617
AC ELECTRICAL CHARACTERISTICS
Test
AD9617JN/JR
AD9617AQ/SQ*
AD9617BQ/TQ*
Parameter
Conditions
Temp
Level
Min
Typ
Max Min
Typ
Max
Min
Typ
Max
Units
FREQUENCY DOMAIN
Bandwidth (3 dB)
Small Signal
V
OUT
2 V p-p
Full
II
135
190
145
190
145
190
MHz
Large Signal
V
OUT
= 4 V p-p
Full
IV
150
115
150
115
150
MHz
Bandwidth Variation vs. A
V
A
V
= 1 to
15
+25
C V
40
40
40
MHz
Amplitude of Peaking (<50 MHz) T = T
MIN
to +25
C
II
0
0
0.3
0
0.3
dB
T = T
MAX
II
0
0
0.6
0
0.6
dB
Amplitude of Peaking (>50 MHz) T = T
MIN
to +25
C
II
0
0
0.8
0
0.8
dB
T = T
MAX
II
0
0
1.0
0
1.0
dB
Amplitude of Roll-Off (<60 MHz)
Full
II
0.1
0.1
0.6
0.1
0.6
dB
Phase Nonlinearity
DC to 75 MHz
+25
C V
0.5
0.5
0.5
Degree
2nd Harmonic Distortion
2 V p-p; 4.3 MHz
Full
IV
86
78
86
78
86
78
dBc
2 V p-p; 20 MHz
Full
IV
67
59
67
59
67
59
dBc
2 V p-p; 60 MHz
Full
II
51
43
51
43
51
43
dBc
3rd Harmonic Distortion
2 V p-p; 4.3 MHz
Full
IV
83
75
83
75
83
75
dBc
2 V p-p; 20 MHz
Full
IV
69
61
69
61
69
61
dBc
2 V p-p; 60 MHz
Full
II
54
46
54
46
54
46
dBc
Input Noise Voltage
10 MHz
+25
C V
1.2
1.2
1.2
nV/
Hz
Inverting Input Noise Current
10 MHz
+25
C V
29
29
29
pA/
Hz
Average Equivalent Integrated
Input Noise Voltage
0.1 MHz to 200 MHz +25
C V
55
55
55
V, rms
TIME DOMAIN
Slew Rate
V
OUT
= 4 V Step
Full
IV
1400
1100 1400
1100
1400
V/
s
Rise/Fall Time
V
OUT
= 2 V Step
Full
IV
2.0
2.0
2.5
2.0
2.5
ns
V
OUT
= 4 V Step
T = +25
C to T
MAX
IV
2.4
2.4
3.3
2.4
3.3
ns
V
OUT
= 4 V Step
T = T
MIN
IV
2.4
2.4
3.5
2.4
3.5
ns
Overshoot
V
OUT
= 2 V Step
Full
IV
3
3
14
3
14
%
Settling Time
To 0.1%
V
OUT
= 2 V Step
Full
IV
10
10
15
10
15
ns
To 0.02%
V
OUT
= 2 V Step
Full
IV
14
14
23
14
23
ns
To 0.1%
V
OUT
= 4 V Step
Full
IV
11
11
16
11
16
ns
To 0.02%
V
OUT
= 4 V Step
Full
IV
16
16
24
16
24
ns
2
Overdrive Recovery to
2 mV of Final Value
V
IN
= 1.7 V Step
+25
C V
50
50
50
ns
Propagation Delay
+25
C V
2
2
2
ns
Differential Gain
1
Full
V
<0. 01
<0. 01
<0 .01
%
Differential Phase
1
Full
V
0.01
0.01
0.01
Degree
POWER SUPPLY REQUIREMENTS
Quiescent Current
+I
S
Full
II
34
48
34
48
34
48
mA
I
S
Full
II
34
48
34
48
34
48
mA
NOTES
*Pending obsoletion: last-time buy October 25, 1999.
1
Frequency = 4.3 MHz; R
L
= 150
; A
V
= +3.
Specifications subject to change without notice.
(Unless otherwise noted, A
V
= +3; V
S
= 5 V; R
F
= 400
; R
LOAD
= 100
)
AD9617
4
REV. B
EXPLANATION OF TEST LEVELS
Test Level
I
- 100% production tested.
II - 100% production tested at +25
C and sample tested at
specified temperatures. AC testing of J grade devices done
on sample basis.
III - Sample tested only.
IV - Parameter is guaranteed by design and characterization
testing.
V - Parameter is a typical value only.
VI - All devices are 100% production tested at +25
C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD9617JN
0
C to +70
C
Plastic DIP
N-8
AD9617JR
0
C to +70
C
SOIC
SO-8
AD9617JR-REEL
0
C to +70
C
13" Tape and Reel
SO-8
DIE CONNECTIONS
+V
S
V
S
V
S
INPUT
+INPUT
+V
S
OUTPUT
TOP VIEW
(Not to Scale)
DIE SIZE = 53 67 15 mils
AD9617
5
REV. B
Typical Performance Characteristics
(A
V
= +3; V
S
= 5 V; R
F
= 400 V, unless otherwise noted)
FREQUENCY MHz
3
0
MAGNITUDE dB
40
80
120
160
200
2
1
0
1
2
3
4
5
6
7
45
0
45
90
135
180
90
135
180
A
V
= +5
A
V
= +1
A
V
= +20
PHASE Degrees
Figure 1. Noninverting Frequency Response
FREQUENCY MHz
3
0
MAGNITUDE dB
40
80
120
160
200
2
1
0
1
2
3
4
5
6
7
45
0
45
90
135
180
90
135
180
PHASE De
g
rees
A
V
= 5
A
V
= 1
A
V
= 20
Figure 2. Inverting Frequency Response
FREQUENCY Hz
120
10k
GAIN dB
100k
1M
10M
100M
1G
105
90
75
60
45
30
15
0
90
120
150
180
210
240
60
30
0
GAIN
PHASE
RELATIVE PHASE De
g
rees
100
TEST CIRCUIT
Figure 3. Open Loop Transimpedance Gain
[
T(s) Relative to 1
]
FREQUENCY Hz
10
100
dB
1k
10k
100k
1M
100M
15
20
25
30
35
40
45
50
55
60
CMRR
PSRR
10M
Figure 4. CMRR and PSRR
TIME s
0.1
0
SETTLING PERCENTAGE %
8
16
24
32
40
0.08
0.06
0.04
0.02
0
0.02
0.04
0.1
V
OUT
= 4V STEP
100
TEST CIRCUIT
6pF
0.06
0.08
Figure 5. Settling Time
TIME s
0.1
0
SETTLING PERCENTAGE %
2
4
6
8
10
0.08
0.06
0.04
0.02
0
0.02
0.04
0.1
V
OUT
= 4V STEP
100
TEST CIRCUIT
6pF
0.06
0.08
Figure 6. Long Term Settling Time
AD9617
6
REV. B
FREQUENCY MHz
40
0
dBc
2
4
6
10
50
60
70
80
100
100 LOAD
90
500 LOAD
20
40
60
100
V
OUT
= 2V p-p
= 2ND HARMONIC
= 3RD HARMONIC
8
Figure 7. Harmonic Distortion
FREQUENCY MHz
3
0
MAGNITUDE dB
40
80
120
160
200
2
1
0
1
2
3
4
5
6
7
45
0
45
90
135
180
90
135
180
R
L
= 500
PHASE De
g
rees
R
L
= 100
R
L
= 50
Figure 8. Frequency Response vs. R
LOAD
FREQUENCY MHz
115
100
pA/ Hz
1k
10k
100k
100
85
70
55
40
25
4
3
2
1
5
6
7
nV/ Hz
nV/ Hz
pA/ Hz
(INVERTING)
Figure 9. Equivalent Input Noise
FREQUENCY MHz
50
0
INTERCEPT +dBm
30
60
90
120
150
40
30
20
50
TEST
CIRCUIT
50
Figure 10. Intermodulation Distortion (IMD)
10ns/DIV
2.5
ANALOG INPUT Volts
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
2.5
A
V
= +3
A
V
= 3
100
TEST CIRCUIT
6pF
Figure 11. Large Signal Pulse Response
10ns/DIV
ANALOG INPUT Volts
1.0
0.5
0
0.5
1.0
A
V
= +3
A
V
= 3
100
TEST CIRCUIT
6pF
Figure 12. Small Signal Pulse Response
AD9617
7
REV. B
THEORY OF OPERATION
The AD9617 has been designed to combine the key attributes of
traditional "low frequency" precision amplifiers with exceptional
high frequency characteristics that are independent of closed-
loop gain. Previous "high frequency" closed-loop amplifiers have
low open loop gain relative to precision amplifiers. This results
in relatively poor dc nonlinearity and precision, as well as exces-
sive high frequency distortion due to open loop gain roll-off.
Operational amplifiers use two basic types of feedback correc-
tion, each with advantages and disadvantages. Voltage feedback
topologies exhibit an essentially constant gain bandwidth prod-
uct. This forces the closed-loop bandwidth to vary inversely with
closed-loop gain. Moreover, this type design typically slew rate
limits in a way that causes the large signal bandwidth to be
much lower than its small signal characteristics.
A newer approach is to use current feedback to realize better
dynamic performance. This architecture provides two key at-
tributes over voltage feedback configurations: (1) avoids slew
rate limiting and therefore large signal bandwidth can approach
small signal performance; and (2) low bandwidth variation ver-
sus gain settings, due to the inherently low open loop inverting
input resistance (R
S
).
The AD9617 uses a new current feedback topology that over-
comes these limitations and combines the positive attributes of
both current feedback and voltage feedback designs. These
devices achieve excellent high frequency dynamics (slew, BW
and distortion) along with excellent low frequency linearity and
good dc precision.
DC GAIN CHARACTERISTICS
A simplified equivalent schematic is shown below. When operat-
ing the device in the inverting mode, the input signal error
current (I
E
) is amplified by the open loop transimpedance gain
(T
O
). The output signal generated is equal to T
O
I
E
. Negative
feedback is applied through R
F
such that the device operates at a
gain (G) equal to R
F
/R
I
.
Noninverting operation is similar, with the input signal applied
to the high impedance buffer (noninverting) input. As before, an
output (buffer) error current (I
E
) is generated at the low imped-
ance inverting input. The signal generated at the output is fed
back to the inverting input such that the external gain is (l + R
F
/
R
I
). The feedback mechanics are identical to the voltage feed-
back topology when exact equations are used.
T
O
V
N
V
I
R
I
C
I
+
I
E
R
S
L
S
C
C
V
O
R
F
Figure 13. Equivalent Circuit
The major difference lies in the front end architecture. A voltage
feedback amplifier has symmetrical high resistance (buffered)
inputs. A current feedback amplifier has a high noninverting
resistance (buffered) input and a low inverting (buffer output)
input resistance. The feedback mechanics can be easily devel-
oped using current feedback and transresistance open loop gain
T(s) to describe the I/O relationship. (See typical specification
chart.)
DC closed-loop gain for the AD9617 can be calculated using
the following equations:
G
=
V
O
V
I
-
R
F
/ R
I
1
+
1 / LG
inverting
(1)
G
=
V
O
V
N
1
+
R
F
/ R
I
1
+
1 / LG
noninverting
(2)
where
1
LG
R
S
R
F
+
R
S
R
I
(
)
T s
( )
R
S
R
I
(
)
(3)
Because the noninverting input buffer is not ideal, input resis-
tance R
S
(at dc) is gain dependent and is typically higher for
noninverting operation than for inverting operation. R
S
will
approach the same value ( 7
) for both at input frequencies
above 50 MHz. Below the open loop corner frequency, the
noninverting R
S
can be approximated as:
R
S
noninverting
(
)
7
+
T s
( )
A
O
=
7
+
T
O
A
O dc
(4)
where: A
O
= Open Loop Voltage Gain G
600
Inverting R
S
below the open loop corner frequency can be ap-
proximated as:
R
S
inverting
(
)
7
+
T s
( )
A
O
=
7
+
T
O
A
O dc
(5)
where: A
O
= 40,000.
The AD9617 approaches this condition. With T
O
= 1
10
6
,
R
L
= 500
and R
S
= 25
(dc), a gain error no greater than
0.05% typically results for G = 1 and 0.15% for G = 40.
Moreover, the architecture linearizes the open loop gain over its
operating voltage range and temperature resulting in
16 bits of
linearity.
V
OUT
Volts
2
ERROR RELATIVE TO FS
0.0002%/DIVISION
0%
1
0
1
2
R
L
= 100
Figure 14. DC Nonlinearity vs. V
OUT
AD9617
8
REV. B
AC GAIN CHARACTERISTICS
Closed-loop bandwidth at high frequencies is determined pri-
marily by the roll-off of T(s). But circuit layout is critical to
minimize external parasitics which can degrade performance by
causing premature peaking and/or reduced bandwidth.
The inverting and noninverting dynamic characteristics are similar.
When driving the noninverting input, the inverting input capaci-
tance (C
I
) will cause the noninverting closed-loop bandwidth to
be higher than the inverting bandwidth for gains less than two
(2). In the remaining cases, inverting and noninverting responses
are nearly identical.
For best overall dynamic performance, the value of the feedback
resistor (R
F
) should be 400 ohms. Although bandwidth reduces
as closed-loop gain increases, the change is relatively small due
to low equivalent series input impedance, Z
S
. (See typical
performance charts.) The simplified equations governing the
device's dynamic performance are shown below.
Closed-Loop Gain vs. Frequency:
(noninverting operation)
V
O
V
I
1
+
R
F
R
I
s 1
+
R
S
R
I
+
1
(6)
where: = R
F
C
C
= 0.9 ns (R
F
= 400
)
Slew Rate
V
O
R
F
KC
C
e
-
/ R
F
KC
C
(7)
where:
K
=
1
+
R
S
R
I
Increasing Bandwidth at Low Gains
By reducing R
F
, wider bandwidth and faster pulse response can
be attained beyond the specified values, although increased
overshoot, settling time and possible ac peaking may result. As a
rule of thumb, overshoot and bandwidth will increase by 1%
and 8%, respectively, for a 5% reduction in R
F
at gains of
10.
Lower gains will increase these sensitivities.
Equations 6 and 7 are simplified and do not accurately model
the second order (open loop) frequency response term which is
the primary contributor to overshoot, peaking and nonlinear
bandwidth expansion. (See Open Loop Bode Plots.) The user
should exercise caution when selecting R
F
values much lower
than 400
. Note that a feedback resistor must be used in all
situations, including those in which the amplifier is used in a
noninverting unity gain configuration.
Increasing Bandwidth at High Gains
Closed loop bandwidth can be extended at high closed loop gain
by reducing R
F.
Bandwidth reduction is a result of the feedback
current being split between R
S
and R
I
. As the gain increases (for
a given R
F
), more feedback current is shunted through R
I
, which
reduces closed loop bandwidth (see Equation 6). To maintain
specified BW, the following equations can be used to approxi-
mate R
F
and R
I
for any gain from
l to
15.
R
F
= 424
8 G
(8)
(+ for inverting and for noninverting)
R
I
424
-
8 G
G
-
1
(noninverting)
(9)
R
I
424
+
8 G
G
-
1
(inverting)
(10)
G = Closed Loop Gain.
Bandwidth Reduction
The closed loop bandwidth can be reduced by increasing R
F.
Equations 6 and 7 can be used to determine the closed loop
bandwidth for any value R
F
. Do not connect a feedback capaci-
tor across R
F
, as this will degrade dynamic performance and
possibly induce oscillation.
DC Precision and Noise
Output offset voltage results from both input bias currents and
input offset voltage. These input errors are multiplied by the
noise gain term (1 + R
F
/R
I
) and algebraically summed at the
output as shown below.
V
O
=
V
IO
1
+
R
F
R
I
IBn
R
N
1
+
R
F
R
I
IBi
R
F
(11)
Since the inputs are asymmetrical, IBi and IBn do not correlate.
Canceling their output effects by making R
N
= R
F
R
I
will not
reduce output offset errors, as it would for voltage feedback
amplifiers. Typically, IBn is 5
A and V
IO
is +0.5 mV (I sigma =
0.3 mV), which means that the dc output error can be reduced
by making R
N
100
. Note that the offset drift will not change
significantly because the IBn TC is relatively small. (See specifi-
cation table.)
IBi
IBn
R
I
R
N
R
F
V
OUT
Figure 15. Output Offset Voltage
10
55 C
IBi/IBn
A
5
0
5
10
25 C
125 C
0
0.5
1.0
0.5
1.0
V
IO
mA
IBi
V
IO
IBn
Figure 16. DC Accuracy
AD9617
9
REV. B
The effective noise at the output of the amplifier can be deter-
mined by taking the root sum of the squares of Equation 11 and
applying the spectral noise values found in the typical graph
section. This applies to noise from the op amp only. Note that
both the noise figure and equivalent input offset voltages im-
prove as the closed loop gain is increased (by keeping R
F
fixed
and reducing R
I
with R
N
= 0
).
CLI
In
400
R
SERIES
R
L
500
CL
Figure 17. Capacitive Load Figure
Capacitive Load Considerations
Due to the low inverting input resistance (R
S
) and output buffer
design, the AD9617 can directly handle input and/or output
load capacitances of up to 20 pF. See the chart below.
A small series resistor can be used at the output of the amplifier
and outside of the feedback loop to facilitate driving larger ca-
pacitive loads or for obtaining faster settling time. For capacitive
loads above 20 pF, R
SERIES
should be considered.
INPUT CAPACITANCE CLI
5pF
4pF/DIV
25pF
INPUT CAPACITANCE CL
10pF
4pF/DIV
30pF
R
SERIES
= 0
35
30
25
20
15
10
V
OUT
= 4V STEP
CL = 0pF
SETTLING TIME TO 0.02% ns
V
OUT
= 4V STEP
CLI = 0pF
Figure 18. Input/Output Capacitance Comparisons
CL pF
25
0
R
SERIES
20
15
10
5
0
20
40
60
80
100
Figure 19. Recommended R
SERIES
vs. CL
APPLYING THE AD9617
The superior frequency and time domain specifications of the
AD9617 make it an obvious choice for driving flash converters
and buffering the outputs of high speed DACs. Its outstanding
distortion and noise performance make it well suited as a driver
for analog to digital converters (ADCs) with resolutions as high
as 16 bits.
Typical circuits for inverting and noninverting applications are
shown in Figures 20 and 21.
Closed-loop gain for noninverting configurations is determined
by the value of RI according to the equation:
G
=
1
+
R
F
R
I
(12)
0.1 F
0.1 F
0.1 F
0.1 F
3.3 F
3.3 F
V
S
+V
S
AD9617
V
OUT
400
R
IN
V
IN
R
I
Figure 20. Noninverting Operation
0.1 F
0.1 F
0.1 F
0.1 F
3.3 F
3.3 F
V
S
+V
S
AD9617
V
OUT
400
R
TERM
V
IN
R
I
Figure 21. Inverting Operation
AD9617
10
REV. B
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Small Outline Package
(SO-8)
8
5
4
1
0.198 (5.00)
0.188 (4.74)
0.244 (6.200)
0.228 (5.80)
PIN 1
0.158 (4.00)
0.150 (3.80)
0.050 (1.27)
BSC
0.069 (1.75)
0.053 (1.35)
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.018 (0.46)
0.014 (0.36)
0.015 (0.38)
0.007 (0.18)
0.045 (1.15)
0.020 (0.50)
8
0
0.205 (5.20)
0.181 (4.60)
Plastic DIP
(N-8)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.200 (5.05)
0.125 (3.18)
0.070 (1.77)
0.045 (1.15)
0.150
(3.81)
MIN
8
1
4
5
PIN 1
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
0.430 (10.92)
0.348 (8.84)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
0 15
LAYOUT CONSIDERATIONS
As with all high performance amplifiers, printed circuit layout is
critical in obtaining optimum results with the AD9617. The
ground plane in the area of the amplifier should cover as much
of the component side of the board as possible. Each power
supply trace should be decoupled close to the package with at
least a 3.3
F tantalum and a low inductance, 0.1
F ceramic
capacitor.
All lead lengths for input, output and the feedback resistor
should be kept as short as possible. All gain setting resistors
should be chosen for low values of parasitic capacitance and
inductance, i.e., microwave resistors and/or carbon resistors.
Stripline techniques should be used for lead lengths in excess of
one inch. Sockets should be avoided if possible because of their
stray inductance and capacitance.
C1353b09/99
PRINTED IN U.S.A.
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