REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD9630*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1999
Low Distortion 750 MHz
Closed-Loop Buffer Amp
PIN CONFIGURATION
1
2
3
4
8
7
6
5
NC = NO CONNECT
AD9630
***
NC
**
INPUT
+V
S
NC
V
S
OUTPUT
NOTE: FOR BEST SETTLING TIME PERFORMANCE USE
OPTIONAL POWER SUPPLIES. ALL SPECIFICATIONS
ARE BASED ON USING SINGLE V
S
CONNECTIONS,
EXCEPT FOR SETTLING TIME TO 0.02% AND SMALL
SIGNAL S21. CONSULT THE FACTORY FOR VERSIONS
WITH OPTIONAL POWER SUPPLY PINS DISCONNECTED
INTERNAL TO THE PACKAGE.
**OPTIONAL +V
S
***OPTIONAL V
S
FEATURES
Excellent Gain Accuracy: 0.99 V/V
Wide Bandwidth: 750 MHz
Slew Rate: 1200 V/ s
Low Distortion
65 dBc @ 20 MHz
80 dBc @ 4.3 MHz
Settling Time
5 ns to 0.1%
8 ns to 0.02%
Low Noise: 2.4 nV/
Hz
Improved Source for CLC-110
APPLICATIONS
IF/Communications
Impedance Transformations
Drives Flash ADCs
Line Driving
GENERAL DESCRIPTION
The AD9630 is a monolithic buffer amplifier that utilizes a
patented, innovative, closed-loop design technique to achieve
exceptional gain accuracy, wide bandwidth, and low distortion.
Slew rate limiting has been overcome as indicated by the
1200 V/
s slew rate; this improvement allows the user greater
flexibility in wideband and pulse applications. The second har-
monic distortion terms for an analog input tone of 4.3 MHz
and 20 MHz are 80 dBc and 66 dBc, respectively. Clearly,
the AD9630 establishes a new standard by combining out-
standing dc and dynamic performance in one part.
The large signal bandwidth, low distortion over frequency, and
drive capabilities of the AD9630 make the buffer an ideal flash
ADC driver. The AD9630 provides better signal fidelity than
many of the flash ADCs that it has been designed to drive.
Other applications that require increased current drive at unity
voltage gain (such as cable driving) benefit from the AD9630's
performance.
The AD9630 is available in plastic DIP (N) and SOIC (R).
*Protected under U.S. patent numbers 5,150,074 and 5,537,079.
2
REV. B
AD9630SPECIFICATIONS
Test
AD9630AN/AR
Parameter
Conditions
Temp
Level
Min
Typ
Max
Units
DC SPECIFICATIONS
Output Offset Voltage
+25
C
I
8
3
+8
mV
Offset Voltage TC
Full
IV
40
8
+40
V/
C
Input Bias Current
+25
C
I
25
2
+25
A
Bias Current TC
Full
IV
100
20
+100
nA/
C
Input Resistance
+25 to T
MAX
II
300
450
k
T
MIN
VI
150
250
k
Input Capacitance
+25
C
V
1.0
pF
Gain
V
OUT
= 2 V p-p
+25 to T
MAX
II
0.983
0.990
V/V
V
OUT
= 2 V p-p
T
MIN
VI
0.980
0.985
V/V
Output Voltage Range
Full
VI
+3.2
3.6
3.2
V
Output Current (50
Load)
+25 to T
MAX
II
50
mA
T
MIN
VI
40
mA
Output Impedance
At DC
+25
C
V
0.6
PSRR
V
S
=
5%
Full
VI
44
55
dB
DC Nonlinearity
2 V Full Scale
+25
C
V
0.03
%
FREQUENCY DOMAIN
Bandwidth (3 dB)
Small Signal
V
O
0.7 V p-p
T
MIN
to +25
II
400
750
MHz
V
O
0.7 V p-p
T
MAX
II
330
550
MHz
Large Signal
V
O
= 5 V p-p
T
MIN
to +25
V
120
MHz
V
O
= 5 V p-p
T
MAX
V
105
MHz
Output Peaking
200 MHz
Full
II
0.4
1.2
dB
Output Rolloff
200 MHz
Full
II
0
0.3
dB
Group Delay
DC to 150 MHz
+25
C
V
0.7
ns
Linear Phase Deviation
DC to 150 MHz
+25
C
V
0.7
Degrees
2nd Harmonic Distortion
2 V p-p; 4.3 MHz
Full
IV
80
73
dBc
2 V p-p; 20 MHz
Full
IV
66
58
dBc
2 V p-p; 50 MHz
Full
II
52
43
dBc
3rd Harmonic Distortion
2 V p-p; 4.3 MHz
Full
IV
86
79
dBc
2 V p-p; 20 MHz
Full
IV
75
68
dBc
2 V p-p; 50 MHz
T
MIN
to +25
II
47
41
dBc
2 V p-p; 50 MHz
T
MAX
II
46
40
dBc
Spectral Input Noise Voltage
10 MHz
+25
C
V
2.4
nV/
Hz
Integrated Output Noise
100 kHz 200 MHz
+25
C
V
32
V
TIME DOMAIN
Slew Rate
V
OUT
= 5 V Step
+25
C
IV
700
1200
V/
s
Rise/Fall Time
V
OUT
= 1 V Step
+25
C
IV
1.1
1.7
ns
V
OUT
= 1 V Step
T
MIN
to T
MAX
IV
1.3
1.9
ns
V
OUT
= 5 V Step
+25
C
IV
4.2
5.7
ns
V
OUT
= 5 V Step
T
MIN
to T
MAX
IV
5.0
6.5
ns
Overshoot Amplitude
V
OUT
= 2 V Step
Full
IV
2
12
%
Settling Time
To 0.1%
V
OUT
= 2 V Step
T
MIN
to +25
IV
6
10
ns
V
OUT
= 2 V Step
T
MAX
IV
7
12
ns
To 0.02%
4
V
OUT
= 2 V Step
T
MIN
to +25
IV
8
ns
V
OUT
= 2 V Step
T
MAX
V
12
ns
Differential Gain
4.4 MHz
+25
C
V
0.015
%
Differential Phase
4.4 MHz
+25
C
V
0.025
Degree
SUPPLY CURRENTS
V
CC
(+I
S
)
V
CC
= +5 V
Full
II
19
26
mA
V
EE
(I
S
)
V
EE
= 5 V
Full
II
19
26
mA
NOTES
1
Short-term settling with 50
source impedance.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
(unless otherwise noted, V
S
= 5 V; R
IN
= 50
, R
LOAD
= 100 )
AD9630
3
REV. B
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltages (
V
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 V
Continuous Output Current
2
. . . . . . . . . . . . . . . . . . . . . 70 mA
Temperature Range over Which Specifications Apply
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . 40
C to +85
C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . +300
C
Storage Temperature
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . 65
C to +150
C
Junction Temperature
3
AD9630AN/AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150
C
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Output is short-circuit protected to ground, but not to supplies. Prolonged short
circuit to ground may affect device reliability.
3
Typical thermal impedances (part soldered onto board): Plastic DIP (N):
JA
=
110
C/W;
JC
= 30
C/W; SOIC (R):
JA
= 155
C/W;
JC
= 40
C/W.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD9630AN
40
C to +85
C 8-Lead Plastic DIP N-8
AD9630AR
40
C to +85
C 8-Lead SOIC
SO-8
AD9630AR-REEL 40
C to +85
C 13
" Tape and Reel SO-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9630 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
EXPLANATION OF TEST LEVELS
Test Level
I
100% Production tested.
II
100% Production tested at +25
C and sample tested at
specified temperatures. AC testing of AN and AR grades
done on sample basis only.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V
Typical value.
VI S Versions are 100% production tested at temperature
extremes. Other grades are sample tested at extremes.
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
NC = NO CONNECT
AD9630
NC
NC
NC
NC
100
(5%, 0.25W)
24
(5%, 0.25W)
+5V
5.2V
0.1 F
0.1 F
AD9630 Burn-In Circuit
THEORY OF OPERATION
The AD9630 is a wide-bandwidth, closed-loop, unity-gain
buffer that makes use of a new voltage-feedback architecture.
This architecture brings together wide bandwidth and high slew
rate along with exceptional dc linearity. Most previous wide-
bandwidth buffers achieved their bandwidth by utilizing an
open-loop topology which sacrificed both dc linearity and fre-
quency distortion when driven into low load impedances. The
design's high loop correction factor radically improves dc lin-
earity and distortion characteristics without diminishing
bandwidth. This, in combination with high slew rate, results in
exceptionally low distortion over a wide frequency range.
The AD9630 is an excellent choice to drive high speed and high
resolution analog-to-digital converters. Its output stage is de-
signed to drive high speed flash converters with minimal or no
series resistance. A current booster built into the output driver
helps to maintain low distortion.
Parasitic or load capacitance (>7 pF) connected directly to the
AD9630 output will result in frequency peaking. A small series
resistor (R
S
) connected between the buffer output and capaci-
tive load will negate this effect. Figure 1 shows the optimal value
of R
S
as a function of C
L
to obtain the flattest frequency re-
sponse. Figure 2 illustrates frequency response for various
capacitive loads utilizing the recommended R
S
.
C
L
pF
50
40
0
0
100
20
R
SERIES
40
60
80
30
20
10
7
R
S
C
L
200
"R"
NO
R
S
NEEDED
WHEN
C
L
<
7pF;
FOR
C
L
>
30pF,
"R"
CAN
BE
OMITTED
Figure 1. Recommended R
S
vs. C
L
WARNING!
ESD SENSITIVE DEVICE
AD9630
4
REV. B
In pulse mode applications, with R
S
equal to approximately
12
, capacitive loads of up to 50 pF can be driven with mini-
mal settling time degradation.
The output stage has short circuit protection to ground. The
output driver will shut down if more than approximately
130 mA of instantaneous sink or source current is reached. This
level of current ensures that output clipping will not result when
driving heavy capacitive loads during high slew conditions,
although average load currents above 70 mA may reduce device
reliability.
LAYOUT CONSIDERATIONS
Due to the high frequency operation of the AD9630 attention to
board layout is necessary to achieve optimum dynamic perfor-
mance. A two ounce copper ground plane on the top side of the
board is recommended; it should cover as much of the board as
possible with appropriate openings for supply decoupling ca-
pacitors as well as for load and source termination resistors, (see
Figure 3).
Optimum settling time and ac performance results will be
achieved with surface mount 0.1
F supply decoupling ceramic
chip capacitors mounted within 50 mils of the corresponding
device pins with the other side soldered directly to the ground
plane. For best high resolution (<0.02%) settling times, the op-
tional power supply pins should be decoupled as shown above.
If the optional power supply pins are not used, they should be
left open.
If surface mount capacitors cannot be used, radial lead ceramic
capacitors with leads less than 30 mils long are recommended.
Low frequency power supply decoupling is necessary and can be
accomplished with 4.7
F tantalum capacitors mounted within
0.5 inches of the supply pins. Due to the series inductance of
these capacitors interacting with the 0.1
F capacitors and
power supply leads, high frequency oscillations might appear on
C
L
2
<0.1MHz
FREQUENCY RESPONSE dB
1
0
1
2
3
4
5
6
7
8
100MHz
200MHz
300MHz
10pF
25pF
50pF
Figure 2. Frequency Response vs. C
L
with Recommended R
S
the device output. To avoid this occurrence, the power supply
leads should be tightly twisted (if appropriate). Ferrite beads
mounted between the tantalum and ceramic capacitors will
serve the same purpose.
All unused pins (except the optional power supply pins) should
be connected to ground to reduce pin-to-pin capacitive coupling
and prevent external RF interference. If the source and drive
electronics require "remote" operation (> 1 inch from the
AD9630), the PC board line impedances should be matched
with the buffer input and output resistances. Basic microstrip
techniques should be observed. R
IN
and R
S
should be connected
as close to the AD9630 as possible.
With only minimal pulse overshoot and ringing, the AD9630
can drive terminated cables directly without the use of an output
termination resistor (R
S
). Termination resistors (R
S
and R
IN
)
can be either standard carbon composition or microwave type.
For matching characteristic impedances, precision microwave
resistors of 1% or better tolerance are preferred.
The AD9630 should be soldered directly to the PC board with
as little vertical clearance as possible. The use of zero insertion
sockets is strongly discouraged because of the high effective pin
inductances. Use of this type socket will result in peaking and
possibly induce oscillation.
8
1
6
AD9630
0.1 F
5
2
*
*
4.7 F
0.1 F
0.1 F
0.1 F
4.7 F
V
S
R
IN
V
IN
V
OUT
+V
S
R
S
**
*SEE PINOUTS
**SEE FIGURE 1
Figure 3. AD9630 Application Circuit
AD9630
5
REV. B
Typical Performance Curves
VOLTS
ppm
0
1000
3
2
3
1
0
1
2
100
600
700
800
900
200
300
500
400
R
L
= 100
R
L
= 200
Figure 4. Endpoint DC Linearity
FREQUENCY Hz
50
0
1M
10M
1G
100M
10
20
40
PSRR dB
30
Figure 7. PSRR vs. Frequency
PHASE
GAIN
V
IN
= 100mV
V
IN
= 750mV
V
IN
= 100mV
FREQUENCY Hz
MAGNITUDE dB
2
5
8
0M
1G
200M
400M
600M
800M
1
4
6
7
2
3
0
1
0
45
90
135
180
PHASE Degrees
Figure 10 . Forward Gain and Phase
FREQUENCY Hz
1M
100k
1
1M
1k
100
10
10k
10M
100M
1G
Figure 5. Input Impedance
INTERCEPT +dBm
FREQUENCY MHz
50
0
dc
250
50
100
150
200
20
10
30
40
50
50
TEST
CIRCUIT
Figure 8. 2-Tone Intermodulation
Distortion
FREQUENCY MHz
MAGNITUDE dB
3
4
7
0
200
R
L
= 50
R
L
= 100
R
L
= 200
40
80
120
160
2
3
5
6
1
2
1
0
Figure 11. Frequency Response vs.
R
LOAD
|Zo|
FREQUENCY Hz
30
25
0
1M
10M
1G
100M
15
10
5
20
PHASE Degrees
100
80
40
20
0
60
|Zo|
Figure 6. Output Impedance
CASE TEMPERATURE C
10
10
2
4
6
8
55
25
125
OFFSET VOLTAGE mV
50
40
50
10
20
30
40
20
0
10
30
BIAS CURRENT
A
8
4
0
2
6
BIAS CURRENT
OFFSET VOLTAGE
Figure 9. Offset Voltage and Bias
Current vs. Temperature
Figure 12. Small-Signal Pulse
Response
2ns/DIVISION
VOLTS
0.25
50
6pF
50
TEST CIRCUIT
0.5
0.5
0
0.25
AD9630
6
REV. B
0.04
0.1
0.08
0
0.04
0.08
0.06
0.02
0.02
0.06
0.1
10
20
30
40
50
TIME ns
100
6pF
TEST CIRCUIT
SETTLING PERCENTAGE %
V
OUT
= 2V STEP
Figure 13. Short-Term Settling Time
dBc
FREQUENCY MHz
40
50
100
1
10
100
70
80
90
60
R
L
= 100
2nd
3rd
Figure 16. Harmonic Distortion
V
OUT
= 4 V p-p
SETTLING PERCENTAGE %
0.04
0.1
0.08
0
0.04
0.08
0.06
0.02
0.02
0.06
0.1
10
100
1k
10k
100k
TIME ns
V
OUT
= 2V STEP
1
100
6pF
TEST CIRCUIT
Figure 14. Long-Term Settling Time
dBc
FREQUENCY MHz
40
50
100
1
10
R
L
= 100
100
70
80
90
60
2nd
3rd
Figure 17. Harmonic Distortion
V
OUT
= 2 V p-p
0.5
5ns/DIVISION
VOLTS
50
6pF
50
TEST CIRCUIT
3.0
0
1.5
2.5
2.0
1.0
0.5
1.0
1.5
2.0
2.5
3.0
Figure 15. Large-Signal Pulse
Response
AD9630
7
REV. B
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
8
1
4
5
PIN 1
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
0.430 (10.92)
0.348 (8.84)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
8-Lead SOIC
(SO-8)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
45
8
5
4
1
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
C1401a012/99 (rev. B)
PRINTED IN U.S.A.
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