Document Outline
- Specifications
- Pinout
- OUTLINE DIMENSIONS
- Ordering Guide
- Features
- Applications
- Product Description
- Absolute Maximum Ratings
- Functional Block Diagram
- Pin Function Description
- Typical Characteristics
- THERMAL CHARACTERISTICS
- CAUTION
- REFERENCE OPERATION
- REFERENCE CONTROL AMPLIFIER
- DAC TRANSFER FUNCTION
- DIGITAL INPUTS
- POWER DISSIPATION
- DAC TIMING
- DIFFERENTIAL COUPLING USING A TRANSFORMER
- DIFFERENTIAL COUPLING USING AN OP AMP
- APPLYING THE AD9740
- POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION
- SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
- SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION
- EVALUATION BOARD
- DIAGRAMS
- Timing Diagram
- Basic AC Characterization Test Setup
- Simplified Block Diagram
- Internal Reference Configuration
- External Reference Configuration
- Equivalent Digital Input
- Differential Output Using a Transformer
- DC Differential Coupling Using an Op Amp
- Single-Supply DC Differential Coupled Circuit
- 0 V to 0.5 V Unbuffered Voltage Output
- Unipolar Buffered Voltage Output
- Differential LC Filter for Single 3.3 V Applications
- Evaluation Board: Power Supply and Digital Inputs
- Evaluation Board: Output Signal Conditioning
- Primary Side
- Secondary Side
- Ground Plane
- Power Plane
- Assembly Primary Side
- Assembly Secondary Side
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD9740
*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
10-Bit, 165 MSPS
TxDAC
D/A Converter
FUNCTIONAL BLOCK DIAGRAM
150pF
+1.20V REF
AVDD
ACOM
REFLO
CURRENT
SOURCE
ARRAY
3.3V
SEGMENTED
SWITCHES
LSB
SWITCH
REFIO
FS ADJ
DVDD
DCOM
CLOCK
3.3V
R
SET
0.1 F
CLOCK
IOUTA
IOUTB
LATCHES
AD9740
SLEEP
DIGITAL DATA INPUTS (DB9DB0)
MODE
FEATURES
High-Performance Member of Pin-Compatible
TxDAC Product Family
Excellent Spurious-Free Dynamic Range Performance
SNR @ 5 MHz Output, 125 MSPS: 65 dB
Two's Complement or Straight Binary Data Format
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 135 mW @ 3.3 V
Power-Down Mode: 15 mW @ 3.3 V
On-Chip 1.20 V Reference
CMOS-Compatible Digital Interface
Package: 28-Lead SOIC and TSSOP Packages
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Base Stations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9740 is a 10-bit resolution, wideband, third generation
member of the TxDAC series of high-performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communica-
tion systems. All of the devices share the same interface options,
small outline package, and pinout, providing an upward or down-
ward component selection path based on performance, resolution,
and cost. The AD9740 offers exceptional ac and dc performance
while supporting update rates up to 165 MSPS.
The AD9740's low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can be
further reduced to a mere 60 mW with a slight degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance. Edge-
triggered input latches and a 1.2 V temperature compensated
band gap reference have been integrated to provide a complete
monolithic DAC solution. The digital inputs support 3 V CMOS
logic families.
PRODUCT HIGHLIGHTS
1. The AD9740 is the 10-bit member of the pin-compatible
TxDAC family that offers excellent INL and DNL
performance.
2. Data input supports two's complement or straight binary
data coding.
3. High-speed, single-ended CMOS clock input supports
165 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on
135 mW from a 3.0 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation, and
a sleep mode is provided for low power idle periods.
5. On-chip voltage reference: The AD9740 includes a 1.2 V
temperature-compensated band gap voltage reference.
6. Industry standard 28-lead SOIC and TSSOP packages.
TxDAC is a registered trademark of Analog Devices, Inc.
* Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
REV. 0
2
AD9740
DC SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
RESOLUTION
10
Bits
DC ACCURACY
1
Integral Linearity Error (INL)
0.7
0.15
+0.7
LSB
Differential Nonlinearity (DNL)
0.5
0.12
+0.5
LSB
ANALOG OUTPUT
Offset Error
0.02
+0.02
% of FSR
Gain Error (Without Internal Reference)
2
0.1
+2
% of FSR
Gain Error (With Internal Reference)
2
0.1
+2
% of FSR
Full-Scale Output Current
2
2.0
20.0
mA
Output Compliance Range
1.0
+1.25
V
Output Resistance
100
k
Output Capacitance
5
pF
REFERENCE OUTPUT
Reference Voltage
1.14
1.20
1.26
V
Reference Output Current
3
100
nA
REFERENCE INPUT
Input Compliance Range
0.1
1.25
V
Reference Input Resistance (Ext. Ref)
1
M
Small Signal Bandwidth
0.5
MHz
TEMPERATURE COEFFICIENTS
Offset Drift
0
ppm of FSR/
C
Gain Drift (Without Internal Reference)
50
ppm of FSR/
C
Gain Drift (With Internal Reference)
100
ppm of FSR/
C
Reference Voltage Drift
50
ppm/
C
POWER SUPPLY
Supply Voltages
AVDD
2.7
3.3
3.6
V
DVDD
2.7
3.3
3.6
V
Analog Supply Current (I
AVDD
)
33
36
mA
Digital Supply Current (I
DVDD
)
4
8
9
mA
Supply Current Sleep Mode (I
AVDD
)
5
6
mA
Power Dissipation
4
135
145
mW
Power Dissipation
5
145
mW
Power Supply Rejection Ratio--AVDD
6
1
+1
% of FSR/V
Power Supply Rejection Ratio--DVDD
6
0.04
+0.04
% of FSR/V
OPERATING RANGE
40
+85
C
NOTES
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32 times the I
REF
current.
3
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at f
CLOCK
= 25 MSPS and f
OUT
= 1.0 MHz.
5
Measured as unbuffered voltage output with I
OUTFS
= 20 mA and 50
R
LOAD
at IOUTA and IOUTB, f
CLOCK
= 100 MSPS and f
OUT
= 40 MHz.
6
5% power supply variation.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.)
REV. 0
3
AD9740
DYNAMIC SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
CLOCK
)
165
MSPS
Output Settling Time (t
ST
) (to 0.1%)
1
11
ns
Output Propagation Delay (t
PD
)
1
ns
Glitch Impulse
5
pV-s
Output Rise Time (10% to 90%)
1
2.5
ns
Output Fall Time (10% to 90%)
1
2.5
ns
Output Noise (I
OUTFS
= 20 mA)
2
50
pA/
Hz
Output Noise (I
OUTFS
= 2 mA)
2
30
pA/
Hz
Noise Spectral Density
3
143
dBm/Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
0 dBFS Output
71
79
dBc
6 dBFS Output
75
dBc
12 dBFS Output
67
dBc
18 dBFS Output
61
dBc
f
CLOCK
= 65 MSPS; f
OUT
= 1.00 MHz
84
dBc
f
CLOCK
= 65 MSPS; f
OUT
= 2.51 MHz
80
dBc
f
CLOCK
= 65 MSPS; f
OUT
= 10 MHz
78
dBc
f
CLOCK
= 65 MSPS; f
OUT
= 15 MHz
76
dBc
f
CLOCK
= 65 MSPS; f
OUT
= 25 MHz
75
dBc
f
CLOCK
= 165 MSPS; f
OUT
= 21 MHz
70
dBc
f
CLOCK
= 165 MSPS; f
OUT
= 41 MHz
60
dBc
Spurious-Free Dynamic Range within a Window
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz; 2 MHz Span
80
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz; 2 MHz Span
90
dBc
f
CLOCK
= 65 MSPS; f
OUT
= 5.03 MHz; 2.5 MHz Span
90
dBc
f
CLOCK
= 125 MSPS; f
OUT
= 5.04 MHz; 4 MHz Span
90
dBc
Total Harmonic Distortion
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
79
71
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 2.00 MHz
77
dBc
f
CLOCK
= 65 MSPS; f
OUT
= 2.00 MHz
77
dBc
f
CLOCK
= 125 MSPS; f
OUT
= 2.00 MHz
77
dBc
Signal-to-Noise Ratio
f
CLOCK
= 65 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 20 mA
70
dB
f
CLOCK
= 65 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 5 mA
81
dB
f
CLOCK
= 125 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 20 mA
65
dB
f
CLOCK
= 125 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 5 mA
76
dB
f
CLOCK
= 165 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 20 mA
64
dB
f
CLOCK
= 165 MSPS; f
OUT
= 5 MHz; I
OUTFS
= 5 mA
71
dB
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
f
CLOCK
= 78 MSPS; f
OUT
= 15.0 MHz to 18.2 MHz
0 dBFS Output
65
dBc
6 dBFS Output
66
dBc
12 dBFS Output
60
dBc
18 dBFS Output
55
dBc
NOTES
1
Measured single-ended into 50
load.
2
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3
Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, I
OUTFS
= 20 mA, Differential Transformer Coupled
Output, 50
Doubly terminated, unless otherwise noted.)
REV. 0
4
AD9740
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Options
*
AD9740AR
40
C to +85C 28-Lead 300 Mil SOIC R-28
AD9740ARU 40
C to +85C 28-Lead TSSOP
RU-28
AD9740-EB
Evaluation Board
*R = Small Outline IC; RU = Thin Shrink Small Outline Package
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300-Mil SOIC
JA
= 71.4
C/W
28-Lead TSSOP
JA
= 97.9
C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9740 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
With
Parameter
Respect to
Min
Max
Unit
AVDD
ACOM
0.3
+3.9
V
DVDD
DCOM
0.3
+3.9
V
ACOM
DCOM
0.3
+0.3
V
AVDD
DVDD
3.9
+3.9
V
CLOCK, SLEEP
DCOM
0.3
DVDD + 0.3 V
Digital Inputs
DCOM
0.3
DVDD + 0.3 V
IOUTA, IOUTB
ACOM
1.0
AVDD + 0.3
V
REFIO, REFLO, FSADJ
ACOM
0.3
AVDD + 0.3
V
Junction Temperature
150
C
Storage Temperature
65
+150
C
Lead Temperature (10 sec)
300
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
DIGITAL SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic "1" Voltage
2.1
3
V
Logic "0" Voltage
0
0.9
V
Logic "1" Current
10
+10
A
Logic "0" Current
10
+10
A
Input Capacitance
5
pF
Input Setup Time (t
S
)
2.0
ns
Input Hold Time (t
H
)
1.5
ns
Latch Pulsewidth (t
LPW
)
1.5
ns
(T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.)
0.1%
0.1%
t
S
t
H
t
LPW
t
PD
t
ST
DB0DB11
CLOCK
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
REV. 0
AD9740
5
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9740
NC = NO CONNECT
(MSB) DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
(LSB) DB0
NC
NC
NC
NC
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
DB1
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
DB9
Most Significant Data Bit (MSB)
29
DB8DB1
Data Bits 81
10
DB0
Least Significant Data Bit (LSB)
1114
NC
No Internal Connection
15
SLEEP
Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used.
16
REFLO
Reference Ground when internal 1.2 V reference used. Connect to AVDD to disable internal reference.
17
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD).
Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to AGND). Requires
0.1
F capacitor to AGND when internal reference activated.
18
FS ADJ
Full-Scale Current Output Adjust
19
NC
No Internal Connection
20
ACOM
Analog Common
21
IOUTB
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22
IOUTA
DAC Current Output. Full-scale current when all data bits are 1s.
23
RESERVED
Reserved. Do Not Connect to Common or Supply.
24
AVDD
Analog Supply Voltage (3.3 V)
25
MODE
Selects Input Data Format. Connect to DGND for straight binary, DVDD for two's complement.
26
DCOM
Digital Common
27
DVDD
Digital Supply Voltage (3.3 V)
28
CLOCK
Clock Input. Data latched on positive edge of clock.
REV. 0
AD9740
6
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight line
drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25
C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per
C. For reference drift, the drift is reported in
ppm per
C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies are
varied from nominal to minimum and maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It is measured as the difference
between the rms amplitude of a carrier tone to the peak spurious
signal in the region of a removed tone.
1.20V REF
AVDD
ACOM
REFLO
PMOS
CURRENT SOURCE
ARRAY
3.3V
SEGMENTED SWITCHES
FOR DB9DB1
LSB
SWITCH
REFIO
FS ADJ
DVDD
DCOM
CLOCK
3.3V
R
SET
2k
0.1 F
DVDD
DCOM
IOUTA
IOUTB
AD9740
SLEEP
50
RETIMED
CLOCK
OUTPUT*
LATCHES
DIGITAL
DATA
TEKTRONIX
AWG-2021
W/OPTION 4
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
50
20pF
50
20pF
100
ROHDE & SCHWARZ
FSEA30
SPECTRUM
ANALYZER
MINI-CIRCUITS
T11T
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
150pF
MODE
Figure 2. Basic AC Characterization Test Setup
REV. 0
7
Typical Performance CharacteristicsAD9740
f
OUT
MHz
SFDR dBc
45
1
10
100
65MSPS
125MSPS
165MSPS
50
55
60
65
70
75
80
85
90
95
TPC 1. SFDR vs. f
OUT
@ 0 dBFS
0
60
10
45
50
55
60
65
70
75
80
85
90
95
f
OUT
MHz
SFDR dBc
40
30
20
50
12dBFS
6dBFS
0dBFS
TPC 4. SFDR vs. f
OUT
@ 165 MSPS
20
15
25
10
5
0
45
55
65
75
85
95
A
OUT
MHz
SFDR dBc
165MSPS
125MSPS
65MSPS
TPC 7. Single-Tone SFDR vs. A
OUT
@ f
OUT
= f
CLOCK
/5
0
5
25
10
15
20
45
50
55
60
65
70
75
80
85
90
95
f
OUT
MHz
SFDR dBc
12dBFS
6dBFS
0dBFS
TPC 2. SFDR vs. f
OUT
@ 65 MSPS
0
5
25
10
15
20
45
50
55
60
65
70
75
80
85
90
95
20mA
10mA
5mA
f
OUT
MHz
SFDR dBc
TPC 5. SFDR vs. f
OUT
and I
OUTFS
@ 65 MSPS and 0 dBFS
90
110
70
130
150
170
60
65
70
75
85
90
20mA
f
CLOCK
MSPS
SNR dB
10mA
5mA
50
80
TPC 8. SNR vs. f
CLOCK
and
I
OUTFS
@ f
OUT
= 5 MHz and 0 dBFS
0
5
45
10
15
35
45
50
55
60
65
70
75
80
85
90
95
0dBFS
6dBFS
12dBFS
f
OUT
MHz
SFDR dBc
40
30
20
25
TPC 3. SFDR vs. f
OUT
@ 125 MSPS
0
5
25
10
15
20
45
55
65
75
85
95
A
OUT
dBFS
SFDR dBc
165MSPS
125MSPS
65MSPS
TPC 6. Single-Tone SFDR vs.
A
OUT
@ f
OUT
= f
CLOCK
/11
45
50
55
60
65
70
75
80
85
90
95
A
OUT
dBFS
SFDR dBc
0
5
10
15
20
25
78MSPS
165MSPS
125MSPS
65MSPS
TPC 9. Dual-Tone IMD vs. A
OUT
@ f
OUT
= f
CLOCK
/7
REV. 0
AD9740
8
40
20
60
0
20
40
50
55
60
65
70
75
80
85
90
4MHz
19MHz
34MHz
TEMPERATURE C
SFDR dBc
80
49MHz
TPC 12. SFDR vs. Temperature @
165 MSPS, 0 dBFS
1
6
26
11
16
21
100
FREQUENCY MHz
MA
GNITUDE dBm
31
f
CLOCK
= 78MSPS
f
OUT1
= 15.0MHz
f
OUT2
= 15.4MHz
f
OUT3
= 15.8MHz
f
OUT4
= 16.2MHz
SFDR = 72dBc
AMPLITUDE = 0dBFS
36
90
80
70
60
50
40
20
0
10
30
TPC 15. Four-Tone SFDR
0
256
512
768
1024
0.25
0.15
0.05
0.05
0.15
0.25
CODE
ERR
OR LSB
TPC 10. Typical INL
1
6
26
11
16
21
100
FREQUENCY MHz
MA
GNITUDE dBm
31
f
CLOCK
= 78MSPS
f
OUT
= 15.0MHz
SFDR = 77dBc
AMPLITUDE = 0dBFS
36
90
80
70
60
50
40
20
0
10
30
TPC 13. Single-Tone SFDR
0
256
512
768
1024
0.25
0.15
0.05
0.05
0.15
0.25
CODE
ERR
OR LSB
TPC 11. Typical DNL
1
6
26
11
16
21
100
FREQUENCY MHz
MA
GNITUDE dBm
31
f
CLOCK
= 78MSPS
f
OUT1
= 15.0MHz
f
OUT2
= 15.4MHz
SFDR = 77dBc
AMPLITUDE = 0dBFS
36
90
80
70
60
50
40
20
0
10
30
TPC 14. Dual-Tone SFDR
REV. 0
AD9740
9
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9740. The
AD9740 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (I
OUTFS
). The array is divided into 31 equal currents
that make up the 5 most significant bits (MSBs). The next 4 bits,
or middle bits, consist of 15 equal current sources whose value
is 1/16th of an MSB current source. The remaining LSBs are
binary weighted fractions of the middle bits current sources.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance for
multitone or low amplitude signals and helps maintain the DAC's
high output impedance (i.e., >100 k
).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces vari-
ous timing errors and provides matching complementary drive
signals to the inputs of the differential current switches.
The analog and digital sections of the AD9740 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.0 V to 3.6 V range. The digital section,
which is capable of operating up to a 165 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.2 V band gap
voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the refer-
ence control amplifier and can be set from 2 mA to 20 mA via
an external resistor, R
SET
, connected to the full-scale adjust
(FSADJ) pin. The external resistor, in combination with both
the reference control amplifier and voltage reference, V
REFIO
,
sets the reference current I
REF
, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, I
OUTFS
, is 32 times I
REF
.
REFERENCE OPERATION
The AD9740 contains an internal 1.2 V band gap reference.
The internal reference can be disabled by raising REFLO to
AVDD. It can also be easily overridden by an external reference
with no effect on performance. REFIO serves as either an input
or output depending on whether the internal or an external
reference is used. To use the internal reference, simply decouple
the REFIO pin to ACOM with a 0.1
F capacitor and connect
REFLO to ACOM via a resistance less than 5
. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used anywhere else in the circuit, an external
buffer amplifier with an input bias current of less than 100 nA
should be used. An example of the use of the internal reference
is given in Figure 4.
150pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
3.3V
REFIO
FS ADJ
2k
0.1 F
AD9740
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
Figure 4. Internal Reference Configuration
An external reference can be applied to REFIO as shown in Figure 5.
The external reference may provide either a fixed reference voltage
to enhance accuracy and drift performance or a varying reference
voltage for gain control. Note that the 0.1
F compensation capaci-
tor is not required since the internal reference is overridden, and
the relatively high input impedance of REFIO minimizes any
loading of the external reference.
150pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
REFIO
FS ADJ
R
SET
AD9740
EXTERNAL
REF
I
REF
=
V
REFIO
/R
SET
AVDD
REFERENCE
CONTROL
AMPLIFIER
V
REFIO
3.3V
Figure 5. External Reference Configuration
DIGITAL DATA INPUTS (DB9DB0)
150pF
+1.20V REF
AVDD
ACOM
REFLO
PMOS
CURRENT SOURCE
ARRAY
3.3V
SEGMENTED SWITCHES
FOR DB9DB1
LSB
SWITCH
REFIO
FS ADJ
DVDD
DCOM
CLOCK
3.3V
R
SET
2k
0.1 F
IOUTA
IOUTB
AD9740
SLEEP
LATCHES
I
REF
V
REFIO
CLOCK
IOUTB
IOUTA
R
LOAD
50
V
OUTB
V
OUTA
R
LOAD
50
V
DIFF
= V
OUTA
V
OUTB
MODE
Figure 3. Simplified Block Diagram
REV. 0
AD9740
10
REFERENCE CONTROL AMPLIFIER
The AD9740 contains a control amplifier that is used to regu-
late the full-scale output current, I
OUTFS
. The control amplifier
is configured as a V-I converter as shown in Figure 4, so that its
current output, I
REF
, is determined by the ratio of the V
REFIO
and an external resistor, R
SET
, as stated in Equation 4. I
REF
is
copied to the segmented current sources with the proper scale
factor to set I
OUTFS
as stated in Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
I
OUTFS
over a 2 mA to 20 mA range by setting I
REF
between
62.5
A and 625 A. The wide adjustment span of I
OUTFS
provides several benefits. The first relates directly to the power
dissipation of the AD9740, which is proportional to I
OUTFS
(refer to the Power Dissipation section). The second relates
to the 20 dB adjustment, which is useful for system gain
control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low-frequency small
signal multiplying applications.
DAC TRANSFER FUNCTION
Both DACs in the AD9740 provide complementary current
outputs, IOUTA and IOUTB. IOUTA will provide a near full-
scale current output, I
OUTFS
, when all bits are high (i.e., DAC
CODE = 1023) while IOUTB, the complementary output,
provides no current. The current output appearing at IOUTA
and IOUTB is a function of both the input code and I
OUTFS
and
can be expressed as:
IOUTA
DAC CODE
I
OUTFS
=
(
/
)
1024
(1)
IOUTB
DAC CODE
I
OUTFS
=
(
) /
1023
1024
(2)
where DAC CODE = 0 to 1023 (i.e., decimal representation).
As mentioned previously, I
OUTFS
is a function of the reference
current I
REF
, which is nominally set by a reference voltage,
V
REFIO
, and external resistor, R
SET
. It can be expressed as:
I
I
OUTFS
REF
=
32
(3)
where
I
V
R
REF
REFIO
SET
=
/
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
LOAD
, that are tied to analog common, ACOM. Note,
R
LOAD
may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50
or 75 cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply:
V
IOUTA
R
OUTA
LOAD
=
(5)
V
IOUTB
R
OUTB
LOAD
=
(6)
Note the full-scale value of V
OUTA
and V
OUTB
should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
V
IOUTA
IOUTB
R
DIFF
LOAD
=
(
)
(7)
Substituting the values of IOUTA, IOUTB, I
REF
, and V
DIFF
can
be expressed as:
V
DAC CODE
R
R
V
DIFF
LOAD
SET
REFIO
=
{
}
(
)
(
) /
/
2
1023
1024
32
(8)
These last two equations highlight some of the advantages of
operating the AD9740 differentially. First, the differential
operation will help cancel common-mode error sources associ-
ated with IOUTA and IOUTB, such as noise, distortion, and dc
offsets. Second, the differential code dependent current and
subsequent voltage, V
DIFF
, is twice the value of the single-ended
voltage output (i.e., V
OUTA
or V
OUTB
), thus providing twice the
signal power to the load.
Note, the gain drift temperature performance for a single-ended
(V
OUTA
and V
OUTB
) or differential output (V
DIFF
) of the AD9740
can be enhanced by selecting temperature tracking resistors for
R
LOAD
and R
SET
due to their ratiometric relationship as shown in
Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA and
IOUTB, may be configured for single-ended or differential opera-
tion. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, V
OUTA
and V
OUTB
, via a load resis-
tor, R
LOAD
, as described in the DAC Transfer Function section by
Equations 5 through 8. The differential voltage, V
DIFF
, existing
between V
OUTA
and V
OUTB
can also be converted to a single-ended
voltage via a transformer or differential amplifier configuration.
The ac performance of the AD9740 is optimum and specified
using a differential transformer coupled output in which the voltage
swing at IOUTA and IOUTB is limited to
0.5 V.
The distortion and noise performance of the AD9740 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi-
cant as the frequency content of the reconstructed waveform
increases and/or its amplitude decreases. This is due to the first
order cancellation of various dynamic common-mode distortion
mechanisms, digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a trans-
former also provides the ability to deliver twice the reconstructed
signal power to the load (i.e., assuming no source termination).
Since the output currents of IOUTA and IOUTB are comple-
mentary, they become additive when processed differentially. A
properly selected transformer will allow the AD9740 to provide
the required power and voltage levels to different loads.
The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 k
in
parallel with 5 pF. It is also slightly dependent on the output
voltage (i.e., V
OUTA
and V
OUTB
) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration will result in
the optimum dc linearity. Note the INL/DNL specifications
for the AD9740 are measured with IOUTA maintained at a
virtual ground via an op amp.
REV. 0
AD9740
11
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range of
1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the AD9740.
The positive output compliance range is slightly dependent on the
full-scale output current, I
OUTFS
. It degrades slightly from its
nominal 1.2 V for an I
OUTFS
= 20 mA to 1.0 V for an I
OUTFS
= 2 mA.
The optimum distortion performance for a single-ended or differ-
ential output is achieved when the maximum full-scale signal at
IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9740's digital section consists of 10 input bit channels
and a clock input. The 10-bit parallel data inputs follow stan-
dard positive binary coding where DB13 is the most significant
bit (MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
DVDD
DIGITAL
INPUT
Figure 6. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
165 MSPS. The clock can be operated at any duty cycle that meets
the specified latch pulsewidth. The setup and hold times can also
be varied within the clock cycle as long as the specified minimum
times are met, although the location of these transition edges
may affect digital feedthrough and distortion performance. Best
performance is typically achieved when the input data transitions
on the falling edge of a 50% duty cycle clock.
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relation-
ship between the position of the clock edges and the point in
time at which the input data changes. The AD9740 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9740 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases. Figure 7 shows the relationship of SFDR
to clock placement with different sample rates. Note that at the
lower sample rates, more tolerance is allowed in clock place-
ment, while at higher rates, more care must be taken.
3
2
2
1
0
1
70
80
TIME (ns) OF DATA CHANGE RELATIVE
TO RISING CLOCK EDGE
SFDR dBc
3
60
50
40
65
75
55
45
f
OUT
= 50MHz
f
OUT
= 20MHz
Figure 7. SFDR vs. Clock Placement @ f
OUT
= 20 MHz and
50 MHz
Sleep Mode Operation
The AD9740 has a power-down function that turns off the output
current and reduces the supply current to less than 4 mA over the
specified supply range of 3.0 V to 3.6 V and temperature range.
This mode can be activated by applying a logic level 1 to the SLEEP
pin. The SLEEP pin logic threshold is equal to 0.5
AVDD. This
digital input also contains an active pull-down circuit that ensures
the AD9740 remains enabled if this input is left disconnected.
The AD9740 takes less than 50 ns to power down and approximately
5
s to power back up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9740 is dependent on
several factors that include:
The power supply voltages (AVDD and DVDD)
The full-scale current output I
OUTFS
The update rate f
CLOCK
The reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, I
AVDD
, and the digital supply current, I
DVDD
.
I
AVDD
is directly proportional to I
OUTFS
as shown in Figure 8
and is insensitive to f
CLOCK
. Conversely, I
DVDD
is dependent on
both the digital input waveform, f
CLOCK
, and digital supply
DVDD. Figure 9 shows I
DVDD
as a function of full-scale sine
wave output ratios (f
OUT
/f
CLOCK
) for various update rates with
DVDD = 3.3 V.
REV. 0
AD9740
12
I
OUTFS
mA
35
0
2
I
AV
D
D
mA
30
25
20
15
10
4
6
8
10
12
14
16
18
20
Figure 8. I
AVDD
vs. I
OUTFS
RATIO
f
OUT
/
f
CLOCK
16
0.01
1
0.1
I
DV
D
D
mA
14
12
10
8
6
4
2
0
165MSPS
125MSPS
65MSPS
Figure 9. I
DVDD
vs. Ratio @ DVDD = 3.3 V
APPLYING THE AD9740
Output Configurations
The following sections illustrate some typical output configurations
for the AD9740. Unless otherwise noted, it is assumed that I
OUTFS
is
set to a nominal 20 mA. For applications requiring the optimum
dynamic performance, a differential output configuration is
suggested. A differential output configuration may consist of either
an RF transformer or a differential op amp configuration. The
transformer configuration provides the optimum high-frequency
performance and is recommended for any application that allows ac
coupling. The differential op amp configuration is suitable for
applications requiring dc coupling, a bipolar output, signal gain,
and/or level shifting, within the bandwidth of the chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, R
LOAD
, referred to ACOM. This configuration
may be more suitable for a single-supply system requiring a
dc-coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus converting
IOUTA or IOUTB into a negative unipolar voltage. This
configuration provides the best dc linearity since IOUTA or
IOUTB is maintained at a virtual ground.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-to-single-
ended signal conversion as shown in Figure 10. A differentially
coupled transformer output provides the optimum distortion
performance for output signals whose spectral content lies within
the transformer's pass band. An RF transformer, such as the Mini-
Circuits T11T, provides excellent rejection of common-mode
distortion (i.e., even-order harmonics) and noise over a wide
frequency range. It also provides electrical isolation and the ability
to deliver twice the power to the load. Transformers with different
impedance ratios may also be used for impedance matching
purposes. Note that the transformer provides ac coupling only.
R
LOAD
AD9740
MINI-CIRCUITS
T11T
OPTIONAL R
DIFF
IOUTA
IOUTB
Figure 10. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path for
both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (i.e., V
OUTA
and V
OUTB
) swing symmetri-
cally around ACOM and should be maintained with the specified
output compliance range of the AD9740. A differential resistor,
R
DIFF
, may be inserted in applications where the output of the
transformer is connected to the load, R
LOAD
, via a passive recon-
struction filter or cable. R
DIFF
is determined by the transformer's
impedance ratio and provides the proper source termination that
results in a low VSWR. Note that approximately half the signal
power will be dissipated across R
DIFF
.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single-ended
conversion as shown in Figure 11. The AD9740 is configured with
two equal load resistors, R
LOAD
, of 25
. The differential voltage
developed across IOUTA and IOUTB is converted to a single-
ended signal via the differential op amp configuration. An optional
capacitor can be installed across IOUTA and IOUTB, forming a
real pole in a low-pass filter. The addition of this capacitor also
enhances the op amp's distortion performance by preventing the
DACs high slewing output from overloading the op amp's input.
AD9740
IOUTA
IOUTB
C
OPT
500
225
225
500
25
25
AD8047
Figure 11. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential
op amp circuit using the AD8047 is configured to provide some
additional signal gain. The op amp must operate off of a dual
supply since its output is approximately
1.0 V. A high-speed
amplifier capable of preserving the differential performance of the
REV. 0
AD9740
13
AD9740 while meeting other system level objectives (i.e., cost,
power) should be selected. The op amp's differential gain, its gain
setting resistor values, and full-scale output swing capabilities
should all be considered when optimizing this circuit.
The differential circuit shown in Figure 12 provides the necessary
level shifting required in a single-supply system. In this case,
AVDD, which is the positive analog supply for both the AD9740
and the op amp, is also used to level shift the differential output
of the AD9740 to midsupply (i.e., AVDD/2). The AD8041 is a
suitable op amp for this application.
AD9740
IOUTA
IOUTB
C
OPT
500
225
225
1k
25
25
AD8041
1k
AVDD
Figure 12. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 13 shows the AD9740 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly termi-
nated 50
cable, since the nominal full-scale current, I
OUTFS
,
of 20 mA flows through the equivalent R
LOAD
of 25
. In this
case, R
LOAD
represents the equivalent load resistance seen by
IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching R
LOAD
.
Different values of I
OUTFS
and R
LOAD
can be selected as long as
the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL) as
discussed in the Analog Output section of this data sheet. For
optimum INL performance, the single-ended, buffered voltage
output configuration is suggested.
AD9740
IOUTA
IOUTB
50
25
50
V
OUTA
= 0V TO 0.5V
I
OUTFS
= 20mA
Figure 13. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 14 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9740
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, minimizing the nonlinear output impedance effect on the
DAC's INL performance as discussed in the Analog Output
section. Although this single-ended configuration typically
provides the best dc linearity performance, its ac distortion
performance at higher DAC update rates may be limited by
U1's slew rate capabilities. U1 provides a negative unipolar output
voltage and its full-scale output voltage is simply the product of R
FB
and I
OUTFS
. The full-scale output should be set within U1's
voltage output swing capabilities by scaling I
OUTFS
and/or R
FB
.
An improvement in ac distortion performance may result with a
reduced I
OUTFS
since U1 will be required to sink less signal current.
AD9740
IOUTA
IOUTB
C
OPT
200
U1
V
OUT
= I
OUTFS
R
FB
I
OUTFS
= 10mA
R
FB
200
Figure 14. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS,
POWER SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit board
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as power
supply bypassing and grounding to ensure optimum performance.
Figures 19 to 22 illustrate the recommended printed circuit board
ground, power, and signal plane layouts that are implemented on
the AD9740 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC's full-scale current, I
OUTFS
. AC noise on the dc supplies is
common in applications where the power distribution is gener-
ated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR vs frequency of the AD9740 AVDD
supply over this frequency range is shown in Figure 15.
FREQUENCY MHz
85
40
12
6
0
PSRR dB
80
75
70
65
60
55
50
2
4
8
10
45
Figure 15. Power Supply Rejection Ratio
Note that the units in Figure 15 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of
modulating the internal switches, and therefore the output current.
The voltage noise on AVDD, therefore, will be added in a
nonlinear manner to the desired IOUT. Due to the relative differ-
ent size of these switches, PSRR is very code dependent. This
can produce a mixing effect that can modulate low-frequency
power supply noise to higher frequencies. Worst-case PSRR for
either one of the differential DAC outputs will occur when the
REV. 0
AD9740
14
full-scale current is directed toward that output. As a result, the
PSRR measurement in Figure 15 represents a worst-case condition
in which the digital inputs remain static and the full-scale output
current of 20 mA is directed to the DAC output being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity
sake (i.e., ignore harmonics), all of this noise is concentrated at
250 kHz. To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC's full-scale
current, I
OUTFS
, one must determine the PSRR in dB using
Figure 15 at 250 kHz. To calculate the PSRR for a given R
LOAD
,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 15 by the scaling factor 20
log(R
LOAD
).
For instance, if R
LOAD
is 50
, the PSRR is reduced by 34 dB (i.e.,
PSRR of the DAC at 250 kHz which is 85 dB in Figure 15 becomes
51 dB V
OUT
/V
IN
).
Proper grounding and decoupling should be a primary objective
in any high-speed, high resolution system. The AD9740 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a system.
In general, AVDD, the analog supply, should be decoupled to
ACOM, the analog common, as close to the chip as physically
possible. Similarly, DVDD, the digital supply, should be decoupled
to DCOM as close to the chip as physically possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 16. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
100 F
ELECT.
0.1 F
CER.
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER SUPPLY
FERRITE
BEADS
AVDD
ACOM
10 F22 F
TANT.
Figure 16. Differential LC Filter for Single 3.3 V Applications
EVALUATION BOARD
General Description
The TxDAC family evaluation board allows for easy set up and
testing of any TxDAC product in the 28-lead SOIC package.
Careful attention to layout and circuit design combined with a
prototyping area allow the user to evaluate the AD9740 easily
and effectively in any application where high resolution, high-speed
conversion is required.
This board allows the user the flexibility to operate the AD9740
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, and single and differ-
ential outputs. The digital inputs are designed to be driven from
various word generators, with the on-board option to add a
resistor network for proper load termination. Provisions are also
made to operate the AD9740 with either the internal or external
reference or to exercise the power-down feature.
REV. 0
AD9740
15
2
R1
3
R2
4
R3
5
R4
6
R5
7
R6
8
R7
9
R8
10
R9
RP5
50
1
RCOM
16
1 RP3
22
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
15
2 RP3
22
14
3 RP3
22
13
4 RP3
22
12
5 RP3
22
11
6 RP3
22
10
7 RP3
22
9
8 RP3
22
16
1 RP4
22
15
2 RP4
22
14
3 RP4
22
13
4 RP4
22
12
5 RP4
22
11
6 RP4
22
9
8 RP4
22
10
7 RP4
22
CKEXT
CKEXTX
2
R1
3
R2
4
R3
5
R4
6
R5
7
R6
8
R7
9
R8
10
R9
RP6
50
1
RCOM
2
R1
3
R2
4
R3
5
R4
6
R5
7
R6
8
R7
9
R8
10
R9
RP1
50
1
RCOM
2
R1
3
R2
4
R3
5
R4
6
R5
7
R6
8
R7
9
R8
10
R9
RP2
50
1
RCOM
2
1
DB13X
4
3
DB12X
6
5
DB11X
8
7
DB10X
10
9
DB9X
12
11
DB8X
14
13
DB7X
16
15
DB6X
18
17
DB5X
20
19
DB4X
22
21
DB3X
24
23
DB2X
26
25
DB1X
28
27
DB0X
30
29
32
31
34
33
CKEXTX
36
35
38
37
40
39
JP3
J1
RIBBON
TB1 1
TB1 2
L2
10 H
C7
0.1 F
TP4
BLK
+
DVDD
TP7
C6
0.1 F
C4
10 F
25V
BLK
BLK
TP8
TP2
RED
TB1 3
TB1 4
L3
10 H
C9
0.1 F
TP6
BLK
+
AVDD
TP10
C8
0.1 F
C5
10 F
25V
BLK
BLK
TP9
TP5
RED
Figure 17. Evaluation Board: Power Supply and Digital Inputs
REV. 0
AD9740
16
R6
OPT
S2
IOUTA
2
A
B
JP10
1
3
IX
R11
50
C13
10pF
JP8
IOUT
S3
4
5
6
3
2
1
T1
T1-1T
JP9
C12
10pF
R10
50
S1
IOUTB
1
2
3
A
B
JP11
IY
1
EXT
2
3
INT
A
B
JP5
REF
+
+
C14
10 F
16V
C16
0.1 F
C17
0.1 F
AVDD
DVDD
CKEXT
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD
C15
10 F
16V
C18
0.1 F
C19
0.1 F
CUT
UNDER DUT
JP6
JP4
R5
10k
DVDD
R4
50
CLOCK
S5
CLOCK
TP1
WHT
DVDD
AVDD
DVDD
R2
10k
JP2
MODE
TP3
WHT
REF
C2
0.1 F
C1
0.1 F
C11
0.1 F
R1
2k
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
U1
AD9740
SLEEP
TP11
WHT
R3
10k
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD
Figure 18. Evaluation Board: Output Signal Conditioning
REV. 0
AD9740
17
Figure 19. Primary Side
Figure 20. Secondary Side
REV. 0
AD9740
18
Figure 21. Ground Plane
Figure 22. Power Plane
REV. 0
AD9740
19
Figure 23. Assembly Primary Side
Figure 24. Assembly Secondary Side
REV. 0
20
C0291105/02(0)
PRINTED IN U.S.A.
AD9740
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
28-Lead Standard Small Outline Package (SOIC)
(R-28)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
45
0.7125 (18.10)
0.6969 (17.70)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
28
15
14
1
28-Lead Thin Shrink SO Package (TSSOP)
(RU-28)
28
15
14
1
0.386 (9.80)
0.378 (9.60)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
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