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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD9750*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
10-Bit, 125 MSPS High Performance
TxDAC
D/A Converter
FUNCTIONAL BLOCK DIAGRAM
150pF
+1.20V REF
AVDD
ACOM
REFLO
ICOMP
CURRENT
SOURCE
ARRAY
+5V
SEGMENTED
SWITCHES
LSB
SWITCH
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
R
SET
0.1 F
CLOCK
IOUTA
IOUTB
0.1 F
LATCHES
AD9750
SLEEP
DIGITAL DATA INPUTS (DB9DB0)
FEATURES
High Performance Member of Pin-Compatible
TxDAC Product Family
125 MSPS Update Rate
10-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 76 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 190 mW @ 5 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
CMOS-Compatible +2.7 V to +5.5 V Digital Interface
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Basestations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
The AD9750 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a 1.2 V temperature compensated bandgap reference have
been integrated to provide a complete monolithic DAC solution.
The digital inputs support +2.7 V and +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and
5703519. Other patents pending.
The AD9750 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 k
output impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9750 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9750 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9750 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9750 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9750 is a member of the wideband TxDAC
high per-
formance product family that provides an upward or downward
component selection path based on resolution (8 to 14 bits),
performance and cost. The entire family of TxDACs is avail-
able in industry standard pinouts.
2. Manufactured on a CMOS process, the AD9750 uses a
proprietary switching technique that enhances dynamic
performance beyond that previously attainable by higher
power/cost bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches interface to
+2.7 V to +5 V CMOS logic families. The AD9750 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of +4.5 V to +5.5 V,
and a wide full-scale current adjustment span of 2 mA to
20 mA, allows the AD9750 to operate at reduced power levels.
5. The current output(s) of the AD9750 can be easily config-
ured for various single-ended or differential circuit topologies.
PRODUCT DESCRIPTION
The AD9750 is a 10-bit resolution, wideband, second generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog-converters (DACs). The TxDAC
family,
which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs,
is specifically optimized for the transmit signal path of commu-
nication systems. All of the devices share the same interface
options, small outline package and pinout, thus providing an up-
ward or downward component selection path based on perfor-
mance, resolution and cost. The AD9750 offers exceptional ac and
dc performance while supporting update rates up to 125 MSPS.
The AD9750's flexible single-supply operating range of 4.5 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 65 mW, without a significant degradation in
performance, by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
apprixmatley 20 mW.
AD9750SPECIFICATIONS
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DC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
RESOLUTION
10
Bits
DC ACCURACY
1
Integral Linearity Error (INL)
1.0
0.1
+1.0
LSB
Differential Nonlinearity (DNL)
0.5
0.1
+0.5
LSB
ANALOG OUTPUT
Offset Error
0.02
+0.02
% of FSR
Gain Error
(Without Internal Reference)
2
0.5
+2
% of FSR
Gain Error
(With Internal Reference)
5
1.5
+5
% of FSR
Full-Scale Output Current
2
2.0
20.0
mA
Output Compliance Range
1.0
1.25
V
Output Resistance
100
k
Output Capacitance
5
pF
REFERENCE OUTPUT
Reference Voltage
1.14
1.20
1.26
V
Reference Output Current
3
100
nA
REFERENCE INPUT
Input Compliance Range
0.1
1.25
V
Reference Input Resistance
1
M
Small Signal Bandwidth
0.5
MHz
TEMPERATURE COEFFICIENTS
Offset Drift
0
ppm of FSR/
C
Gain Drift
(Without Internal Reference)
50
ppm of FSR/
C
Gain Drift
(With Internal Reference)
100
ppm of FSR/
C
Reference Voltage Drift
50
ppm/
C
POWER SUPPLY
Supply Voltages
AVDD
4.5
5.0
5.5
V
DVDD
2.7
5.0
5.5
V
Analog Supply Current (I
AVDD
)
4
33
39
mA
Digital Supply Current (I
DVDD
)
5
5.0
7
mA
Supply Current Sleep Mode (I
AVDD
)
6
4.0
8
mA
Power Dissipation
5
(5 V, I
OUTFS
= 20 mA)
190
230
mW
Power Supply Rejection Ratio
7
--AVDD
0.4
+0.4
% of FSR/V
Power Supply Rejection Ratio
7
--DVDD
0.025
+0.025
% of FSR/V
OPERATING RANGE
40
+85
C
NOTES
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32
the I
REF
current.
3
Use an external buffer amplifier to drive any external load.
4
Requires +5 V supply.
5
Measured at f
CLOCK
= 50 MSPS and I
OUT
= static full scale (20 mA).
6
Logic level for SLEEP pin must be referenced to AVDD. Min V
IH
= 3.5 V.
7
5% Power supply variation.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, unless otherwise noted)
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AD9750
DYNAMIC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
CLOCK
)
125
MSPS
Output Settling Time (t
ST
) (to 0.1%)
1
35
ns
Output Propagation Delay (t
PD
)
1
ns
Glitch Impulse
5
pV-s
Output Rise Time (10% to 90%)
1
2.5
ns
Output Fall Time (10% to 90%)
1
2.5
ns
Output Noise (I
OUTFS
= 20 mA)
50
pA/
Hz
Output Noise (I
OUTFS
= 2 mA)
30
pA/
Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz
0 dBFS Output
T
A
= +25
C
71
82
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 2.51 MHz
79
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz
76
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 20.2 MHz
60
dBc
f
CLOCK
= 100 MSPS; f
OUT
= 2.51 MHz
78
dBc
f
CLOCK
= 100 MSPS; f
OUT
= 5.04 MHz
77
dBc
f
CLOCK
= 100 MSPS; f
OUT
= 20.2 MHz
69
dBc
f
CLOCK
= 100 MSPS; f
OUT
= 40.4 MHz
63
dBc
Spurious-Free Dynamic Range within a Window
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz
80
87
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz; 2 MHz Span
86
dBc
f
CLOCK
= 100 MSPS; f
OUT
= 5.04 MHz; 4 MHz Span
86
dBc
Total Harmonic Distortion
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz
T
A
= +25
C
80
dBc
f
CLOCK
= 50 MHz; f
OUT
= 2.00 MHz
76
dBc
f
CLOCK
= 100 MHz; f
OUT
= 2.00 MHz
76
dBc
NOTES
1
Measured single ended into 50
load.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, Differential Transformer Coupled Output,
50
Doubly Terminated, unless otherwise noted)
AD9750
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DIGITAL SPECIFICATIONS
Parameter
Min
Typ
Max
Units
DIGITAL INPUTS
Logic "1" Voltage @ DVDD = +5 V
1
3.5
5
V
Logic "1" Voltage @ DVDD = +3 V
2.1
3
V
Logic "0" Voltage @ DVDD = +5 V
1
0
1.3
V
Logic "0" Voltage @ DVDD = +3 V
0
0.9
V
Logic "1" Current
10
+10
A
Logic "0" Current
10
+10
A
Input Capacitance
5
pF
Input Setup Time (t
S
)
2.0
ns
Input Hold Time (t
H
)
1.5
ns
Latch Pulsewidth (t
LPW
)
3.5
ns
NOTES
1
When DVDD = +5 V, and Logic 1 voltage
3.5 V and Logic 0 voltage
1.3 V, IVDD can increase by up to 10 mA depending on f
CLOCK
.
Specifications subject to change without notice.
0.1%
0.1%
t
S
t
H
t
LPW
t
PD
t
ST
DB0DB11
CLOCK
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
With
Parameter
Respect to
Min
Max
Units
AVDD
ACOM
0.3
+6.5
V
DVDD
DCOM
0.3
+6.5
V
ACOM
DCOM
0.3
+0.3
V
AVDD
DVDD
6.5
+6.5
V
CLOCK, SLEEP
DCOM
0.3
DVDD + 0.3
V
Digital Inputs
DCOM
0.3
DVDD + 0.3
V
IOUTA, IOUTB
ACOM
1.0
AVDD + 0.3
V
ICOMP
ACOM
0.3
AVDD + 0.3
V
REFIO, FSADJ
ACOM
0.3
AVDD + 0.3
V
REFLO
ACOM
0.3
+0.3
V
Junction Temperature
+150
C
Storage Temperature
65
+150
C
Lead Temperature
(10 sec)
+300
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
ORDERING GUIDE
Temperature
Package
Package
Model
Ranges
Descriptions
Options*
AD9750AR
40
C to +85
C 28-Lead 300 Mil SOIC R-28
AD9750ARU 40
C to +85
C 28-Lead TSSOP
RU-28
AD9750-EB
Evaluation Board
*R = Small Outline IC; RU = Thin Shrink Small Outline Package.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 Mil SOIC
JA
= 71.4
C/W
JC
= 23
C/W
28-Lead TSSOP
JA
= 97.9
C/W
JC
= 14.0
C/W
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA unless otherwise noted)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9750 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD9750
5
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PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9750
NC = NO CONNECT
(MSB) DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
NC
NC
CLOCK
DVDD
DCOM
NC
AVDD
ICOMP
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1
DB9
Most Significant Data Bit (MSB).
29
DB8DB1
Data Bits 18.
10
DB0
Least Significant Data Bit (LSB).
1114, 19, 25
NC
No Internal Connection.
15
SLEEP
Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated
if not used.
16
REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.
17
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO
to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to
ACOM). Requires 0.1
F capacitor to ACOM when internal reference activated.
18
FS ADJ
Full-Scale Current Output Adjust.
20
ACOM
Analog Common.
21
IOUTB
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22
IOUTA
DAC Current Output. Full-scale current when all data bits are 1s.
23
ICOMP
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1
F capacitor.
24
AVDD
Analog Supply Voltage (+4.5 V to +5.5 V).
26
DCOM
Digital Common.
27
DVDD
Digital Supply Voltage (+2.7 V to +5.5 V).
28
CLOCK
Clock Input. Data latched on positive edge of clock.
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