REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD9752*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
12-Bit, 125 MSPS High Performance
TxDAC
D/A Converter
FUNCTIONAL BLOCK DIAGRAM
150pF
+1.20V REF
AVDD
ACOM
REFLO
ICOMP
CURRENT
SOURCE
ARRAY
+5V
SEGMENTED
SWITCHES
LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
R
SET
0.1 F
CLOCK
IOUTA
IOUTB
0.1 F
LATCHES
AD9752
SLEEP
DIGITAL DATA INPUTS (DB11DB0)
FEATURES
High Performance Member of Pin-Compatible
TxDAC Product Family
125 MSPS Update Rate
12-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 79 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 185 mW @ 5 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
CMOS-Compatible +2.7 V to +5.5 V Digital Interface
Package: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Basestations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9752 is a 12-bit resolution, wideband, second generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog-converters (DACs). The TxDAC
family,
which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communica-
tion systems. All of the devices share the same interface options,
small outline package and pinout, thus providing an upward or
downward component selection path based on performance,
resolution and cost. The AD9752 offers exceptional ac and dc
performance while supporting update rates up to 125 MSPS.
The AD9752's flexible single-supply operating range of 4.5 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 65 mW, without a significant degradation in
performance, by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 20 mW.
The AD9752 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a 1.2 V temperature compensated bandgap reference have
been integrated to provide a complete monolithic DAC solution.
The digital inputs support +2.7 V to +5 V CMOS logic families.
The AD9752 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 k
output impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9752 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9752 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9752 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9752 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9752 is a member of the wideband TxDAC
product
family that provides an upward or downward component selec-
tion path based on resolution (8 to 14 bits), performance and
cost. The entire family of TxDACs is available in industry
standard pinouts.
2. Manufactured on a CMOS process, the AD9752 uses a
proprietary switching technique that enhances dynamic
performance beyond that previously attainable by higher
power/cost bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches interface readily
to +2.7 V to +5 V CMOS logic families. The AD9752 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 4.5 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9752 to operate at reduced power levels.
5. The current output(s) of the AD9752 can be easily config-
ured for various single-ended or differential circuit topologies.
TxDAC is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and
5703519. Other patents pending.
2
AD9752SPECIFICATIONS
REV. 0
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, unless otherwise noted)
DC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
RESOLUTION
12
Bits
DC ACCURACY
1
Integral Linearity Error (INL)
T
A
= +25
C
1.5
0.5
+1.5
LSB
T
MIN
to T
MAX
2.0
+2.0
LSB
Differential Nonlinearity (DNL)
T
A
= +25
C
0.75
0.25
+0.75
LSB
T
MIN
to T
MAX
1.0
+1.0
LSB
ANALOG OUTPUT
Offset Error
0.02
+0.02
% of FSR
Gain Error
(Without Internal Reference)
2
0.5
+2
% of FSR
Gain Error
(With Internal Reference)
5
1.5
+5
% of FSR
Full-Scale Output Current
2
2.0
20.0
mA
Output Compliance Range
1.0
1.25
V
Output Resistance
100
k
Output Capacitance
5
pF
REFERENCE OUTPUT
Reference Voltage
1.14
1.20
1.26
V
Reference Output Current
3
100
nA
REFERENCE INPUT
Input Compliance Range
0.1
1.25
V
Reference Input Resistance
1
M
Small Signal Bandwidth
0.5
MHz
TEMPERATURE COEFFICIENTS
Offset Drift
0
ppm of FSR/
C
Gain Drift
(Without Internal Reference)
50
ppm of FSR/
C
Gain Drift
(With Internal Reference)
100
ppm of FSR/
C
Reference Voltage Drift
50
ppm/
C
POWER SUPPLY
Supply Voltages
AVDD
4.5
5.0
5.5
V
DVDD
2.7
5.0
5.5
V
Analog Supply Current (I
AVDD
)
4
34
39
mA
Digital Supply Current (I
DVDD
)
5
3
5
mA
Supply Current Sleep Mode (I
AVDD
)
6
4
8
mA
Power Dissipation
5
(5 V, I
OUTFS
= 20 mA)
185
220
mW
Power Supply Rejection Ratio
7
--AVDD
0.4
+0.4
% of FSR/V
Power Supply Rejection Ratio
7
--DVDD
0.025
+0.025
% of FSR/V
OPERATING RANGE
40
+85
C
NOTES
1
Measured at IOUTA, driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32
the I
REF
current.
3
Use an external buffer amplifier to drive any external load.
4
Requires +5 V supply.
5
Measured at f
CLOCK
= 25 MSPS and I
OUT
= static full scale (20 mA).
6
Logic level for SLEEP pin must be referenced to AVDD. Min V
IH
= 3.5 V.
7
5% Power supply variation.
Specifications subject to change without notice.
REV. 0
3
AD9752
DYNAMIC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
CLOCK
)
125
MSPS
Output Settling Time (t
ST
) (to 0.1%)
1
35
ns
Output Propagation Delay (t
PD
)
1
ns
Glitch Impulse
5
pV-s
Output Rise Time (10% to 90%)
1
2.5
ns
Output Fall Time (10% to 90%)
1
2.5
ns
Output Noise (I
OUTFS
= 20 mA)
50
pA/
Hz
Output Noise (I
OUTFS
= 2 mA)
30
pA/
Hz
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
0 dBFS Output
T
A
= +25
C
75
84
dBc
6 dBFS Output
76
dBc
12 dBFS Output
81
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz
81
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 2.51 MHz
81
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz
76
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 14.02 MHz
62
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 20.2 MHz
60
dBc
f
CLOCK
= 100 MSPS; f
OUT
= 2.5 MHz
78
dBc
f
CLOCK
= 100 MSPS; f
OUT
= 5 MHz
76
dBc
f
CLOCK
= 100 MSPS; f
OUT
= 20 MHz
63
dBc
f
CLOCK
= 100 MSPS; f
OUT
= 40 MHz
55
dBc
Spurious-Free Dynamic Range within a Window
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
84
93
dBc
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz; 2 MHz Span
86
dBc
f
CLOCK
= 100 MSPS; f
OUT
= 5.04 MHz; 4 MHz Span
86
dBc
Total Harmonic Distortion
f
CLOCK
= 25 MSPS; f
OUT
= 1.00 MHz
T
A
= +25
C
82
74
dBc
f
CLOCK
= 50 MHz; f
OUT
= 2.00 MHz
76
dBc
f
CLOCK
= 100 MHz; f
OUT
= 2.00 MHz
76
dBc
Multitone Power Ratio (8 Tones at 110 kHz Spacing)
f
CLOCK
= 20 MSPS; f
OUT
= 2.00 MHz to 2.99 MHz
0 dBFS Output
81
dBc
6 dBFS Output
81
dBc
12 dBFS Output
85
dBc
18 dBFS Output
86
dBc
NOTES
1
Measured single ended into 50
load.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, Differential Transformer Coupled Output,
50
Doubly Terminated, unless otherwise noted)
REV. 0
AD9752
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9752 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
With
Parameter
Respect to
Min
Max
Units
AVDD
ACOM
0.3
+6.5
V
DVDD
DCOM
0.3
+6.5
V
ACOM
DCOM
0.3
+0.3
V
AVDD
DVDD
6.5
+6.5
V
CLOCK, SLEEP
DCOM
0.3
DVDD + 0.3
V
Digital Inputs
DCOM
0.3
DVDD + 0.3
V
IOUTA, IOUTB
ACOM
1.0
AVDD + 0.3
V
ICOMP
ACOM
0.3
AVDD + 0.3
V
REFIO, FSADJ
ACOM
0.3
AVDD + 0.3
V
REFLO
ACOM
0.3
+0.3
V
Junction Temperature
+150
C
Storage Temperature
65
+150
C
Lead Temperature
(10 sec)
+300
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
DIGITAL SPECIFICATIONS
Parameter
Min
Typ
Max
Units
DIGITAL INPUTS
Logic "1" Voltage @ DVDD = +5 V
1
3.5
5
V
Logic "1" Voltage @ DVDD = +3 V
2.1
3
V
Logic "0" Voltage @ DVDD = +5 V
1
0
1.3
V
Logic "0" Voltage @ DVDD = +3 V
0
0.9
V
Logic "1" Current
10
+10
A
Logic "0" Current
10
+10
A
Input Capacitance
5
pF
Input Setup Time (t
S
)
2.0
ns
Input Hold Time (t
H
)
1.5
ns
Latch Pulsewidth (t
LPW
)
3.5
ns
NOTES
1
When DVDD = +5 V and Logic 1 voltage
3.5 V and Logic 0 voltage
1.3 V. IVDD can increase by up to 10 mA, depending on f
CLOCK
.
Specifications subject to change without notice.
0.1%
0.1%
t
S
t
H
t
LPW
t
PD
t
ST
DB0DB11
CLOCK
IOUTA
OR
IOUTB
Figure 1. Timing Diagram
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, unless otherwise noted)
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Options*
AD9752AR
40
C to +85
C 28-Lead 300 Mil SOIC R-28
AD9752ARU 40
C to +85
C 28-Lead TSSOP
RU-28
AD9752-EB
Evaluation Board
*R = Small Outline IC; RU = Thin Shrink Small Outline Package.
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 Mil SOIC
JA
= 71.4
C/W
JC
= 23
C/W
28-Lead TSSOP
JA
= 97.9
C/W
JC
= 14.0
C/W
REV. 0
AD9752
5
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9752
NC = NO CONNECT
(MSB) DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
CLOCK
DVDD
DCOM
NC
AVDD
ICOMP
IOUTA
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1
DB11
Most Significant Data Bit (MSB).
211
DB10DB1 Data Bits 110.
12
DB0
Least Significant Data Bit (LSB).
13, 14,
19, 25
NC
No Internal Connection.
15
SLEEP
Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated
if not used.
16
REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1
F capacitor to ACOM when internal reference activated.
18
FS ADJ
Full-Scale Current Output Adjust.
19
NC
No Connect.
20
ACOM
Analog Common.
21
IOUTB
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22
IOUTA
DAC Current Output. Full-scale current when all data bits are 1s.
23
ICOMP
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1
F capacitor.
24
AVDD
Analog Supply Voltage (+4.5 V to +5.5 V).
26
DCOM
Digital Common.
27
DVDD
Digital Supply Voltage (+2.7 V to +5.5 V).
28
CLOCK
Clock Input. Data latched on positive edge of clock.
REV. 0
AD9752
6
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25
C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per
C. For reference drift, the drift is reported
in ppm per
C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing mul-
tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.
+1.20V REF
AVDD
ACOM
REFLO
ICOMP
PMOS
CURRENT SOURCE
ARRAY
+5V
SEGMENTED SWITCHES
FOR DB11DB3
LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
R
SET
2k
0.1 F
DVDD
DCOM
IOUTA
IOUTB
0.1 F
AD9752
SLEEP
50
RETIMED
CLOCK
OUTPUT*
LATCHES
DIGITAL
DATA
TEKTRONIX
AWG-2021
W/OPTION 4
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
50
20pF
50
20pF
100
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50 INPUT
MINI-CIRCUITS
T1-1T
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
150pF
Figure 2. Basic AC Characterization Test Setup
REV. 0
AD9752
7
Typical AC Characterization Curves @ +5 V Supplies
(AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, 50
Doubly Terminated Load, Differential Output, T
A
= +25 C, SFDR up to Nyquist, unless otherwise noted)
f
OUT
MHz
SFDR dB
90
80
40
0
1
100
10
70
60
50
25MSPS
50MSPS
125MSPS
65MSPS
Figure 3. SFDR vs. f
OUT
@ 0 dBFS
f
OUT
MHz
SFDR dBc
90
80
40
0
5
30
20
70
60
50
10
15
25
12dBFS
6dBFS
0dBFS
Figure 6. SFDR vs. f
OUT
@ 65 MSPS
A
OUT
dBFS
SFDR dB
90
70
30
25
0
10
80
20
15
5
40
60
50
2.27MHz@25MSPS
4.55MHz@50MSPS
5.91MHz@65MSPS
11.36MHz@125MSPS
Figure 9. Single-Tone SFDR vs. A
OUT
@ f
OUT
= f
CLOCK
/11
SFDR dB
90
80
40
0
2
14
12
70
60
50
4
6
8
10
12dBFS
0dBFS
6dBFS
f
OUT
MHz
Figure 4. SFDR vs. f
OUT
@ 25 MSPS
SFDR dB
90
80
40
0
10
60
40
70
60
50
20
30
50
6dBFS
0dBFS
12dBFS
f
OUT
MHz
Figure 7. SFDR vs. f
OUT
@ 125 MSPS
A
OUT
dBFS
SFDR dB
90
70
30
25
0
10
80
20
15
5
40
60
50
5MHz@25MSPS
10MHz@50MSPS
13MHz@65MSPS
25MHz@125MSPS
Figure 10. Single-Tone SFDR vs.
A
OUT
@ f
OUT
= f
CLOCK
/5
f
OUT
MHz
SFDR dBc
90
80
40
0
5
25
10
70
60
50
15
20
12dBFS
6dBFS
0dBFS
Figure 5. SFDR vs. f
OUT
@ 50 MSPS
f
OUT
MHz
SFDR dBc
90
0
2
12
8
80
70
4
6
10
50
60
10mA FS
20mA FS
5mA FS
Figure 8. SFDR vs. f
OUT
and I
OUTFS
@ 25 MSPS and 0 dBFS
f
CLOCK
MSPS
SNR dB
0
20
120
80
80
40
60
100
60
70
50
20mA FS
10mA FS
5mA FS
Figure 11. SNR vs. f
CLOCK
and I
OUTFS
@ f
OUT
= 2 MHz and 0 dBFS
REV. 0
AD9752
8
CODE
ERROR LSB
0
4000
1000
2000
3000
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
Figure 12. Typical INL
f
OUT
MHz
SIGNAL AMPLITUDE dBm
0
60
10
20
30
0
10
20
30
40
100
50
60
70
80
90
40
50
f
CLK
= 125MSPS
f
OUT1
= 13.5MHz
f
OUT2
= 14.5MHz
A
OUT
= 0dBFS
SFDR = 68.4dBc
Figure 15. Dual-Tone SFDR
CODE
ERROR LSB
0
4000
1000
2000
3000
0.1
0.0
0.1
0.2
0.3
0.5
0.4
Figure 13. Typical DNL
SIGNAL AMPLITUDE dBm
0
30.0
5.0
10.0
15.0
0
10
20
30
40
100
50
60
70
80
90
20.0
25.0
f
CLK
= 65MSPS
f
OUT1
= 6.25MHz
f
OUT2
= 6.75MHz
f
OUT3
= 7.25MHz
f
OUT4
= 7.75MHz
SFDR = 69dBc
AMPLITUDE = 0dBFS
f
OUT
MHz
Figure 16. Four-Tone SFDR
TEMPERATURE C
SFDR dBc
55
95
30
5
20
90
70
80
50
60
45
70
f
OUT
= 4MHz
f
OUT
= 10MHz
f
OUT
= 29MHz
f
OUT
= 40MHz
Figure 14. SFDR vs. Temperature @
125 MSPS, 0 dBFS
REV. 0
AD9752
9
FUNCTIONAL DESCRIPTION
Figure 17 shows a simplified block diagram of the AD9752.
The AD9752 consists of a large PMOS current source array that
is capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle-bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC's high output
impedance (i.e., >100 k
).
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on a new
architecture that drastically improves distortion performance.
This new switch architecture reduces various timing errors and
provides matching complementary drive signals to the inputs of
the differential current switches.
The analog and digital sections of the AD9752 have separate
power supply inputs (i.e., AVDD and DVDD). The digital
section, which is capable of operating up to a 125 MSPS clock
rate and over a +2.7 V to +5.5 V operating range, consists of
edge-triggered latches and segment decoding logic circuitry.
The analog section, which can operate over a +4.5 V to +5.5 V
range, includes the PMOS current sources, the associated differ-
ential switches, a 1.20 V bandgap voltage reference and a refer-
ence control amplifier.
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, R
SET
. The external resistor, in combination with
both the reference control amplifier and voltage reference V
REFIO
,
sets the reference current I
REF
, which is mirrored over to the
segmented current sources with the proper scaling factor. The
full-scale current, I
OUTFS
, is thirty-two times the value of I
REF
.
DAC TRANSFER FUNCTION
The AD9752 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
I
OUTFS
, when all bits are high (i.e., DAC CODE = 4095) while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function
of both the input code and I
OUTFS
and can be expressed as:
IOUTA = (DAC CODE/4096)
I
OUTFS
(1)
IOUTB = (4095 DAC CODE)/4096
I
OUTFS
(2)
where DAC CODE = 0 to 4095 (i.e., Decimal Representation).
As mentioned previously, I
OUTFS
is a function of the reference
current I
REF
, which is nominally set by a reference voltage
V
REFIO
and external resistor R
SET
. It can be expressed as:
I
OUTFS
= 32
I
REF
(3)
where I
REF
= V
REFIO
/R
SET
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
LOAD
, which are tied to analog common, ACOM. Note,
R
LOAD
may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50
or 75
cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply :
V
OUTA
= IOUTA
R
LOAD
(5)
V
OUTB
= IOUTB
R
LOAD
(6)
Note the full-scale value of V
OUTA
and V
OUTB
should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
The differential voltage, V
DIFF
, appearing across IOUTA and
IOUTB is:
V
DIFF
= (IOUTA IOUTB)
R
LOAD
(7)
Substituting the values of I
OUTA
, I
OUTB
, and I
REF
; V
DIFF
can be
expressed as:
V
DIFF
= {(2 DAC CODE 4095)/4096}
(32 R
LOAD
/R
SET
)
V
REFIO
(8)
These last two equations highlight some of the advantages of
operating the AD9752 differentially. First, the differential op-
eration will help cancel common-mode error sources associated
with I
OUTA
and I
OUTB
such as noise, distortion and dc offsets.
Second, the differential code dependent current and subsequent
voltage, V
DIFF
, is twice the value of the single-ended voltage
output (i.e., V
OUTA
or V
OUTB
), thus providing twice the signal
power to the load.
Note, the gain drift temperature performance for a single-ended
(V
OUTA
and V
OUTB
) or differential output (V
DIFF
) of the AD9752
can be enhanced by selecting temperature tracking resistors for
R
LOAD
and R
SET
due to their ratiometric relationship as shown
in Equation 8.
DIGITAL DATA INPUTS (DB11DB0)
150pF
+1.20V REF
AVDD
ACOM
REFLO
ICOMP
PMOS
CURRENT SOURCE
ARRAY
+5V
SEGMENTED SWITCHES
FOR DB11DB3
LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
R
SET
2k
0.1 F
IOUTA
IOUTB
0.1 F
AD9752
SLEEP
LATCHES
I
REF
V
REFIO
CLOCK
I
OUTB
I
OUTA
R
LOAD
50
V
OUTB
V
OUTA
R
LOAD
50
V
DIFF
= V
OUTA
V
OUTB
Figure 17. Functional Block Diagram
REV. 0
AD9752
10
REFERENCE OPERATION
The AD9752 contains an internal 1.20 V bandgap reference
that can easily be disabled and overridden by an external refer-
ence. REFIO serves as either an input or output depending on
whether the internal or an external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 18, the internal
reference is activated and REFIO provides a 1.20 V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1
F or greater from REFIO
to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100 nA if any
additional loading is required.
150pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
+5V
REFIO
FS ADJ
2k
0.1 F
AD9752
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
Figure 18. Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 19. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1
F compensation capacitor is not required
since the internal reference is disabled, and the high input im-
pedance (i.e., 1 M
) of REFIO minimizes any loading of the
external reference.
150pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
AVDD
REFIO
FS ADJ
R
SET
AD9752
EXTERNAL
REF
I
REF
=
V
REFIO
/R
SET
AVDD
REFERENCE
CONTROL
AMPLIFIER
V
REFIO
Figure 19. External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9752 also contains an internal control amplifier that is
used to regulate the DAC's full-scale output current, I
OUTFS
.
The control amplifier is configured as a V-I converter as shown
in Figure 19, such that its current output, I
REF
, is determined by
the ratio of the V
REFIO
and an external resistor, R
SET
, as stated
in Equation 4. I
REF
is copied over to the segmented current
sources with the proper scaling factor to set I
OUTFS
as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
I
OUTFS
over a 2 mA to 20 mA range by setting IREF between
62.5
A and 625
A. The wide adjustment span of I
OUTFS
provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9752, which is
proportional to I
OUTFS
(refer to the Power Dissipation section).
The second benefit relates to the 20 dB adjustment, which is
useful for system gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 0.5 MHz. The output of the control amplifier is
internally compensated via a 150 pF capacitor that limits the
control amplifier small-signal bandwidth and reduces its
output impedance. Since the 3 dB bandwidth corresponds to
the dominant pole, and hence the time constant, the settling
time of the control amplifier to a stepped reference input re-
sponse can be approximated. In this case, the time constant can
be approximated to be 320 ns.
There are two methods in which I
REF
can be varied for a fixed
R
SET
. The first method is suitable for a single-supply system in
which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, thus allowing I
REF
to be varied for a fixed R
SET
. Since the
input impedance of REFIO is approximately 1 M
, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 20 using the AD7524 and an external 1.2 V reference,
the AD1580.
1.2V
150pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
AVDD
REFIO
FS ADJ
R
SET
AD9752
I
REF
=
V
REF
/R
SET
AVDD
V
REF
V
DD
R
FB
OUT1
OUT2
AGND
DB7DB0
AD7524
AD1580
0.1V TO 1.2V
Figure 20. Single-Supply Gain Control Circuit
REV. 0
AD9752
11
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed and I
REF
is
varied by an external voltage, V
GC
, applied to R
SET
via an ampli-
fier. An example of this method is shown in Figure 21, in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V
GC
, is
referenced to ACOM and should not exceed 1.2 V. The value
of R
SET
is such that I
REFMAX
and I
REFMIN
do not exceed 62.5
A
and 625
A, respectively. The associated equations in Figure 21
can be used to determine the value of R
SET
.
150pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
AVDD
REFIO
FS ADJ
R
SET
AD9752
I
REF
V
GC
1 F
I
REF
= (1.2V
GC
)/R
SET
WITH V
GC
< V
REFIO
AND 62.5 A
I
REF
625A
Figure 21. Dual-Supply Gain Control Circuit
ANALOG OUTPUTS
The AD9752 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end
or differential operation. IOUTA and IOUTB can be converted
into complementary single-ended voltage outputs, V
OUTA
and
V
OUTB
, via a load resistor, R
LOAD
, as described in the DAC
Transfer Function section by Equations 5 through 8. The
differential voltage, V
DIFF
, existing between V
OUTA
and V
OUTB
can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.
Figure 22 shows the equivalent analog output circuit of the
AD9752 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is deter-
mined by the equivalent parallel combination of the PMOS
switches and is typically 100 k
in parallel with 5 pF. Due to
the nature of a PMOS device, the output impedance is also
slightly dependent on the output voltage (i.e., V
OUTA
and V
OUTB
)
and, to a lesser extent, the analog supply voltage, AVDD, and
full-scale current, I
OUTFS
. Although the output impedance's
signal dependency can be a source of dc nonlinearity and ac linear-
ity (i.e., distortion), its effects can be limited if certain precau-
tions are noted.
AVDD
IOUTB
IOUTA
R
LOAD
R
LOAD
Figure 22. Equivalent Analog Output
IOUTA and IOUTB also have a negative and positive voltage
compliance range. The negative output compliance range of
1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9752.
The positive output compliance range is slightly dependent on
the full-scale output current, I
OUTFS
. It degrades slightly from its
nominal 1.25 V for an I
OUTFS
= 20 mA to 1.00 V for an I
OUTFS
=
2 mA. Operation beyond the positive compliance range will
induce clipping of the output signal which severely degrades
the AD9752's linearity and distortion performance.
For applications requiring the optimum dc linearity, IOUTA
and/or IOUTB should be maintained at a virtual ground via an
I-V op amp configuration. Maintaining IOUTA and/or IOUTB
at a virtual ground keeps the output impedance of the AD9752
fixed, significantly reducing its effect on linearity. However,
it does not necessarily lead to the optimum distortion perfor-
mance due to limitations of the I-V op amp. Note that the
INL/DNL specifications for the AD9752 are measured in
this manner using IOUTA. In addition, these dc linearity
specifications remain virtually unaffected over the specified
power supply range of 4.5 V to 5.5 V.
Operating the AD9752 with reduced voltage output swings at
IOUTA and IOUTB in a differential or single-ended output
configuration reduces the signal dependency of its output
impedance thus enhancing distortion performance. Although
the voltage compliance range of IOUTA and IOUTB extends
from 1.0 V to +1.25 V, optimum distortion performance is
achieved when the maximum full-scale signal at IOUTA and
IOUTB does not exceed approximately 0.5 V. A properly se-
lected transformer with a grounded center-tap will allow the
AD9752 to provide the required power and voltage levels to
different loads while maintaining reduced voltage swings at
IOUTA and IOUTB. DC-coupled applications requiring a
differential or single-ended output configuration should size
R
LOAD
accordingly. Refer to Applying the AD9752 section for
examples of various output configurations.
The most significant improvement in the AD9752's distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both
IOUTA and IOUTB can be substantially reduced by the
common-mode rejection of a transformer or differential am-
plifier. These common-mode error sources include even-
order distortion products and noise. The enhancement in
distortion performance becomes more significant as the recon-
structed waveform's frequency content increases and/or its
amplitude decreases.
The distortion and noise performance of the AD9752 is also
slightly dependent on the analog and digital supply as well as the
full-scale current setting, I
OUTFS
. Operating the analog supply at
5.0 V ensures maximum headroom for its internal PMOS current
sources and differential switches leading to improved distortion
performance. Although I
OUTFS
can be set between 2 mA and
20 mA, selecting an I
OUTFS
of 20 mA will provide the best dis-
tortion and noise performance also shown in Figure 8. The
noise performance of the AD9752 is affected by the digital sup-
ply (DVDD), output frequency, and increases with increasing
clock rate as shown in Figure 11. Operating the AD9752 with
low voltage logic levels between 3 V and 3.3 V will slightly re-
duce the amount of on-chip digital noise.
REV. 0
AD9752
12
In summary, the AD9752 achieves the optimum distortion and
noise performance under the following conditions:
(1) Differential Operation.
(2) Positive voltage swing at IOUTA and IOUTB limited to
+0.5 V.
(3) I
OUTFS
set to 20 mA.
(4) Analog Supply (AVDD) set at 5.0 V.
(5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro-
priate logic levels.
Note that the ac performance of the AD9752 is characterized
under the above mentioned operating conditions.
DIGITAL INPUTS
The AD9752's digital input consists of 12 data input pins and a
clock input pin. The 12-bit parallel data inputs follow standard
positive binary coding where DB11 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulse-
width. The setup and hold times can also be varied within the
clock cycle as long as the specified minimum times are met;
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is
typically achieved when the input data transitions on the falling edge
of a 50% duty cycle clock.
The digital inputs are CMOS compatible with logic thresholds,
V
THRESHOLD
set to approximately half the digital positive supply
(DVDD) or
V
THRESHOLD
= DVDD/2 (
20%)
The internal digital circuitry of the AD9752 is capable of operating
over a digital supply range of 2.7 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V
OH(MAX)
. A DVDD of 3 V to 3.3 V will typically ensure
proper compatibility with most TTL logic families. Figure 23
shows the equivalent digital input circuit for the data and clock
inputs. The sleep mode input is similar with the exception that
it contains an active pull-down circuit, thus ensuring that the
AD9752 remains enabled if this input is left disconnected.
DVDD
DIGITAL
INPUT
Figure 23. Equivalent Digital Input
Since the AD9752 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the mini-
mum setup and hold times of the AD9752 as well as its re-
quired min/max input logic level thresholds. Typically, the
selection of the slowest logic family that satisfies the above con-
ditions will result in the lowest data feedthrough and noise.
Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20
to 100
) between the
AD9752 digital inputs and driver outputs may be helpful in reduc-
ing any overshooting and ringing at the digital inputs that con-
tribute to data feedthrough. For longer run lengths and high data
update rates, strip line techniques with proper termination resis-
tors should be considered to maintain "clean" digital inputs. Also,
operating the AD9752 with reduced logic swings and a corre-
sponding digital supply (DVDD) will also reduce data feedthrough.
The external clock driver circuitry should provide the AD9752
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
Note, the clock input could also be driven via a sine wave, which is
centered around the digital threshold (i.e., DVDD/2), and meets
the min/max logic threshold. This will typically result in a slight
degradation in the phase noise, which becomes more noticeable
at higher sampling rates and output frequencies. Also, at higher
sampling rates, the 20% tolerance of the digital logic threshold
should be considered since it will affect the effective clock duty
cycle and subsequently cut into the required data setup and
hold times.
INPUT CLOCK/DATA TIMING RELATIONSHIP
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9752 is positive edge triggered, and
so exhibits SNR sensitivity when the data transition is close to
this edge. In general, the goal when applying the AD9752 is to
make the data transitions shortly after the positive clock edge.
This becomes more important as the sample rate increases. Figure
24 shows the relationship of SNR to clock placement with dif-
ferent sample rates and different frequencies out. Note that at
the lower sample rates, much more tolerance is allowed in clock
placement, while at higher rates, much more care must be taken.
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE ns
68
40
8
10
6
4
2
0
2
4
6
8
64
60
56
52
48
SNR dB
44
F
S
= 65MSPS
F
S
= 125MSPS
Figure 24. SNR vs. Clock Placement @ f
OUT
= 10 MHz
REV. 0
AD9752
13
SLEEP MODE OPERATION
The AD9752 has a power-down function which turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 2.7 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level "1" to the SLEEP pin. This digital input also con-
tains an active pull-down circuit that ensures the AD9752 re-
mains enabled if this input is left disconnected. The AD9752
takes less than 50 ns to power down and approximately 5
s to
power back up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9752 is dependent on
several factors which include: (1) AVDD and DVDD, the
power supply voltages; (2) I
OUTFS
, the full-scale current output;
(3) f
CLOCK
, the update rate; (4) and the reconstructed digital
input waveform. The power dissipation is directly proportional
to the analog supply current, I
AVDD
, and the digital supply cur-
rent, I
DVDD
. I
AVDD
is directly proportional to I
OUTFS
as shown in
Figure 25 and is insensitive to f
CLOCK
.
Conversely, I
DVDD
is dependent on both the digital input wave-
form, f
CLOCK
, and digital supply DVDD. Figures 26 and 27
show I
DVDD
as a function of full-scale sine wave output ratios
(f
OUT
/f
CLOCK
) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note, how I
DVDD
is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
I
OUTFS
mA
35
5
2
20
4
6
8
10
12
14
16
18
30
25
20
15
10
I
AVDD
mA
Figure 25. I
AVDD
vs. I
OUTFS
RATIO (f
CLOCK
/f
OUT
)
18
16
0
0.01
1
0.1
I
DVDD
mA
8
6
4
2
12
10
14
125MSPS
100MSPS
50MSPS
25MSPS
5MSPS
Figure 26. I
DVDD
vs. Ratio @ DVDD = 5 V
RATIO (f
CLOCK
/f
OUT
)
8
0
0.01
1
0.1
I
DVDD
mA
6
4
2
125MSPS
100MSPS
50MSPS
25MSPS
5MSPS
Figure 27. I
DVDD
vs. Ratio @ DVDD = 3 V
APPLYING THE AD9752
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configura-
tions for the AD9752. Unless otherwise noted, it is assumed
that I
OUTFS
is set to a nominal 20 mA. For applications requir-
ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the opti-
mum high frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling, a
bipolar output, signal gain and/or level shifting.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropri-
ately sized load resistor, R
LOAD
, referred to ACOM. This con-
figuration may be more suitable for a single-supply system
requiring a dc coupled, ground referred output voltage. Alterna-
tively, an amplifier could be configured as an I-V converter thus
converting IOUTA or IOUTB into a negative unipolar voltage.
This configuration provides the best dc linearity since IOUTA
or IOUTB is maintained at a virtual ground. Note, IOUTA
provides slightly better performance than IOUTB.
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-to-
single-ended signal conversion as shown in Figure 28. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer's passband. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and noise
over a wide frequency range. It also provides electrical isolation
and the ability to deliver twice the power to the load. Trans-
formers with different impedance ratios may also be used for
impedance matching purposes. Note that the transformer
provides ac coupling only.
REV. 0
AD9752
14
R
LOAD
AD9752
MINI-CIRCUITS
T1-1T
OPTIONAL R
DIFF
IOUTA
IOUTB
Figure 28. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., V
OUTA
and V
OUTB
)
swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9752. A
differential resistor, R
DIFF
, may be inserted in applications in
which the output of the transformer is connected to the load,
R
LOAD
, via a passive reconstruction filter or cable. R
DIFF
is deter-
mined by the transformer's impedance ratio and provides the
proper source termination which results in a low VSWR. Note
that approximately half the signal power will be dissipated across
R
DIFF
.
DIFFERENTIAL USING AN OP AMP
An op amp can also be used to perform a differential to single-
ended conversion as shown in Figure 29. The AD9752 is con-
figured with two equal load resistors, R
LOAD
, of 25
. The
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB forming a real pole in a low-pass filter.
The addition of this capacitor also enhances the op amps distor-
tion performance by preventing the DACs high slewing output
from overloading the op amp's input.
AD9752
IOUTA
IOUTB
C
OPT
500
225
225
500
25
25
AD8055
Figure 29. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ-
ential op amp circuit is configured to provide some additional
signal gain. The op amp must operate off of a dual supply since
its output is approximately
1.0 V. A high speed amplifier such
as the AD8055 or AD9632 capable of preserving the differential
performance of the AD9752 while meeting other system level
objectives (i.e., cost, power) should be selected. The op amps
differential gain, its gain setting resistor values, and full-scale
output swing capabilities should all be considered when opti-
mizing this circuit.
The differential circuit shown in Figure 30 provides the neces-
sary level-shifting required in a single supply system. In this
case, AVDD which is the positive analog supply for both the
AD9752 and the op amp is also used to level-shift the differ-
ential output of the AD9752 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.
AD9752
IOUTA
IOUTB
C
OPT
500
225
225
1k
25
25
AD8041
1k
AVDD
Figure 30. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 31 shows the AD9752 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50
cable since the nominal full-scale current, I
OUTFS
, of
20 mA flows through the equivalent R
LOAD
of 25
. In this
case, R
LOAD
represents the equivalent load resistance seen by
IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching R
LOAD
.
Different values of I
OUTFS
and R
LOAD
can be selected as long as
the positive compliance range is adhered to. One additional
consideration in this mode is the integral nonlinearity (INL) as
discussed in the ANALOG OUTPUT section of this data sheet.
For optimum INL performance, the single-ended, buffered
voltage output configuration is suggested.
AD9752
IOUTA
IOUTB
50
25
50
V
OUTA
= 0 TO +0.5V
I
OUTFS
= 20mA
Figure 31. 0 V to +0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 32 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9752
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, thus minimizing the nonlinear output impedance effect
on the DAC's INL performance as discussed in the ANALOG
OUTPUT section. Although this single-ended configuration
typically provides the best dc linearity performance, its ac distor-
tion performance at higher DAC update rates may be limited by
U1's slewing capabilities. U1 provides a negative unipolar out-
put voltage and its full-scale output voltage is simply the
product of R
FB
and I
OUTFS
. The full-scale output should be set
within U1's voltage output swing capabilities by scaling I
OUTFS
and/or R
FB
. An improvement in ac distortion performance may
result with a reduced I
OUTFS
since the signal current U1 will be
required to sink will be subsequently reduced.
REV. 0
AD9752
15
AD9752
IOUTA
IOUTB
C
OPT
200
U1
V
OUT
= I
OUTFS
R
FB
I
OUTFS
= 10mA
R
FB
200
Figure 32. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION
Many applications seek high speed and high performance under
less than ideal operating conditions. In these circuits, the imple-
mentation and construction of the printed circuit board design
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figures 42-47 illustrate the recommended printed
circuit board ground, power and signal plane layouts which are
implemented on the AD9752 evaluation board.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution
(i.e., AVDD, DVDD). This is referred to as Power Supply
Rejection Ratio (PSRR). For dc variations of the power supply,
the resulting performance of the DAC directly corresponds to a
gain error associated with the DAC's full-scale current, I
OUTFS
.
AC noise on the dc supplies is common in applications where
the power distribution is generated by a switching power supply.
Typically, switching power supply noise will occur over the
spectrum from tens of kHz to several MHz. PSRR vs. frequency
of the AD9752 AVDD supply, over this frequency range, is
given in Figure 33.
FREQUENCY MHz
90
80
60
1.0
0.26
PSRR dB
0.5
0.75
70
Figure 33. Power Supply Rejection Ratio of AD9752
Note that the units in Figure 33 are given in units of (amps out)/
(volts in). Noise on the analog power supply has the effect of
modulating the internal switches, and therefore the output
current. The voltage noise on the dc power, therefore, will be
added in a nonlinear manner to the desired I
OUT
. Due to the
relative different sizes of these switches, PSRR is very code depen-
dent. This can produce a mixing effect which can modulate low
frequency power supply noise to higher frequencies. Worst case
PSRR for either one of the differential DAC outputs will occur
when the full-scale current is directed towards that output. As a
result, the PSRR measurement in Figure 33 represents a worst
case condition in which the digital inputs remain static and the
full scale output current of 20 mA is directed to the DAC out-
put being measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV rms of noise and for
simplicity sake (i.e., ignore harmonics), all of this noise is con-
centrated at 250 kHz. To calculate how much of this undesired
noise will appear as current noise super imposed on the DAC's
full-scale current, I
OUTFS
, one must determine the PSRR in dB
using Figure 33 at 250 kHz. To calculate the PSRR for a given
R
LOAD
, such that the units of PSRR are converted from A/V to
V/V, adjust the curve in Figure 33 by the scaling factor 20
Log
(R
LOAD
). For instance, if R
LOAD
is 50
, the PSRR is reduced
by 34 dB (i.e., PSRR of the DAC at 1 MHz which is 74 dB in
Figure 33 becomes 40 dB V
OUT
/V
IN
).
Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9752 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be de-
coupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, DVDD, the digital supply, should
be decoupled to DCOM as close as physically as possible.
For those applications that require a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 34. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.
100 F
ELECT.
10-22 F
TANT.
0.1 F
CER.
TTL/CMOS
LOGIC
CIRCUITS
+5V OR +3V
POWER SUPPLY
FERRITE
BEADS
AVDD
ACOM
Figure 34. Differential LC Filter for Single +5 V or +3 V
Applications
Maintaining low noise on power supplies and ground is critical
to obtaining optimum results from the AD9752. If properly
implemented, ground planes can perform a host of functions on
high speed circuit boards: bypassing, shielding, current trans-
port, etc. In mixed signal design, the analog and digital portions
of the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined to areas covering
the digital interconnects.
All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8
to 1/4 inch wide underneath or within 1/2 inch of the DAC to
REV. 0
AD9752
16
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC as well as any clock signals. On the analog side, this
includes the DAC output signal, reference signal and the supply
feeders.
The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part, as well as providing
some "free" capacitive decoupling to the appropriate ground
plane. It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous volt-
age drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the pack-
age as possible in order to minimize the sharing of conduction
paths between different currents. When runs exceed an inch in
length, strip line techniques with proper termination resistor
should be considered. The necessity and value of this resistor
will be dependent upon the logic family used.
For a more detailed discussion of the implementation and
construction of high speed, mixed signal printed circuit boards,
refer to Analog Devices' application notes AN-280 and
AN-333.
FREQUENCY Hz
30
40
100
1M
600k
AMPLITUDE dBm
800k
50
60
70
80
90
Figure 35a. Notch in Missing Bin at 750 kHz is Down
>60 dB. (Peak Amplitude + 0 dBm).
FREQUENCY MHz
30
40
100
5.15
4.85
AMPLITUDE dBm
5
50
60
70
80
90
110
Figure 35b. Notch in Missing Bin at 5 MHz is Down
>60 dB. (Peak Amplitude + 0 dBm).
APPLICATIONS
VDSL Applications Using the AD9752
Very High Frequency Digital Subscriber Line (VDSL) technol-
ogy is growing rapidly in applications requiring data transfer
over relatively short distances. By using QAM modulation and
transmitting the data in multiple discrete tones, high data rates
can be achieved.
As with other multitone applications, each VDSL tone is ca-
pable of transmitting a given number of bits, depending on the
signal-to-noise ratio (SNR) in a narrow band around that tone.
The tones are evenly spaced over the range of several kHz to
10 MHz. At the high frequency end of this range, performance
is generally limited by cable characteristics and environmental
factors, such as external interferers. Performance at the lower
frequencies is much more dependent on the performance of the
components in the signal chain. In addition to in-band noise,
intermodulation from other tones can also potentially interfere
with the recovery of data for a given tone. The two graphs in
Figure 35 represent a 500 tone missing bin test vector, with
frequencies evenly spaced from 400 Hz to 10 MHz. This test is
very commonly done to determine if distortion will limit the
number of bits which can be transmitted in a tone. The test
vector has a series of missing tones around 750 kHz, which is
represented in Figure 35a and a series of missing tones around
5 MHz which is represented in Figure 35b. In both cases, the
spurious free range between the transmitted tones and the empty
bins is greater than 60 dB.
Using the AD9752 for Quadrature Amplitude Modulation
(QAM)
QAM is one of the most widely used digital modulation
schemes in digital communication systems. This modulation
technique can be found in FDM as well as spreadspectrum (i.e.,
CDMA) based systems. A QAM signal is a carrier frequency
that is modulated in both amplitude (i.e., AM modulation) and
phase (i.e., PM modulation). It can be generated by indepen-
dently modulating two carriers of identical frequency but with a
90
phase difference. This results in an in-phase (I) carrier com-
ponent and a quadrature (Q) carrier component at a 90
phase
shift with respect to the I component. The I and Q components
are then summed to provide a QAM signal at the specified car-
rier frequency.
A common and traditional implementation of a QAM modu-
lator is shown in Figure 36. The modulation is performed in the
analog domain in which two DACs are used to generate the
baseband I and Q components, respectively. Each component is
then typically applied to a Nyquist filter before being applied to
a quadrature mixer. The matching Nyquist filters shape and
limit each component's spectral envelope while minimizing
intersymbol interference. The DAC is typically updated at the
QAM symbol rate or possibly a multiple of it if an interpolating
filter precedes the DAC. The use of an interpolating filter typi-
cally eases the implementation and complexity of the analog
filter, which can be a significant contributor to mismatches in
gain and phase between the two baseband channels. A quadra-
ture mixer modulates the I and Q components with in-phase
and quadrature phase carrier frequency and then sums the two
outputs to provide the QAM signal.
REV. 0
AD9752
17
AD9752
("I DAC")
AD9752
("Q DAC")
IOUTA
IOUTB
QOUTA
QOUTB
DCOM
FSADJ
REFIO
SLEEP
R
SET2
1.9k
0.1 F
CLK
Q DATA
INPUT
I DATA
INPUT
DVDD
AVDD
100W
500
100
C
FILTER
100
C
FILTER
100
500
500
500
500
500
500
634
0.1 F
+5V
VPBF
BBIP
BBIN
BBQP
BBQN
AD8346
PHASE
SPLITTER
LOIP
LOIN
VOUT
500mV p-p WITH
V
CM
=1.2V
NOTE: 500 RESISTOR NETWORK - OHMTEK ORN5000D
100 RESISTOR NETWORK - TOMC1603-100D
REFLO
ACOM
REFLO
AVDD
REFIO
FSADJ
R
SET1
2k
R
CAL
220
U1
U2
AVDD
1.82V
LATCHES
500
DAC
DAC
+
LATCHES
Figure 37. Baseband QAM Implementation Using Two AD9752s
AD9752
0
90
AD9752
CARRIER
FREQUENCY
12
12
TO
MIXER
DSP
OR
ASIC
NYQUIST
FILTERS
QUADRATURE
MODULATOR
Figure 36. Typical Analog QAM Architecture
In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 37 helps improve
upon the matching and temperature stability characteristics
between the I and Q channels, as well as showing a path for up-
conversion using the AD8346 quadrature modulator. Using a
single voltage reference derived from U1 to set the gain for both
the I and Q channels will improve the gain matching and stabil-
ity. R
CAL
can be used to compensate for any mismatch in gain
between the two channels. This mismatch may be attributed to
the mismatch between R
SET1
and R
SET2
, effective load resistance
of each channel, and/or the voltage offset of the control ampli-
fier in each DAC. The differential voltage outputs of U1 and U2
are fed into the respective differential inputs of the AD8346 via
matching networks.
Using the same matching techniques described above, Figure 38
shows an example of the AD9752 used in a W-CDMA transmit-
ter application using the AD6122 CDMA 3 V transmitter IF
subsystem. The AD6122 has functions, such as external gain
control and low distortion characteristics, needed for the supe-
rior Adjacent Channel Power (ACP) requirements of W-CDMA.
CDMA
Carrier Division Multiple Access, or CDMA, is an air transmit/
receive scheme where the signal in the transmit path is modu-
lated with a pseudorandom digital code (sometimes referred to
as the spreading code). The effect of this is to spread the trans-
mitted signal across a wide spectrum. Similar to a DMT wave-
form, a CDMA waveform containing multiple subscribers can
be characterized as having a high peak to average ratio (i.e.,
crest factor), thus demanding highly linear components in the
transmit signal path. The bandwidth of the spectrum is defined
by the CDMA standard being used, and in operation is imple-
mented by using a spreading code with particular characteristics.
Distortion in the transmit path can lead to power being trans-
mitted out of the defined band. The ratio of power transmitted
in-band to out-of-band is often referred to as Adjacent Channel
Power (ACP). This is a regulatory issue due to the possibility of
interference with other signals being transmitted by air. Regula-
tory bodies define a spectral mask outside of the transmit band,
and the ACP must fall under this mask. If distortion in the
transmit path cause the ACP to be above the spectral mask,
then filtering, or different component selection is needed to
meet the mask requirements.
REV. 0
AD9752
18
AD9752
("I DAC")
AD9752
("Q DAC")
IOUTA
IOUTB
QOUTA
QOUTB
DCOM
FSADJ
REFIO
SLEEP
R
SET2
1.9k
0.1 F
CLK
Q DATA
INPUT
I DATA
INPUT
DVDD
AVDD
100W
500
100
C
FILTER
100
500
500
500
500
500
500
634
+3V
IIPP
IIPN
IIQP
IIQN
AD6122
REFLO
ACOM
REFLO
AVDD
REFIO
FSADJ
R
SET1
2k
R
CAL
220
U1
U2
AVDD
LATCHES
500
DAC
DAC
LATCHES
100
PHASE
SPLITTER
2
TEMPERATURE
COMPENSATION
GAIN
CONTROL
SCALE
FACTOR
REFIN
VGAIN
GAIN
CONTROL
LOIPP
LOIPN
TXOPP
TXOPN
V
CC
V
CC
Figure 38. CDMA Transmit Application Using AD9752
Figure 39 shows the AD9752 reconstructing a wideband, or
W-CDMA test vector with a bandwidth of 5 MHz, centered at
15.625 MHz and being sampled at 62.5 MSPS. ACP for the given
test vector is measured at 70 dB.
20
80
120
CENTER 16.384MHz
SPAN 14.096MHz
1.4096MHz
30
70
90
110
50
60
100
40
CO
CO
CL1
CU1
Figure 39. CDMA Signal, Sampled at 65 MSPS, Adjacent
Channel Power >70 dBm
It is also possible to generate a QAM signal completely in the
digital domain via a DSP or ASIC, in which case only a single
DAC of sufficient resolution and performance is required to
reconstruct the QAM signal. Also available from several vendors
are Digital ASICs which implement other digital modulation
schemes such as PSK and FSK. This digital implementation has
the benefit of generating perfectly matched I and Q components
in terms of gain and phase, which is essential in maintaining
optimum performance in a communication system. In this imple-
mentation, the reconstruction DAC must be operating at a
sufficiently high clock rate to accommodate the highest specified
QAM carrier frequency. Figure 40 shows a block diagram of
such an implementation using the AD9752.
50
AD9752
LPF
50
TO
MIXER
STEL-1130
QAM
12
COS
12
SIN
12
12
I DATA
Q DATA
12
CARRIER
FREQUENCY
12
STEL-1177
NCO
CLOCK
Figure 40. Digital QAM Architecture
AD9752 EVALUATION BOARD
General Description
The AD9752-EB is an evaluation board for the AD9752 12-bit
D/A converter. Careful attention to layout and circuit design
combined with a prototyping area allow the user to easily and
effectively evaluate the AD9752 in any application where high
resolution, high speed conversion is required.
This board allows the user the flexibility to operate the AD9752
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting
and differential amplifier outputs. The digital inputs are designed
to be driven directly from various word generators, with the
on-board option to add a resistor network for proper load
termination. Provisions are also made to operate the AD9752
with either the internal or external reference, or to exercise the
power-down feature.
Refer to the application note AN-420 for a thorough description
and operating instructions for the AD9752 evaluation board.
REV. 0
AD9752
19
1
0
98
76
54
32
1
R4
10
9
8
7
6
5
4
3
2
1
R7
DVDD
10
9
8
7
6
5
4
3
2
1
R3
1
0
98
76
54
32
1
DVDD
R6
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
P1
10
9
8
7
6
5
4
3
2
1
R5
DVDD
10
9
8
7
6
5
4
3
2
1
R1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
C19
C1
C2
C25
C26
C27
C28
C29
16 PINDIP
RES PK
16
15
14
13
12
11
10
1
2
3
4
5
6
7
C30
C31
C32
C33
C34
C35
C36
16 PINDIP
RES PK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
U1
AD975x
AVDD
CT1
A
1
A
R15
49.9
CLK
JP1
AB
3
2
1
J1
TP1
EXTCLK
C7
1
F
C8
0.1
F
AVDD
A
C9
0.1
F
TP8
2
AVDD
TP11
C11
0.1
F
TP10
TP9
R16
2k
TP14
JP4
C10
0.1
F
OUT 1
OUT 2
TP13
R17
49.9
PDIN
J2
A
A
A
AVDD
3
JP2
TP12
TP7
A
C6
10
F
AVCC
B6
TP6
A
C5
10
F
AVEE
B5
TP19
A
AGND
B4
TP18
TP5
C4
10
F
TP4
AVDD
B3
TP2
DGND
B2
C3
10
F
TP3
DVDD
B1
R20
49.9
J3
C12
22pF
A
A
R14
0
A
4
5
6
1
3
T1
J7
R38
49.9
J4
A
A
JP6A
JP6B
A
R13
OPEN
C13
22pF
C20
0
R12
OPEN
A
B
A
JP7B
B
A
JP7A
R10
1k
B
A
JP8
R9
1k
A
B
A
R35
1k
JP9
R18
1k
A
3
7
6
2
4
AD8047
C21
0.1
F
A
C22
1
F
R36
1k
C23
0.1
F
A
C24
1
F
AVEE
AVCC
R37
49.9
J6
A
3
7
6
2
4
1
2
3
JP5
C15
0.1
F
A
AVEE
R46
1k
C17
0.1
F
A
1
2
3
JP3
A
B
AVCC
A
CW
R43
5k
R45
1k
C14
1
F
A
R44
50
EXTREFIN
J5
A
R42
1k
C16
1
F
A
AVCC
C18
0.1
F
U7
6
2
4
A
VIN
VOUT
GND
REF43
98
76
54
32
1
R2
10
A
1
0
98
76
54
32
1
DVDD
R8
U6
A
AD8047
OUT2
OUT1
U4
Figure 41. Evaluation Board Schematic
REV. 0
AD9752
20
Figure 42. Silkscreen Layer--Top
Figure 43. Component Side PCB Layout (Layer 1)
REV. 0
AD9752
21
Figure 44. Ground Plane PCB Layout (Layer 2)
Figure 45. Power Plane PCB Layout (Layer 3)
REV. 0
AD9752
22
Figure 46. Solder Side PCB Layout (Layer 4)
Figure 47. Silkscreen Layer--Bottom
REV. 0
AD9752
23
28-Lead, 300 Mil SOIC
(R-28)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
45
0.7125 (18.10)
0.6969 (17.70)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
28
15
14
1
28-Lead TSSOP
(RU-28)
28
15
14
1
0.386 (9.80)
0.378 (9.60)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C333281/99
PRINTED IN U.S.A.
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