REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD9754*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

14-Bit, 125 MSPS High Performance

TxDAC

D/A Converter

FUNCTIONAL BLOCK DIAGRAM

150pF

+1.20V REF

AVDD

ACOM

REFLO

ICOMP

CURRENT

SOURCE

ARRAY

+5V

SEGMENTED

SWITCHES

LSB

SWITCHES

REFIO

FS ADJ

DVDD

DCOM

CLOCK

+5V

SET

0.1 F

CLOCK

IOUTA

IOUTB

0.1 F

LATCHES

AD9754

SLEEP

DIGITAL DATA INPUTS (DB13DB0)

FEATURES
High Performance Member of Pin-Compatible

TxDAC Product Family

125 MSPS Update Rate
14-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 83 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 185 mW @ 5 V
Power-Down Mode: 20 mW @ 5 V
On-Chip 1.20 V Reference
CMOS-Compatible +2.7 V to +5.5 V Digital Interface
Package: 28-Lead SOIC, TSSOP Packages
Edge-Triggered Latches

APPLICATIONS
Wideband Communication Transmit Channel:

Direct IF
Basestations
Wireless Local Loop
Digital Radio Link

Direct Digital Synthesis (DDS)
Instrumentation

PRODUCT DESCRIPTION

The AD9754 is a 14-bit resolution, wideband, second genera-
tion member of the TxDAC series of high performance, low
power CMOS digital-to-analog-converters (DACs). The
TxDAC

family, which consists of pin compatible 8-, 10-, 12-

and 14-bit DACs, is specifically optimized for the transmit
signal path of communication systems. All of the devices share
the same interface options, small outline package and pinout,
providing an upward or downward component selection path
based on performance, resolution and cost. The AD9754 offers
exceptional ac and dc performance while supporting update
rates up to 125 MSPS.

The AD9754's flexible single-supply operating range of +4.5 V to
+5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further reduc-
ed to a mere 65 mW with a slight degradation in performance by
lowering the full-scale current output. Also, a power-down mode
reduces the standby power dissipation to approximately 20 mW.

The AD9754 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input latches
and a 1.2 V temperature compensated bandgap reference have
been integrated to provide a complete monolithic DAC solution.
The digital inputs support +2.7 V and +5 V CMOS logic families.

The AD9754 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 k

output impedance.

Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.

The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9754 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier, which provides a wide
(>10:1) adjustment span, allows the AD9754 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9754 may operate
at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.

The AD9754 is available in 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.

PRODUCT HIGHLIGHTS

1. The AD9754 is a member of the wideband TxDAC

high per-

formance product family that provides an upward or downward
component selection path based on resolution (8 to 14 bits),
performance and cost. The entire family of TxDACs is avail-
able in industry standard pinouts.

2. Manufactured on a CMOS process, the AD9754 uses a

proprietary switching technique that enhances dynamic per-
formance beyond that previously attainable by higher power/
cost bipolar or BiCMOS devices.

3. On-chip, edge-triggered input CMOS latches readily inter-

face to +2.7 V to +5 V CMOS logic families. The AD9754
can support update rates up to 125 MSPS.

4. A flexible single-supply operating range of +4.5 V to +5.5 V,

and a wide full-scale current adjustment span of 2 mA to
20 mA, allows the AD9754 to operate at reduced power levels.

5. The current output(s) of the AD9754 can be easily config-

ured for various single-ended or differential circuit topologies.

TxDAC is a registered trademark of Analog Devices, Inc.
*Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and

5703519. Other patents pending.

DC SPECIFICATIONS

Parameter

Min

Typ

Max

Units

RESOLUTION

Bits

DC ACCURACY

Integral Linearity Error (INL)

= +25

3.0

1.5

+3.0

LSB

Differential Nonlinearity (DNL)

= +25

2.0

0.75

+2.0

LSB

ANALOG OUTPUT

Offset Error

0.02

+0.02

% of FSR

Gain Error

(Without Internal Reference)

0.5

% of FSR

Gain Error

(With Internal Reference)

1.5

% of FSR

Full-Scale Output Current

2.0

20.0

Output Compliance Range

1.0

1.25

Output Resistance

100

Output Capacitance

REFERENCE OUTPUT

Reference Voltage

1.14

1.20

1.26

Reference Output Current

100

REFERENCE INPUT

Input Compliance Range

0.1

1.25

Reference Input Resistance

Small Signal Bandwidth

0.5

MHz

TEMPERATURE COEFFICIENTS

Offset Drift

ppm of FSR/

Gain Drift

(Without Internal Reference)

ppm of FSR/

Gain Drift

(With Internal Reference)

100

ppm of FSR/

Reference Voltage Drift

ppm/

POWER SUPPLY

Supply Voltages

AVDD

4.5

5.0

5.5

DVDD

2.7

5.0

5.5

Analog Supply Current (I

AVDD

)

Digital Supply Current (I

DVDD

)

3.0

Supply Current Sleep Mode (I

AVDD

)

4.0

Power Dissipation

(5 V, I

OUTFS

= 20 mA)

185

220

Power Supply Rejection Ratio

--AVDD

0.4

+0.4

% of FSR/V

Power Supply Rejection Ratio

--DVDD

0.025

+0.025

% of FSR/V

OPERATING RANGE

+85

NOTES

Measured at IOUTA, driving a virtual ground.

Nominal full-scale current, I

OUTFS

, is 32

the I

REF

current.

Use an external buffer amplifier to drive any external load.

Requires +5 V supply.

Measured at f

CLOCK

= 25 MSPS and I

OUT

= static full scale (20 mA).

Logic level for SLEEP pin must be referenced to AVDD. Min V

= 3.5 V.

5% Power supply variation.

Specifications subject to change without notice.

MIN

to T

MAX

, AVDD = +5 V, DVDD = +5 V, I

OUTFS

= 20 mA, unless otherwise noted)

REV. A

AD9754SPECIFICATIONS

DYNAMIC SPECIFICATIONS

Parameter

Min

Typ

Max

Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f

CLOCK

)

125

MSPS

Output Settling Time (t

) (to 0.1%)

Output Propagation Delay (t

)

Glitch Impulse

pV-s

Output Rise Time (10% to 90%)

2.5

Output Fall Time (10% to 90%)

2.5

Output Noise (I

OUTFS

= 20 mA)

pA/

Output Noise (I

OUTFS

= 2 mA)

pA/

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

CLOCK

= 25 MSPS; f

OUT

= 1.00 MHz

0 dBFS Output

= +25

dBc

6 dBFS Output

dBc

12 dBFS Output

dBc

CLOCK

= 50 MSPS; f

OUT

= 1.00 MHz

dBc

CLOCK

= 50 MSPS; f

OUT

= 2.51 MHz

dBc

CLOCK

= 50 MSPS; f

OUT

= 5.02 MHz

dBc

CLOCK

= 50 MSPS; f

OUT

= 20.2 MHz

dBc

CLOCK

= 100 MSPS; f

OUT

= 10 MHz

dBc

Spurious-Free Dynamic Range within a Window

CLOCK

= 25 MSPS; f

OUT

= 1.00 MHz; 2 MHz Span

dBc

CLOCK

= 50 MSPS; f

OUT

= 5.02 MHz; 2 MHz Span

dBc

CLOCK

= 100 MSPS; f

OUT

= 5.04 MHz; 4 MHz Span

dBc

Total Harmonic Distortion

CLOCK

= 25 MSPS; f

OUT

= 1.00 MHz

= +25

dBc

CLOCK

= 50 MHz; f

OUT

= 2.00 MHz

dBc

CLOCK

= 100 MHz; f

OUT

= 2.00 MHz

dBc

Multitone Power Ratio (8 Tones at 110 kHz Spacing)

CLOCK

= 20 MSPS; f

OUT

= 2.00 MHz to 2.99 MHz

0 dBFS Output

dBc

6 dBFS Output

dBc

12 dBFS Output

dBc

18 dBFS Output

dBc

NOTES

Measured single-ended into 50

load.

Specifications subject to change without notice.

MIN

to T

MAX

, AVDD = +5 V, DVDD = +5 V, I

OUTFS

= 20 mA, Differential Transformer Coupled Output,

Doubly Terminated, unless otherwise noted)

AD9754

REV. A

AD9754

REV. A

ABSOLUTE MAXIMUM RATINGS*

With

Parameter

Respect to

Min

Max

Units

AVDD

ACOM

0.3

+6.5

DVDD

DCOM

0.3

+6.5

ACOM

DCOM

0.3

+0.3

AVDD

DVDD

6.5

+6.5

CLOCK, SLEEP

DCOM

0.3

DVDD + 0.3

Digital Inputs

DCOM

0.3

DVDD + 0.3

IOUTA, IOUTB

ACOM

1.0

AVDD + 0.3

ICOMP

ACOM

0.3

AVDD + 0.3

REFIO, FSADJ

ACOM

0.3

AVDD + 0.3

REFLO

ACOM

0.3

AVDD +0.3

Junction Temperature

+150

Storage Temperature

+150

Lead Temperature

(10 sec)

+300

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.

ORDERING GUIDE

Temperature

Package

Model

Range

Descriptions

Options*

AD9754AR

C to +85

28-Lead 300 Mil SOIC R-28

AD9754ARU 40

C to +85

28-Lead TSSOP

RU-28

AD9754-EB

Evaluation Board

*R = Small Outline IC; RU = Thin Shrink Small Outline Package.

THERMAL CHARACTERISTICS
Thermal Resistance

28-Lead 300 Mil SOIC

= 71.4

C/W

= 23

C/W

28-Lead TSSOP

= 97.9

C/W

= 14.0

C/W

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9754 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

MIN

to T

MAX

, AVDD = +5 V, DVDD = +5 V, I

OUTFS

= 20 mA unless otherwise noted)

DIGITAL SPECIFICATIONS

Parameter

Min

Typ

Max

Units

DIGITAL INPUTS

Logic "1" Voltage @ DVDD = +5 V

3.5

Logic "1" Voltage @ DVDD = +3 V

2.1

Logic "0" Voltage @ DVDD = +5 V

1.3

Logic "0" Voltage @ DVDD = +3 V

0.9

Logic "1" Current

+10

Logic "0" Current

+10

Input Capacitance

Input Setup Time (t

)

2.0

Input Hold Time (t

)

1.5

Latch Pulsewidth (t

LPW

)

3.5

NOTES

When DVDD = +5 V and Logic 1 voltage

3.5 V and Logic 0 voltage

1.3

IVDD can increase by up to 10 mA depending on f

CLOCK

Specifications subject to change without notice.

0.1%

DB0DB11

CLOCK

IOUTA

IOUTB

LPW

Figure 1. Timing Diagram

WARNING!

ESD SENSITIVE DEVICE

AD9754

REV. A

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

Description

DB13

Most Significant Data Bit (MSB).

213

DB12DB1 Data Bits 112.

DB0

Least Significant Data Bit (LSB).

SLEEP

Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if
not used.

REFLO

Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.

REFIO

Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1

F capacitor to ACOM when internal reference activated.

FS ADJ

Full-Scale Current Output Adjust.

19, 25

No Connect.

ACOM

Analog Common.

IOUTB

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

IOUTA

DAC Current Output. Full-scale current when all data bits are 1s.

ICOMP

Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1

F capacitor.

AVDD

Analog Supply Voltage (+4.5 V to +5.5 V).

DCOM

Digital Common.

DVDD

Digital Supply Voltage (+2.7 V to +5.5 V).

CLOCK

Clock Input. Data latched on positive edge of clock.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD9754

NC = NO CONNECT

(MSB) DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

(LSB) DB0

CLOCK

DVDD

DCOM

AVDD

ICOMP

IOUTA

IOUTB

ACOM

FS ADJ

REFIO

REFLO

SLEEP

AD9754

REV. A

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (+25

C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per

C. For reference drift, the drift is reported

in ppm per

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied over a specified range.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the sum of the rms value of the first six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).

Multitone Power Ratio

The spurious-free dynamic range for an output containing mul-
tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.

150pF

+1.20V REF

AVDD

ACOM

REFLO

ICOMP

PMOS

CURRENT SOURCE

ARRAY

SEGMENTED SWITCHES

FOR DB13DB5

LSB

SWITCHES

REFIO

FS ADJ

DVDD

DCOM

CLOCK

+5V

SET

0.1 F

DVDD

DCOM

IOUTA

IOUTB

0.1 F

AD9754

SLEEP

RETIMED

CLOCK

OUTPUT*

LATCHES

DIGITAL

DATA

TEKTRONIX AWG-2021

w/OPTION 4

LECROY 9210

PULSE GENERATOR

CLOCK

OUTPUT

20pF

100

TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50 INPUT

MINI-CIRCUITS

T1-1T

* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.

+5V

Figure 2. Basic AC Characterization Test Setup

AD9754

REV. A

Typical AC Characterization Curves

(AVDD = +5 V, DVDD = +3 V, I

OUTFS

= 20 mA, 50

Doubly Terminated Load, Differential Output, T

= +25 C, SFDR up to Nyquist, unless

otherwise noted)

OUT

 MHz

SFDR dB

0.1

100

5MSPS

25MSPS

65MSPS

50MSPS

125MSPS

Figure 3. SFDR vs. f

OUT

@ 0 dBFS

OUT

 MHz

SFDR dBc

0dBFS

6dBFS

12dBFS

Figure 6. SFDR vs. f

OUT

@ 65 MSPS

OUT

 dBFS

SFDR dB

30

25

20

15

10

455kHz

@5MSPS

2.27MHz

@25MSPS

59.1MHz
@65MSPS

11.37MHz

@125MSPS

Figure 9. Single-Tone SFDR vs. A

OUT

@ f

OUT

= f

CLOCK

/11

FREQUENCY MHz

SFDR dB

0.0

2.0

0.4

0.8

1.2

1.6

0dBFS

6dBFS

12dBFS

Figure 4. SFDR vs. f

OUT

@ 5 MSPS

OUT

 MHz

SFDR dBc

0dBFS

6dBFS

12dBFS

Figure 7. SFDR vs. f

OUT

@125 MSPS

OUT

 dBFS

SFDR dB

100

30

25

20

15

10

1MHz

@5MSPS

5MHz

@25MSPS

25MHz

@125MSPS

13MHz

@65MSPS

Figure 10. Single-Tone SFDR vs.
A

OUT

@ f

OUT

= f

CLOCK

FREQUENCY MHz

SFDR dB

0dBFS

6dBFS

12dBFS

Figure 5. SFDR vs. f

OUT

@ 25 MSPS

10mA FS

OUT

 MHz

SFDR dBc

20mA FS

5mA FS

Figure 8. SFDR vs. f

OUT

and

OUTFS

@ 25 MSPS and 0 dBFS

CLOCK

 MSPS

SNR dB

140

100

120

20mA FS

5mA FS

10mA FS

Figure 11. SNR vs. f

CLOCK

and I

OUTFS

@ f

OUT

= 2 MHz and 0 dBFS

AD9754

REV. A

FUNCTIONAL DESCRIPTION

Figure 16 shows a simplified block diagram of the AD9754. The
AD9754 consists of a large PMOS current source array that is
capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the five most
significant bits (MSBs). The next four bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC's high output
impedance (i.e., >100 k

All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on a new
architecture that drastically improves distortion performance.
This new switch architecture reduces various timing errors and
provides matching complementary drive signals to the inputs of
the differential current switches.

The analog and digital sections of the AD9754 have separate
power supply inputs (i.e., AVDD and DVDD). The digital sec-
tion, which is capable of operating up to a 125 MSPS clock rate
and over +2.7 V to +5.5 V operating range, consists of edge-
triggered latches and segment decoding logic circuitry. The
analog section, which can operate over a +4.5 V to +5.5 V range
includes the PMOS current sources, the associated differential
switches, a 1.20 V bandgap voltage reference and a reference
control amplifier.

The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, R

SET

. The external resistor, in combination with

both the reference control amplifier and voltage reference V

REFIO

sets the reference current I

REF

, which is mirrored over to the

segmented current sources with the proper scaling factor. The
full-scale current, I

OUTFS

, is 32 times the value of I

REF

DAC TRANSFER FUNCTION

The AD9754 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current out-
put, I

OUTFS

, when all bits are high (i.e., DAC CODE = 16383)

while IOUTB, the complementary output, provides no current.
The current output appearing at IOUTA and IOUTB is a func-
tion of both the input code and I

OUTFS

and can be expressed as:

IOUTA = (DAC CODE/16384)

OUTFS

(1)

IOUTB = (16383 DAC CODE)/16384

OUTFS

(2)

where DAC CODE = 0 to 16383 (i.e., Decimal Representation).

As mentioned previously, I

OUTFS

is a function of the reference

current I

REF

, which is nominally set by a reference voltage V

REFIO

and external resistor R

SET

. It can be expressed as:

OUTFS

= 32

REF

(3)

where I

REF

= V

REFIO

SET

(4)

The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R

LOAD

, that are tied to analog common, ACOM. Note

that R

LOAD

may represent the equivalent load resistance seen by

IOUTA or IOUTB as would be the case in a doubly terminated
50

or 75

cable. The single-ended voltage output appearing

at the IOUTA and IOUTB nodes is simply:

OUTA

= IOUTA

LOAD

(5)

OUTB

= IOUTB

LOAD

(6)

Note that the full-scale value of V

OUTA

and V

OUTB

should not

exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.

The differential voltage, V

DIFF

, appearing across IOUTA and

IOUTB is:

DIFF

= (IOUTA IOUTB)

LOAD

(7)

Substituting the values of IOUTA, IOUTB and I

REF

; V

DIFF

can

be expressed as:

DIFF

= {(2 DAC CODE 16383)/16384}

DIFF

= {

(32 R

LOAD

SET

)

REFIO

(8)

DIGITAL DATA INPUTS (DB13DB0)

150pF

+1.20V REF

AVDD

ACOM

REFLO

ICOMP

PMOS

CURRENT SOURCE

ARRAY

+5V

SEGMENTED SWITCHES

FOR DB13DB5

LSB

SWITCHES

REFIO

FS ADJ

DVDD

DCOM

CLOCK

+5V

SET

0.1 F

IOUTA

IOUTB

0.1 F

AD9754

SLEEP

LATCHES

REF

REFIO

CLOCK

OUTB

OUTA

LOAD

OUTB

OUTA

LOAD

DIFF

= V

OUTA

 V

OUTB

Figure 16. Functional Block Diagram

AD9754

REV. A

These last two equations highlight some of the advantages of
operating the AD9754 differentially. First, the differential op-
eration will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion and dc off-
sets. Second, the differential code-dependent current and
subsequent voltage, V

DIFF

, is twice the value of the single-

ended voltage output (i.e., V

OUTA

or V

OUTB

), thus providing

twice the signal power to the load.

Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (V

DIFF

) of

the AD9754 can be enhanced by selecting temperature tracking
resistors for R

LOAD

and R

SET

due to their ratiometric relation-

ship as shown in Equation 8.

REFERENCE OPERATION

The AD9754 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external
reference. REFIO serves as either an input or output, depending
on whether the internal or external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 17, the internal
reference is activated, and REFIO provides a 1.20 V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1

F or greater from REFIO

to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100 nA if any
additional loading is required.

150pF

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

+5V

REFIO

FS ADJ

0.1 F

AD9754

ADDITIONAL

LOAD

OPTIONAL

EXTERNAL

REF BUFFER

Figure 17. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 18. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1

F compensation capacitor is not required

since the internal reference is disabled, and the high input im-
pedance (i.e., 1 M

) of REFIO minimizes any loading of the

external reference.

REFERENCE CONTROL AMPLIFIER

The AD9754 also contains an internal control amplifier that is
used to regulate the DAC's full-scale output current, I

OUTFS

The control amplifier is configured as a V-I converter, as shown
in Figure 18, such that its current output, I

REF

, is determined by

150pF

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9754

EXTERNAL

REF

REFIO

SET

AVDD

REFERENCE
CONTROL
AMPLIFIER

REFIO

Figure 18. External Reference Configuration

the ratio of the V

REFIO

and an external resistor, R

SET

, as stated

in Equation 4. I

REF

is copied over to the segmented current

sources with the proper scaling factor to set I

OUTFS

as stated in

Equation 3.

The control amplifier allows a wide (10:1) adjustment span of
I

OUTFS

over a 2 mA to 20 mA range by setting IREF between

62.5

A and 625

A. The wide adjustment span of I

OUTFS

provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9754, which is pro-
portional to I

OUTFS

(refer to the Power Dissipation section). The

second benefit relates to the 20 dB adjustment, which is useful
for system gain control purposes.

The small signal bandwidth of the reference control amplifier
is approximately 0.5 MHz. The output of the control amplifier
is internally compensated via a 150 pF capacitor that limits the
control amplifier small-signal bandwidth and reduces its output
impedance. Since the 3 dB bandwidth corresponds to the
dominant pole, and hence the time constant, the settling time of
the control amplifier to a stepped reference input response can
be approximated In this case, the time constant can be approxi-
mated to be 320 ns.

There are two methods in which I

REF

can be varied for a fixed

SET

. The first method is suitable for a single-supply system in

which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, thus allowing I

REF

to be varied for a fixed R

SET

. Since the

1.2V

150pF

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9754

REF

SET

AVDD

REF

OUT1

OUT2

AGND

DB7DB0

AD7524

AD1580

0.1V TO 1.2V

Figure 19. Single-Supply Gain Control Circuit

AD9754

REV. A

input impedance of REFIO is approximately 1 M

, a simple,

low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 19 using the AD7524 and an external 1.2 V reference,
the AD1580.

The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed, and I

REF

varied by an external voltage, V

, applied to R

SET

via an ampli-

fier. An example of this method is shown in Figure 25 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V

, is

referenced to ACOM and should not exceed 1.2 V. The value of
R

SET

is such that I

REFMAX

and I

REFMIN

do not exceed 62.5

and 625

A, respectively. The associated equations in Figure 20

can be used to determine the value of R

SET

150pF

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9754

REF

1 F

REF

= (1.2 V

)/R

SET

WITH V

REFIO

AND 62.5 A

REF

625A

Figure 20. Dual-Supply Gain Control Circuit

ANALOG OUTPUTS

The AD9754 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-end
or differential operation. IOUTA and IOUTB can be converted
into complementary single-ended voltage outputs, V

OUTA

and

OUTB

, via a load resistor, R

LOAD

, as described in the DAC

Transfer Function section by Equations 5 through 8. The
differential voltage, V

DIFF

, existing between V

OUTA

and V

OUTB

can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.

Figure 21 shows the equivalent analog output circuit of the
AD9754 consisting of a parallel combination of PMOS differen-
tial current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is deter-
mined by the equivalent parallel combination of the PMOS
switches and is typically 100 k

in parallel with 5 pF. Due to

the nature of a PMOS device, the output impedance is also
slightly dependent on the output voltage (i.e., V

OUTA

and V

OUTB

)

and, to a lesser extent, the analog supply voltage, AVDD, and
full-scale current, I

OUTFS

. Although the output impedance's signal

dependency can be a source of dc nonlinearity and ac linearity
(i.e., distortion), its effects can be limited if certain precautions
are noted.

AD9754

AVDD

IOUTA

IOUTB

LOAD

Figure 21. Equivalent Analog Output Circuit

IOUTA and IOUTB also have a negative and positive voltage
compliance range. The negative output compliance range of
1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9754.
The positive output compliance range is slightly dependent on
the full-scale output current, I

OUTFS

. It degrades slightly from its

nominal 1.25 V for an I

OUTFS

= 20 mA to 1.00 V for an I

OUTFS

2 mA. Operation beyond the positive compliance range will
induce clipping of the output signal which severely degrades
the AD9754's linearity and distortion performance.

For applications requiring the optimum dc linearity, IOUTA
and/or IOUTB should be maintained at a virtual ground via an
I-V op amp configuration. Maintaining IOUTA and/or IOUTB
at a virtual ground keeps the output impedance of the AD9754
fixed, significantly reducing its effect on linearity. However,
it does not necessarily lead to the optimum distortion perfor-
mance due to limitations of the I-V op amp. Note that the
INL/DNL specifications for the AD9754 are measured in
this manner using IOUTA. In addition, these dc linearity
specifications remain virtually unaffected over the specified
power supply range of +4.5 V to +5.5 V.

Operating the AD9754 with reduced voltage output swings at
IOUTA and IOUTB in a differential or single-ended output
configuration reduces the signal dependency of its output
impedance thus enhancing distortion performance. Although
the voltage compliance range of IOUTA and IOUTB extends
from 1.0 V to +1.25 V, optimum distortion performance is
achieved when the maximum full-scale signal at IOUTA and
IOUTB does not exceed approximately 0.5 V. A properly se-
lected transformer with a grounded center-tap will allow the
AD9754 to provide the required power and voltage levels to
different loads while maintaining reduced voltage swings at
IOUTA and IOUTB. DC-coupled applications requiring a
differential or single-ended output configuration should size
R

LOAD

accordingly. Refer to Applying the AD9754 section for

examples of various output configurations.

AD9754

REV. A

The most significant improvement in the AD9754's distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both
IOUTA and IOUTB can be substantially reduced by the
common-mode rejection of a transformer or differential am-
plifier. These common-mode error sources include even-order
distortion products and noise. The enhancement in distortion
performance becomes more significant as the reconstructed
waveform's frequency content increases and/or its amplitude
decreases.

The distortion and noise performance of the AD9754 is also
slightly dependent on the analog and digital supply as well as the
full-scale current setting, I

OUTFS

. Operating the analog supply at

5.0 V ensures maximum headroom for its internal PMOS current
sources and differential switches leading to improved distortion
performance. Although I

OUTFS

can be set between 2 mA and

20 mA, selecting an I

OUTFS

of 20 mA will provide the best

distortion and noise performance also shown in Figure 13. The
noise performance of the AD9754 is affected by the digital sup-
ply (DVDD), output frequency, and increases with increasing
clock rate as shown in Figure 8. Operating the AD9754 with
low voltage logic levels between 3 V and 3.3 V will slightly
reduce the amount of on-chip digital noise.

In summary, the AD9754 achieves the optimum distortion and
noise performance under the following conditions:

(1) Differential Operation.

(2) Positive voltage swing at IOUTA and IOUTB limited to

+0.5 V.

(3) I

OUTFS

set to 20 mA.

(4) Analog Supply (AVDD) set at 5.0 V.

(5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro-

priate logic levels.

Note that the ac performance of the AD9754 is characterized
under the above mentioned operating conditions.

DIGITAL INPUTS

The AD9754's digital input consists of 14 data input pins and a
clock input pin. The 14-bit parallel data inputs follow standard
positive binary coding where DB13 is the most significant bit
(MSB), and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.

The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulse
width. The setup and hold times can also be varied within the
clock cycle as long as the specified minimum times are met,
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is
typically achieved when the input data transitions on the falling
edge of a 50% duty cycle clock.

The digital inputs are CMOS-compatible with logic thresholds,
V

THRESHOLD,

set to approximately half the digital positive supply

(DVDD) or

THRESHOLD

= DVDD/2 (

20%)

The internal digital circuitry of the AD9754 is capable of operating
over a digital supply range of 2.7 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V

OH(MAX)

. A DVDD of 3 V to 3.3 V will typically ensure

proper compatibility with most TTL logic families. Figure 22
shows the equivalent digital input circuit for the data and clock
inputs. The sleep mode input is similar with the exception that
it contains an active pull-down circuit, thus ensuring that the
AD9754 remains enabled if this input is left disconnected.

DVDD

DIGITAL

INPUT

Figure 22. Equivalent Digital Input

Since the AD9754 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. Operating the AD9754
with reduced logic swings and a corresponding digital supply
(DVDD) will result in the lowest data feedthrough and on-chip
digital noise. The drivers of the digital data interface circuitry
should be specified to meet the minimum setup and hold times
of the AD9754 as well as its required min/max input logic level
thresholds.

Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20

to 100

) between the

AD9754 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to data feedthrough. For longer run lengths and high
data update rates, strip line techniques with proper termination
resistors should be considered to maintain "clean" digital inputs.

The external clock driver circuitry should provide the AD9754
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.

Note, that the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2)
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the effec-
tive clock duty cycle and, subsequently, cut into the required
data setup and hold times.

AD9754

REV. A

INPUT CLOCK AND DATA TIMING RELATIONSHIP

SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9754 is positive edge triggered, and
so exhibits SNR sensitivity when the data transition is close to
this edge. In general, the goal when applying the AD9754 is to
make the data transitions close to the negative clock edge. This
becomes more important as the sample rate increases. Figure 23
shows the relationship of SNR to clock placement.

TIME (ns) OF DATA CHANGE RELATIVE TO

RISING CLOCK EDGE

SNR dB

= 125MSPS

= 65MSPS

Figure 23. SNR vs. Clock Placement @ f

OUT

= 10 MHz

SLEEP MODE OPERATION

The AD9754 has a power-down function that turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 2.7 V to 5.5 V and
temperature range. This mode can be activated by applying a
logic level "1" to the SLEEP pin. This digital input also con-
tains an active pull-down circuit that ensures the AD9754 re-
mains enabled if this input is left disconnected. The AD9754
takes less than 50 ns to power down and approximately 5

s to

power back up.

POWER DISSIPATION

The power dissipation, P

, of the AD9754 is dependent on

several factors, including: (1) AVDD and DVDD, the power
supply voltages; (2) I

OUTFS

, the full-scale current output; (3)

CLOCK

, the update rate; and (4) the reconstructed digital input

waveform. The power dissipation is directly proportional to the
analog supply current, I

AVDD

, and the digital supply current,

DVDD

. I

AVDD

is directly proportional to I

OUTFS,

as shown in

Figure 24, and is insensitive to f

CLOCK

Conversely, I

DVDD

is dependent on both the digital input wave-

form, f

CLOCK

, and digital supply DVDD. Figures 25 and 26

show I

DVDD

as a function of full-scale sine wave output ratios

OUT

CLOCK

) for various update rates with DVDD = 5 V and

DVDD = 3 V, respectively. Note, how I

DVDD

is reduced by more

than a factor of 2 when DVDD is reduced from 5 V to 3 V.

OUTFS

 mA

AVDD

 mA

Figure 24. I

AVDD

vs. I

OUTFS

RATIO (f

CLOCK

OUT

)

0.01

0.1

DVDD

 mA

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 25. I

DVDD

vs. Ratio @ DVDD = 5 V

RATIO (f

CLOCK

OUT

)

0.01

0.1

DVDD

 mA

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 26. I

DVDD

vs. Ratio @ DVDD = 3 V

AD9754

REV. A

APPLYING THE AD9754

OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configura-
tions for the AD9754. Unless otherwise noted, it is assumed
that I

OUTFS

is set to a nominal 20 mA. For applications requir-

ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the opti-
mum high frequency performance and is recommended for any
application allowing for ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling, a
bipolar output, signal gain and/or level shifting.

A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropri-
ately sized load resistor, R

LOAD

, referred to ACOM. This con-

figuration may be more suitable for a single-supply system
requiring a dc coupled, ground referred output voltage. Alterna-
tively, an amplifier could be configured as an I-V converter, thus
converting IOUTA or IOUTB into a negative unipolar voltage.
This configuration provides the best dc linearity since IOUTA
or IOUTB is maintained at a virtual ground. Note, IOUTA
provides slightly better performance than IOUTB.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to-
single-ended signal conversion as shown in Figure 27. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer's passband. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and noise
over a wide frequency range. It also provides electrical isolation
and the ability to deliver twice the power to the load. Trans-
formers with different impedance ratios may also be used for
impedance matching purposes. Note that the transformer
provides ac coupling only.

LOAD

AD9754

MINI-CIRCUITS

T1-1T

OPTIONAL R

DIFF

IOUTA

IOUTB

Figure 27. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., V

OUTA

and V

OUTB

)

swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9754. A
differential resistor, R

DIFF

, may be inserted in applications in

which the output of the transformer is connected to the load,
R

LOAD

, via a passive reconstruction filter or cable. R

DIFF

is deter-

mined by the transformer's impedance ratio and provides the
proper source termination that results in a low VSWR. Note
that approximately half the signal power will be dissipated
across R

DIFF

DIFFERENTIAL USING AN OP AMP

An op amp can also be used to perform a differential-to-single-
ended conversion as shown in Figure 28. The AD9754 is con-
figured with two equal load resistors, R

LOAD

, of 25

. The

differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter.
The addition of this capacitor also enhances the op amp's dis-
tortion performance by preventing the DAC's high slewing
output from overloading the op amp's input.

The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ-
ential op amp circuit is configured to provide some additional
signal gain. The op amp must operate from a dual supply since
its output is approximately

1.0 V. A high speed amplifier such

as the AD8055 or AD9632 capable of preserving the differential

AD9754

IOUTA

IOUTB

OPT

500

225

500

AD8055

Figure 28. DC Differential Coupling Using an Op Amp

performance of the AD9754 while meeting other system level
objectives (i.e., cost, power) should be selected. The op amps
differential gain, its gain setting resistor values and full-scale
output swing capabilities should all be considered when opti-
mizing this circuit.

The differential circuit shown in Figure 29 provides the neces-
sary level-shifting required in a single supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9754 and the op amp, is also used to level-shift the differ-
ential output of the AD9754 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.

AD9754

IOUTA

IOUTB

OPT

500

225

AD8041

AVDD

Figure 29. Single-Supply DC Differential Coupled Circuit

AD9754

REV. A

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 30 shows the AD9754 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50

cable since the nominal full-scale current, I

OUTFS

, of

20 mA flows through the equivalent R

LOAD

of 25

. In this case,

LOAD

represents the equivalent load resistance seen by IOUTA

or IOUTB. The unused output (IOUTA or IOUTB) can be
connected to ACOM directly or via a matching R

LOAD

. Different

values of I

OUTFS

and R

LOAD

can be selected as long as the posi-

tive compliance range is adhered to. One additional consider-
ation in this mode is the integral nonlinearity (INL) as discussed
in the Analog Output section of this data sheet. For optimum
INL performance, the single-ended, buffered voltage output
configuration is suggested.

AD9754

IOUTA

IOUTB

OUTA

= 0 TO +0.5V

OUTFS

= 20mA

Figure 30. 0 V to +0.5 V Unbuffered Voltage Output

SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
CONFIGURATION

Figure 31 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9754
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, thus minimizing the nonlinear output impedance effect
on the DAC's INL performance as discussed in the Analog
Output section. Although this single-ended configuration typi-
cally provides the best dc linearity performance, its ac distortion
performance at higher DAC update rates may be limited by
U1's slewing capabilities. U1 provides a negative unipolar
output voltage and its full-scale output voltage is simply the
product of R

and I

OUTFS

. The full-scale output should be set

within U1's voltage output swing capabilities by scaling I

OUTFS

and/or R

. An improvement in ac distortion performance may

result with a reduced I

OUTFS

since the signal current U1 will be

required to sink will be subsequently reduced.

AD9754

IOUTA

IOUTB

OPT

200

OUT

= I

OUTFS

= 10mA

200

Figure 31. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS, POWER
SUPPLY REJECTION

Many applications seek high speed and high performance under
less than ideal operating conditions. In these circuits, the imple-
mentation and construction of the printed circuit board design
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figures 39-44 illustrate the recommended printed
circuit board ground, power and signal plane layouts which are
implemented on the AD9754 evaluation board.

One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution
(i.e., AVDD, DVDD). This is referred to as Power Supply
Rejection Ratio (PSRR). For dc variations of the power supply,
the resulting performance of the DAC directly corresponds to a
gain error associated with the DAC's full-scale current, I

OUTFS

AC noise on the dc supplies is common in applications where
the power distribution is generated by a switching power supply.
Typically, switching power supply noise will occur over the
spectrum from tens of kHz to several MHz. PSRR vs. frequency
of the AD9754 AVDD supply, over this frequency range, is
given in Figure 32.

FREQUENCY MHz

PSRR dB

1.0

0.5

0.75

0.26

Figure 32. Power Supply Rejection Ratio of AD9754

Note that the units in Figure 32 are given in units of (amps out)/
(volts in). Noise on the analog power supply has the effect of
modulating the internal switches, and therefore the output
current. The voltage noise on the dc power, therefore, will be
added in a nonlinear manner to the desired I

OUT

. Due to the

relative different sizes of these switches, PSRR is very code
dependent. This can produce a mixing effect which can modu-
late low frequency power supply noise to higher frequencies.
Worst case PSRR for either one of the differential DAC outputs
will occur when the full-scale current is directed towards that
output. As a result, the PSRR measurement in Figure 32 repre-
sents a worst case condition in which the digital inputs remain
static and the full-scale output current of 20 mA is directed to
the DAC output being measured.

AD9754

REV. A

An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV rms of noise and for
simplicity sake (i.e., ignore harmonics), all of this noise is con-
centrated at 250 kHz. To calculate how much of this undesired
noise will appear as current noise super imposed on the DAC's
full-scale current, I

OUTFS

, one must determine the PSRR in dB

using Figure 32 at 250 kHz. To calculate the PSRR for a given
R

LOAD

, such that the units of PSRR are converted from A/V to

V/V, adjust the curve in Figure 32 by the scaling factor 20

Log

LOAD

). For instance, if R

LOAD

is 50

, the PSRR is reduced

by 34 dB (i.e., PSRR of the DAC at 1 MHz which is 74 dB in
Figure 32 becomes 40 dB V

OUT

Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9754 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physi-
cally possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close as physically as possible.

For those applications requiring a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 33. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.

100 F
ELECT.

10-22 F
TANT.

0.1 F
CER.

TTL/CMOS

LOGIC

CIRCUITS

+5V OR +3V

POWER SUPPLY

FERRITE

BEADS

AVDD

ACOM

Figure 33. Differential LC Filter for Single +5 V or +3 V
Applications

Maintaining low noise on power supplies and ground is critical
to obtain optimum results from the AD9754. If properly
implemented, ground planes can perform a host of functions on
high speed circuit boards: bypassing, shielding current trans-
port, etc. In mixed signal design, the analog and digital portions
of the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined to areas covering
the digital interconnects.

All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8 to
1/4 inch wide underneath or within 1/2 inch of the DAC to
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC as well as any clock signals. On the analog side, this
includes the DAC output signal, reference signal and the supply
feeders.

The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part, as well as providing
some "free" capacitive decoupling to the appropriate ground
plane. It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous volt-
age drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the pack-
age as possible in order to minimize the sharing of conduction
paths between different currents. When runs exceed an inch in
length, strip line techniques with proper termination resistors
should be considered. The necessity and value of this resistor
will be dependent upon the logic family used.

For a more detailed discussion of the implementation and
construction of high speed, mixed signal printed circuit boards,
refer to Analog Devices' application notes AN-280 and AN-333.

MULTITONE PERFORMANCE CONSIDERATIONS AND
CHARACTERIZATION

The frequency domain performance of high speed DACs has
traditionally been characterized by analyzing the spectral output
of a reconstructed full-scale (i.e., 0 dBFS), single-tone sine wave
at a particular output frequency and update rate. Although this
characterization data is useful, it is often insufficient to reflect a
DAC's performance for a reconstructed multitone or spread-
spectrum waveform. In fact, evaluating a DAC's spectral
performance using a full-scale, single tone at the highest specified
frequency (i.e., f

) of a bandlimited waveform is typically

indicative of a DAC's "worst-case" performance for that given
waveform. In the time domain, this full-scale sine wave represents
the lowest peak-to-rms ratio or crest factor (i.e., V

PEAK

/V rms)

that this bandlimited signal will encounter.

MAGNITUDE dBm

FREQUENCY MHz

10

70

110

2.19

2.81

2.25 2.31

2.38 2.44

2.50 2.56

2.63 2.69

2.75

20

60

80

100

40

50

90

30

Figure 34a. Multitone Spectral Plot

However, the inherent nature of a multitone, spread spectrum,
or QAM waveform, in which the spectral energy of the wave-
form is spread over a designated bandwidth, will result in a
higher peak-to-rms ratio when compared to the case of a simple
sine wave. As the reconstructed waveform's peak-to-average
ratio increases, an increasing amount of the signal energy is
concentrated around the DAC's midscale value. Figure 34a is
just one example of a bandlimited multitone vector (i.e., eight
tones) centered around one-half the Nyquist bandwidth (i.e.,

AD9754

REV. A

CLOCK

/4). This particular multitone vector, has a peak-to-rms

ratio of 13.5 dB compared to a sine waves peak-to-rms ratio of
3 dB. A "snapshot" of this reconstructed multitone vector in the
time domain as shown in Figure 34b reveals the higher signal
content around the midscale value. As a result, a DAC's "small-
scale" dynamic and static linearity becomes increasingly criti-
cal in obtaining low intermodulation distortion and maintaining
sufficient carrier-to-noise ratios for a given modulation scheme.

A DAC's small-scale linearity performance is also an important
consideration in applications where additive dynamic range is
required for gain control purposes or "predistortion" signal
conditioning. For instance, a DAC with sufficient dynamic
range can be used to provide additional gain control of its
reconstructed signal. In fact, the gain can be controlled in
6 dB increments by simply performing a shift left or right on the
DAC's digital input word. Other applications may intentionally

TIME

1.0000

0.8000

1.0000

VOLTS

0.2000

0.4000

0.6000

0.8000

0.2000

0.0000

0.4000

0.6000

Figure 34b. Time Domain "Snapshot" of the Multitone
Waveform

predistort a DAC's digital input signal to compensate for
nonlinearities associated with the subsequent analog compo-
nents in the signal chain. For example, the signal compression
associated with a power amplifier can be compensated for by
predistorting the DAC's digital input with the inverse nonlinear
transfer function of the power amplifier. In either case, the
DAC's performance at reduced signal levels should be carefully
evaluated.

A full-scale single tone will induce all of the dynamic and static
nonlinearities present in a DAC that contribute to its distortion
and hence SFDR performance. Referring to Figure 3, as the
frequency of this reconstructed full-scale, single-tone waveform
increases, the dynamic nonlinearities of any DAC (i.e., AD9754)
tend to dominate thus contributing to the roll-off in its SFDR
performance. However, unlike most DACs, which employ an R-2R
ladder for the lower bit current segmentation, the AD9754 (as

well as other TxDAC members) exhibits an improvement in
distortion performance as the amplitude of a single tone is re-
duced from its full-scale level. This improvement in distortion
performance at reduced signal levels is evident if one compares
the SFDR performance vs. frequency at different amplitudes
(i.e., 0 dBFS, 6 dBFS and 12 dBFS) and sample rates as
shown in Figures 4 through 7. Maintaining decent "small-scale"
linearity across the full span of a DAC transfer function is also
critical in maintaining excellent multitone performance.

Although characterizing a DAC's multitone performance tends
to be application-specific, much insight into the potential perfor-
mance of a DAC can also be gained by evaluating the DAC's
swept power (i.e., amplitude) performance for single, dual and
multitone test vectors at different clock rates and carrier frequen-
cies. The DAC is evaluated at different clock rates when recon-
structing a specific waveform whose amplitude is decreased in
3 dB increments from full-scale (i.e., 0 dBFS). For each specific
waveform, a graph showing the SFDR (over Nyquist) perfor-
mance vs. amplitude can be generated at the different tested
clock rates as shown in Figures 911. Note that the carrier(s)-to-
clock ratio remains constant in each figure. In each case, an
improvement in SFDR performance is seen as the amplitude is
reduced from 0 dBFS to approximately 9.0 dBFS.

A multitone test vector may consist of several equal amplitude,
spaced carriers each representative of a channel within a defined
bandwidth as shown in Figure 37a. In many cases, one or more
tones are removed so the intermodulation distortion performance
of the DAC can be evaluated. Nonlinearities associated with the
DAC will create spurious tones of which some may fall back into
the "empty" channel thus limiting a channel's carrier-to-noise
ratio. Other spurious components falling outside the band of
interest may also be important, depending on the system's spectral
mask and filtering requirements.

This particular test vector was centered around one-half the
Nyquist bandwidth (i.e., f

CLOCK

/4) with a passband of f

CLOCK

/16.

Centering the tones at a much lower region (i.e., f

CLOCK

/10)

would lead to an improvement in performance while centering
the tones at a higher region (i.e., f

CLOCK

/2.5) would result in a

degradation in performance.

AD9754

REV. A

APPLICATIONS
VDSL Applications Using the AD9754

Very High Frequency Digital Subscriber Line (VDSL) technol-
ogy is growing rapidly in applications requiring data transfer
over relatively short distances. By using QAM modulation and
transmitting the data in multiple discrete tones, high data rates
can be achieved.

As with other multitone applications, each VDSL tone is ca-
pable of transmitting a given number of bits, depending on the
signal to noise ratio (SNR) in a narrow band around that tone.
The tones are evenly spaced over the range of several kHz to
10 MHz. At the high frequency end of this range, performance
is generally limited by cable characteristics and environmental
factors, such as external interferers. Performance at the lower
frequencies is much more dependent on the performance of the
components in the signal chain. In addition to in-band noise,
intermodulation from other tones can also potentially interfere
with the recovery of data for a given tone. The two graphs in
Figure 35 represent a 500 tone missing bin test vector, with
frequencies evenly spaced from 400 Hz to 10 MHz. This test is
very commonly done to determine if distortion will limit the
number of bits which can transmitted in a tone. The test vector
has a series of missing tones around 750 kHz, which is represented
in Figure 35a, and a series of missing tones around 5 MHz,
which is represented in Figure 35b. In both cases, the spurious
free range between the transmitted tones and the empty bins is
greater than 60 dB.

FREQUENCY Hz

AMPLITUDE dBm

30

50

110

70

90

600k

800k

1.0M

40

60

80

100

Figure 35a. Notch in missing bin at 750 kHz is down
>60 dB. Peak amplitude = 0 dBm.

FREQUENCY MHz

AMPLITUDE dBm

30

50

110

70

90

4.8

5.0

5.2

40

60

80

100

Figure 35b. Notch in missing bin at 5 MHz is down
>60 dB. Peak amplitude = 0 dBm.

CDMA

Carrier Division Multiple Access, or CDMA, is an air transmit/
receive scheme where the signal in the transmit path is modu-
lated with a pseudorandom digital code (sometimes referred to
as the spreading code). The effect of this is to spread the trans-
mitted signal across a wide spectrum. Similar to a DMT wave-
form, a CDMA waveform containing multiple subscribers can
be characterized as having a high peak to average ratio (i.e.,
crest factor), thus demanding highly linear components in the
transmit signal path. The bandwidth of the spectrum is defined
by the CDMA standard being used, and in operation is imple-
mented by using a spreading code with particular characteristics.

Distortion in the transmit path can lead to power being trans-
mitted out of the defined band. The ratio of power transmitted
in-band to out-of-band is often referred to as Adjacent Channel
Power (ACP). This is a regulatory issue due to the possibility of
interference with other signals being transmitted by air. Regula-
tory bodies define a spectral mask outside of the transmit band,
and the ACP must fall under this mask. If distortion in the
transmit path cause the ACP to be above the spectral mask,
then filtering, or different component selection is needed to
meet the mask requirements.

Figure 36 shows an example of the AD9754 used in a W-CDMA
transmitter application using the AD6122 CDMA 3 V transmit-
ter IF subsystem. The AD6122 has functions, such as external
gain control and low distortion characteristics, needed for the
superior Adjacent Channel Power (ACP) requirements of
WCDMA.

AD9754

REV. A

Figure 37 shows the AD9754 reconstructing a wideband, or
W-CDMA test vector with a bandwidth of 5 MHz, centered at
15.625 MHz and being sampled at 62.5 MSPS. ACP for the
given test vector is measured at 70 dB.

FREQUENCY MHz

REFERENCE LEVEL dBm

30

50

110

70

90

13.125

15.625

18.125

40

60

80

100

20

120

Figure 37. CDMA Signal, Sampled at 65 MSPS, Adjacent
Channel Power >70 dB

AD9754 EVALUATION BOARD
General Description

The AD9754-EB is an evaluation board for the AD9754 14-bit
DAC converter. Careful attention to layout and circuit design,
combined with a prototyping area, allows the user to easily and
effectively evaluate the AD9754 in any application where high
resolution, high speed conversion is required.

This board allows the user the flexibility to operate the AD9754
in various configurations. Possible output configurations in-
clude transformer coupled, resistor terminated, inverting/
noninverting and differential amplifier outputs. The digital inputs
are designed to be driven directly from various word generators
with the onboard option to add a resistor network for proper
load termination. Provisions are also made to operate the
AD9754 with either the internal or external reference or to
exercise the power-down feature.

Refer to the application note AN-420 for a thorough description
and operating instructions for the AD9754 evaluation board.

AD9754

("I DAC")

AD9754

("Q DAC")

IOUTA

IOUTB

QOUTA

QOUTB

DCOM

FSADJ

REFIO

SLEEP

SET2

1.9k

0.1 F

CLK

Q DATA

INPUT

I DATA

INPUT

DVDD

AVDD

100W

500

100

FILTER

100

500

634

+3V

IIPP

IIPN

IIQP

IIQN

AD6122

REFLO

ACOM

REFLO

AVDD

REFIO

FSADJ

SET1

CAL

220

AVDD

LATCHES

500

DAC

LATCHES

100

TEMPERATURE

COMPENSATION

GAIN

CONTROL

SCALE

FACTOR

REFIN

VGAIN

GAIN

CONTROL

LOIPP
LOIPN

TXOPP

TXOPN

PHASE

SPLITTER

MODOPP

MODOPN

Figure 36. CDMA Transmit Application Using AD9754

AD9754

REV. A

Figure 38. Evaluation Board Schematic

10
9
8
7
6
5
4
3
2

DVDD

10
9
8
7
6
5
4
3
2

DVDD

10
9
8
7
6
5
4
3
2

DVDD

10
9
8
7
6
5
4
3
2

C19

C25

C26

C27

C28

C29

16 PINDIP

RES PK

C30

C31

C32

C33

C34

C35

C36

16 PINDIP

RES PK

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CLOCK

DVDD

DCOM

AVDD

ICOMP

IOUTA

IOUTB

ACOM

FS ADJ

REFIO

REFLO

SLEEP

AD975x

AVDD

CT1

R15

49.9

CLK

JP1

TP1

EXTCLK

0.1

AVDD

0.1

TP8

AVDD

TP11

C11

0.1

TP10

TP9

R16

TP14

JP4

C10

0.1

OUT 1

OUT 2

TP13

R17

49.9

PDIN

AVDD

JP2

TP12

TP7

AVCC

TP6

AVEE

TP19

AGND

TP18

TP5

TP4

AVDD

TP2

DGND

TP3

DVDD

R20

49.9

C12

22pF

R14

R38

49.9

JP6A

JP6B

R13

OPEN

C13

22pF

C20

R12

OPEN

JP7B

JP7A

R10

JP8

R35

JP9

R18

AD8047

C21

0.1

C22

R36

C23

0.1

C24

AVEE

AVCC

R37

49.9

JP5

C15

0.1

AVEE

R46

C17

0.1

JP3

AVCC

R43

R45

C14

R44

EXTREFIN

R42

C16

AVCC

C18

0.1

VIN

VOUT

GND

REF43

DVDD

AD8047

OUT2

OUT1

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