REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD9762*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

12-Bit, 125 MSPS

TxDAC

D/A Converter

FUNCTIONAL BLOCK DIAGRAM

50pF

COMP1

+1.20V REF

AVDD

ACOM

REFLO

COMP2

CURRENT

SOURCE

ARRAY

0.1 F

+5V

SEGMENTED

SWITCHES

LSB

SWITCHES

REFIO

FS ADJ

DVDD

DCOM

CLOCK

+5V

SET

0.1 F

CLOCK

IOUTA

IOUTB

0.1 F

LATCHES

AD9762

SLEEP

DIGITAL DATA INPUTS (DB11DB0)

FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
12-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 5 MHz Output: 70 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Package: 28-Lead SOIC and TSSOP
Edge-Triggered Latches

APPLICATIONS
Communication Transmit Channel:

Basestations (Single/Multichannel Applications)
ADSL/HFC Modems

Direct Digital Synthesis (DDS)
Instrumentation

PRODUCT DESCRIPTION

The AD9762 is the 12-bit resolution member of the TxDAC
series of high performance, low power CMOS digital-to-analog
converters (DACs). The TxDAC

family which consists of pin

compatible 8-, 10-, 12-, and 14-bit DACs is specifically opti-
mized for the transmit signal path of communication systems.
All of the devices share the same interface options, small outline
package and pinout, thus providing an upward or downward
component selection path based on performance, resolution and
cost. The AD9762 offers exceptional ac and dc performance
while supporting update rates up to 125 MSPS.

The AD9762's flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.

The AD9762 is manufactured on an advanced CMOS process.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Edge-triggered input
latches and a 1.2 V temperature compensated bandgap refer-
ence have been integrated to provide a complete monolithic
DAC solution. Flexible supply options support +3 V and +5 V
CMOS logic families.

The AD9762 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 k

output impedance.

TxDAC is a registered trademark of Analog Devices, Inc.
*Patent pending.

Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.

The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9762 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier which provides a wide
(>10:1) adjustment span allows the AD9762 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9762 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.

The AD9762 is available in 28-lead SOIC and TSSOP pack-
ages. It is specified for operation over the industrial tempera-
ture range.

PRODUCT HIGHLIGHTS

1. The AD9762 is a member of the TxDAC

product family which

provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.

2. Manufactured on a CMOS process, the AD9762 uses a pro-

prietary switching technique that enhances dynamic perfor-
mance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.

3. On-chip, edge-triggered input CMOS latches interface readily

to +3 V and +5 V CMOS logic families. The AD9762 can
support update rates up to 125 MSPS.

4. A flexible single-supply operating range of 2.7 V to 5.5 V and

a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9762 to operate at reduced power levels.

5. The current output(s) of the AD9762 can be easily config-

ured for various single-ended or differential circuit topologies.

DC SPECIFICATIONS

Parameter

Min

Typ

Max

Units

RESOLUTION

Bits

DC ACCURACY

Integral Linearity Error (INL)

= +25

°C

2.5

±0.75

+2.5

LSB

MIN

to T

MAX

4.0

±1.0

+4.0

LSB

Differential Nonlinearity (DNL)

= +25

°C

1.5

±0.5

+1.5

LSB

MIN

to T

MAX

2.0

±0.75

+2.0

LSB

ANALOG OUTPUT

Offset Error

0.025

+0.025

% of FSR

Gain Error

(Without Internal Reference)

±2

+10

% of FSR

Gain Error

(With Internal Reference)

±1

+10

% of FSR

Full-Scale Output Current

2.0

20.0

Output Compliance Range

1.0

+1.25

Output Resistance

100

Output Capacitance

REFERENCE OUTPUT

Reference Voltage

1.08

1.20

1.32

Reference Output Current

100

REFERENCE INPUT

Input Compliance Range

0.1

1.25

Reference Input Resistance

Small Signal Bandwidth (w/o C

COMP1

)

1.4

MHz

TEMPERATURE COEFFICIENTS

Offset Drift

ppm of FSR/

°C

Gain Drift

(Without Internal Reference)

±50

ppm of FSR/

°C

Gain Drift

(With Internal Reference)

±100

ppm of FSR/

°C

Reference Voltage Drift

±50

ppm/

°C

POWER SUPPLY

Supply Voltages

AVDD

2.7

5.0

5.5

DVDD

2.7

5.0

5.5

Analog Supply Current (I

AVDD

)

Digital Supply Current (I

DVDD

)

1.5

Supply Current Sleep Mode (I

AVDD

)

8.5

Power Dissipation

(5 V, I

OUTFS

= 20 mA)

133

160

Power Dissipation

(5 V, I

OUTFS

= 20 mA)

190

Power Dissipation

(3 V, I

OUTFS

= 2 mA)

Power Supply Rejection Ratio--AVDD

0.4

+0.4

% of FSR/V

Power Supply Rejection Ratio--DVDD

0.025

+0.025

% of FSR/V

OPERATING RANGE

+85

°C

NOTES

Measured at IOUTA, driving a virtual ground.

Nominal full-scale current, I

OUTFS

, is 32

× the I

REF

current.

Use an external buffer amplifier to drive any external load.

Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.

For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.

Measured at f

CLOCK

= 25 MSPS and f

OUT

= 1.0 MHz.

Measured as unbuffered voltage output into 50

LOAD

at IOUTA and IOUTB, f

CLOCK

= 100 MSPS and f

OUT

= 40 MHz.

Specifications subject to change without notice.

MIN

to T

MAX

, AVDD = +5 V, DVDD = +5 V, I

OUTFS

= 20 mA, unless otherwise noted)

REV. B

AD9762SPECIFICATIONS

DYNAMIC SPECIFICATIONS

Parameter

Min

Typ

Max

Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f

CLOCK

)

125

MSPS

Output Settling Time (t

) (to 0.1%)

Output Propagation Delay (t

)

Glitch Impulse

pV-s

Output Rise Time (10% to 90%)

2.5

Output Fall Time (10% to 90%)

2.5

Output Noise (I

OUTFS

= 20 mA)

pA/

Output Noise (I

OUTFS

= 2 mA)

pA/

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

CLOCK

= 25 MSPS; f

OUT

= 1.00 MHz

= +25

°C

dBc

MIN

to T

MAX

dBc

CLOCK

= 50 MSPS; f

OUT

= 1.00 MHz

dBc

CLOCK

= 50 MSPS; f

OUT

= 2.51 MHz

dBc

CLOCK

= 50 MSPS; f

OUT

= 5.02 MHz

dBc

CLOCK

= 50 MSPS; f

OUT

= 20.2 MHz

dBc

CLOCK

= 100 MSPS; f

OUT

= 2.51 MHz

dBc

CLOCK

= 100 MSPS; f

OUT

= 5.04 MHz

dBc

CLOCK

= 100 MSPS; f

OUT

= 20.2 MHz

dBc

CLOCK

= 100 MSPS; f

OUT

= 40.4 MHz

dBc

Spurious-Free Dynamic Range within a Window

CLOCK

= 25 MSPS; f

OUT

=1.00 MHz; 2 MHz Span

= +25

°C

dBc

MIN

to T

MAX

dBc

CLOCK

= 50 MSPS; f

OUT

= 5.02 MHz; 2 MHz Span

dBc

CLOCK

= 100 MSPS; f

OUT

= 5.04 MHz; 4 MHz Span

dBc

Total Harmonic Distortion

CLOCK

= 25 MSPS; f

OUT

= 1.00 MHz

= +25

°C

dBc

MIN

to T

MAX

dBc

CLOCK

= 50 MHz; f

OUT

= 2.00 MHz

dBc

CLOCK

= 100 MHz; f

OUT

= 2.00 MHz

dBc

Multitone Power Ratio (8 Tones at 110 kHz Spacing)

CLOCK

= 20 MSPS; f

OUT

= 2.00 MHz to 2.99 MHz

dBc

NOTES

Measured single ended into 50

load.

Specifications subject to change without notice.

MIN

to T

MAX

, AVDD = +5 V, DVDD = +5 V, I

OUTFS

= 20 mA, Differential Transformer Coupled Output,

Doubly Terminated, unless otherwise noted)

AD9762

REV. B

AD9762

REV. B

DIGITAL SPECIFICATIONS

Parameter

Min

Typ

Max

Units

DIGITAL INPUTS

Logic "1" Voltage @ DVDD = +5 V

3.5

Logic "1" Voltage @ DVDD = +3 V

2.1

Logic "0" Voltage @ DVDD = +5 V

1.3

Logic "0" Voltage @ DVDD = +3 V

0.9

Logic "1" Current

+10

µA

Logic "0" Current

+10

µA

Input Capacitance

Input Setup Time (t

)

2.0

Input Hold Time (t

)

1.5

Latch Pulsewidth (t

LPW

)

3.5

Specifications subject to change without notice.

0.1%

LPW

DB0DB11

CLOCK

IOUTA

IOUTB

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

With

Parameter

Respect to

Min

Max

Units

AVDD

ACOM

0.3

+6.5

DVDD

DCOM

0.3

+6.5

ACOM

DCOM

0.3

+0.3

AVDD

DVDD

6.5

+6.5

CLOCK, SLEEP

DCOM

0.3

DVDD + 0.3

Digital Inputs

DCOM

0.3

DVDD + 0.3

IOUTA, IOUTB

ACOM

1.0

AVDD + 0.3

COMP1, COMP2

ACOM

0.3

AVDD + 0.3

REFIO, FSADJ

ACOM

0.3

AVDD + 0.3

REFLO

ACOM

0.3

+0.3

Junction Temperature

+150

°C

Storage Temperature

+150

°C

Lead Temperature

(10 sec)

+300

°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option*

AD9762AR

°C to +85°C 28-Lead 300 mil SOIC R-28

AD9762ARU 40

°C to +85°C 28-Lead TSSOP

RU-28

AD9762-EB

Evaluation Board

*R = SOIC, RU = TSSOP.

THERMAL CHARACTERISTICS
Thermal Resistance

28-Lead 300 mil SOIC

= 71.4

°C/W

= 23

°C/W

28-Lead TSSOP

= 97.9

°C/W

= 14.0

°C/W

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9762 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

MIN

to T

MAX

, AVDD = +5 V, DVDD = +5 V, I

OUTFS

= 20 mA unless otherwise noted)

WARNING!

ESD SENSITIVE DEVICE

AD9762

REV. B

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD9762

NC = NO CONNECT

(MSB) DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CLOCK

DVDD

DCOM

AVDD

COMP2

IOUTA

IOUTB

ACOM

COMP1

FS ADJ

REFIO

REFLO

SLEEP

PIN DESCRIPTIONS

Pin No.

Name

Description

DB11

Most Significant Data Bit (MSB).

211

DB10DB1 Data Bits 110.

DB0

Least Significant Data Bit (LSB).

13, 14, 25 NC

No Internal Connection.

SLEEP

Power-down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if
not used.

REFLO

Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.

REFIO

Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1

µF capacitor to ACOM when internal reference activated.

FS ADJ

Full-Scale Current Output Adjust.

COMP1

Bandwidth/Noise Reduction Node. Add 0.1

µF to AVDD for optimum performance.

ACOM

Analog Common.

IOUTB

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

IOUTA

DAC Current Output. Full-scale current when all data bits are 1s.

COMP2

Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1

µF capacitor.

AVDD

Analog Supply Voltage (+2.7 V to +5.5 V).

DCOM

Digital Common.

DVDD

Digital Supply Voltage (+2.7 V to +5.5 V).

CLOCK

Clock Input. Data latched on positive edge of clock.

AD9762

REV. B

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For I

OUTA

, 0 mA output is expected when the

inputs are all 0s. For I

OUTB

, 0 mA output is expected when all

inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (+25

°C) value to the value at either T

MIN

or T

MAX

. For

offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).

Multitone Power Ratio

The spurious-free dynamic range for an output containing mul-
tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.

50pF

COMP1

+1.20V REF

AVDD

ACOM

REFLO

COMP2

PMOS

CURRENT SOURCE

ARRAY

0.1 F

+5V

SEGMENTED SWITCHES

FOR DB11DB3

LSB

SWITCHES

REFIO

FS ADJ

DVDD

DCOM

CLOCK

+5V

SET

0.1 F

DVDD

DCOM

IOUTA

IOUTB

0.1 F

AD9762

SLEEP

RETIMED

CLOCK

OUTPUT*

LATCHES

DIGITAL

DATA

TEKTRONIX

AWG-2021

LECROY 9210

PULSE GENERATOR

CLOCK

OUTPUT

20pF

100

TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50 INPUT

MINI-CIRCUITS

T1-1T

* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.

Figure 2. Basic AC Characterization Test Set-Up

AD9762

REV. B

Typical AC Characterization Curves @ +5 V Supplies

(AVDD = +5 V, DVDD = +5 V, I

OUTFS

= 20 mA, 50

Doubly Terminated Load, Differential Output, T

= +25 C, SFDR up to Nyquist, unless otherwise noted)

FREQUENCY MHz

SFDR

dBc

0.1

100

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 3. SFDR vs. f

OUT

@ 0 dBFS

FREQUENCY MHz

SFDR

dBc

0.00

5.00

25.00

10.00

15.00

20.00

0dBFS

6dBFS

12dBFS

Figure 6. SFDR vs. f

OUT

@ 50 MSPS

OUT

 dBFS

SFDR

dBc

30

25

20

15

10

455kHz

@ 5MSPS

2.27MHz

@ 25MSPS

4.55MHz
@ 50MSPS

9.1MHz
@ 100MSPS

11.37MHz

@ 125MSPS

Figure 9. Single-Tone SFDR vs. A

OUT

@ f

OUT

= f

CLOCK

/11

FREQUENCY MHz

SFDR

dBc

0.00

2.50

0.50

1.00

1.50

2.00

0dBFS

6dBFS

12dBFS

Figure 4. SFDR vs. f

OUT

@ 5 MSPS

FREQUENCY MHz

SFDR

dBc

0.00

10.00

50.00

20.00

30.00

40.00

0dBFS

6dBFS

12dBFS

Figure 7. SFDR vs. f

OUT

@100 MSPS

OUT

 dBFS

SFDR

dBc

30

25

20

15

10

1MHz

@ 5MSPS

5.0MHz

@ 25MSPS

10MHz

@ 50MSPS

20MHz

@ 100MSPS

25MHz

@ 125MSPS

Figure 10. Single-Tone SFDR vs.
A

OUT

@ f

OUT

= f

CLOCK

FREQUENCY MHz

SFDR

dBc

0.00

2.00

12.00

4.00

6.00

8.00

10.00

0dBFS

6dBFS

12dBFS

Figure 5. SFDR vs. f

OUT

@ 25 MSPS

FREQUENCY MHz

SFDR

dBc

0.00 10.00

60.00

20.00 30.00

40.00 50.00

0dBFS

6dBFS

12dBFS

Figure 8. SFDR vs. f

OUT

@ 125 MSPS

OUT

 dBFS

SFDR

dBc

30

25

20

15

10

0.675/0.725MHz

@ 5MSPS

3.38/3.63MHz

@ 25MSPS

6.75/7.25MHz
@ 50MSPS

13.5/14.5MHz
@ 100MSPS

16.9/18.1MHz

@ 125MSPS

Figure 11. Dual-Tone SFDR vs. A

OUT

@ f

OUT

= f

CLOCK

AD9762

REV. B

FREQUENCY MSPS

dBc

70

75

95

140

100

120

80

85

90

2ND
HARMONIC

3RD

HARMONIC

4TH
HARMONIC

Figure 12. THD vs. f

CLOCK

OUT

= 2 MHz

1.25

0.50

1.25

4000

ERROR

LSB

1000

2000

3000

1.00

0.25

0.75

0.50

1.00

0.75

CODE

Figure 15. Typical INL

10dB

Div

100

START: 0.3 MHz

STOP: 50.0 MHz

CLOCK

= 100 MSPS

OUT

= 2.41MHz

SFDR = 72dBc
AMPLITUDE = 0dBFS

Figure 18. Single-Tone SFDR

OUTFS

 mA

SFDR

dBc

2.5MHz

10MHz

22.2MHz

40MHz

Figure 13. SFDR vs. f

OUT

and I

OUTFS

@ 100 MSPS, 0 dBFS

0.4

4000

ERROR

LSB

1000

2000

3000

0.8

0.2

0.4

0.6

CODE

Figure 16. Typical DNL

10dB

Div

100

START: 0.3 MHz

STOP: 50.0 MHz

CLOCK

= 100 MSPS

OUT1

= 13.5MHz

OUT2

= 14.5MHz

SFDR = 62dBc
AMPLITUDE = 0dBFS

Figure 19. Dual-Tone SFDR

OUTPUT FREQUENCY MHz

SFDR

dBc

100

IDIFF @ 6dBFS

IDIFF @ 0dBFS

IOUTA @ 6dBFS

IOUTA @ 0dBFS

Figure 14. Differential vs. Single-
Ended SFDR vs. f

OUT

@ 100 MSPS

TEMPERATURE C

SFDR

dBc

40

20

2.5MHz

10MHz

40MHz

Figure 17. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS

10dB

Div

10

110

START: 0.3 MHz

STOP: 25.0 MHz

CLOCK

= 50 MSPS

OUT1

= 6.25MHz

OUT2

= 6.75MHz

OUT3

= 7.25MHz

OUT4

= 7.75MHz

SFDR = 71dBc
AMPLITUDE = 0dBFS

Figure 20. Four-Tone SFDR

AD9762

REV. B

FREQUENCY MHz

SFDR

dBc

0.1

100

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 21. SFDR vs. f

OUT

@ 0 dBFS

FREQUENCY MHz

SFDR

dBc

0dBFS

6dBFS

12dBFS

Figure 24. SFDR vs. f

OUT

@ 50 MSPS

OUT

 dBFS

SFDR

dBc

30

25

20

15

10

455kHz

@ 5MSPS

2.27MHz

@ 25MSPS

4.55MHz

@ 50MSPS

9.1MHz

@ 100MSPS

11.37MHz

@ 125MSPS

Figure 27. Single-Tone SFDR vs. A

OUT

@ f

OUT

= f

CLOCK

/11

Typical AC Characterization Curves @ +3 V Supplies

(AVDD = +3 V, DVDD = +3 V, I

OUTFS

= 20 mA, 50

Doubly Terminated Load, Differential Output, T

= +25 C, SFDR up to Nyquist, unless otherwise noted)

FREQUENCY MHz

SFDR

dBc

0.00

2.50

0.50

1.00

1.50

2.00

0dBFS

6dBFS

12dBFS

Figure 22. SFDR vs. f

OUT

@ 5 MSPS

FREQUENCY MHz

SFDR

dBc

0dBFS

6dBFS

12dBFS

Figure 25. SFDR vs. f

OUT

@ 100 MSPS

OUT

 dBFS

SFDR

dBc

30

25

20

15

10

1MHz

@ 5MSPS

5.0MHz

@ 25MSPS

10MHz

@ 50MSPS

20MHz
@ 100MSPS

25MHz
@ 125MSPS

Figure 28. Single-Tone SFDR vs.
A

OUT

@ f

OUT

= f

CLOCK

FREQUENCY MHz

SFDR

dBc

0dBFS

6dBFS

12dBFS

Figure 23. SFDR vs. f

OUT

@ 25 MSPS

FREQUENCY MHz

SFDR

dBc

0dBFS

6dBFS

12dBFS

Figure 26. SFDR vs. f

OUT

@ 125 MSPS

OUT

 dBFS

SFDR

dBc

30

25

20

15

10

0.675/0.725MHz

@ 5MSPS

3.38/3.63MHz

@ 25MSPS

6.75/7.25MHz
@ 50MSPS

13.5/14.5MHz
@ 100MSPS

16.9/18.1MHz
@ 125MSPS

Figure 29. Dual-Tone SFDR vs. A

OUT

@ f

OUT

= f

CLOCK

AD9762

REV. B

FREQUENCY MSPS

dBc

70

75

95

140

100

120

80

85

90

2ND

HARMONIC

3RD
HARMONIC

4TH
HARMONIC

Figure 30. THD vs. f

CLOCK

@ f

OUT

2 MHz

1.25

0.50

1.25

4000

ERROR

LSB

1000

2000

3000

1.00

0.25

0.75

0.50

1.00

0.75

CODE

Figure 33. Typical INL

10dB

Div

100

START: 0.3 MHz

STOP: 50.0 MHz

CLOCK

= 100 MSPS

OUT

= 2.41MHz

SFDR = 72dBc
AMPLITUDE = 0dBFS

Figure 36. Single-Tone SFDR

OUTFS

 mA

SFDR

dBc

2.5MHz

10MHz

22.2MHz

40MHz

Figure 31. SFDR vs. f

OUT

and I

OUTFS

@ 100 MSPS, 0 dBFS

0.4

4000

ERROR

LSB

1000

2000

3000

0.8

0.2

0.4

0.6

CODE

Figure 34. Typical DNL

10dB

Div

100

START: 0.3 MHz

STOP: 50.0 MHz

CLOCK

= 100 MSPS

OUT1

= 13.5MHz

OUT2

= 14.5MHz

SFDR = 59.0dBc
AMPLITUDE = 0dBFS

Figure 37. Dual-Tone SFDR

OUTPUT FREQUENCY MHz

SFDR

dBc

100

IDIFF @
6dBFS

IDIFF @

0dBFS

IOUTA @

6dBFS

IOUTA @

0dBFS

Figure 32. Differential vs. Single
Ended SFDR vs. f

OUT

@ 100 MSPS

TEMPERATURE C

SFDR

dBc

40

20

2.5MHz

10MHz

28.6MHz

Figure 35. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS

10dB

Div

10

110

START: 0.3 MHz

STOP: 25.0 MHz

CLOCK

= 50 MSPS

OUT1

= 6.25MHz

OUT2

= 6.75MHz

OUT3

= 7.25MHz

OUT4

= 7.75MHz

SFDR = 71dBc
AMPLITUDE = 0dBFS

Figure 38. Four-Tone SFDR

AD9762

REV. B

FUNCTIONAL DESCRIPTION

Figure 39 shows a simplified block diagram of the AD9762.
The AD9762 consists of a large PMOS current source array
that is capable of providing up to 20 mA of total current. The
array is divided into 31 equal currents that make up the 5
most significant bits (MSBs). The next 4 bits or middle bits
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSBs are binary weighted
fractions of the middle-bits current sources. Implementing
the middle and lower bits with current sources, instead of an
R-2R ladder, enhances its dynamic performance for multitone
or low amplitude signals and helps maintain the DAC's high
output impedance (i.e., >100 k

All of these current sources are switched to one or the other
of the two output nodes (i.e., I

OUTA

or I

OUTB

) via PMOS differen-

tial current switches. The switches are based on a new archi-
tecture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.

The analog and digital sections of the AD9762 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.

The full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R

SET

. The external resistor, in combination

with both the reference control amplifier and voltage refer-
ence V

REFIO

, sets the reference current I

REF

, which is mirrored

over to the segmented current sources with the proper scaling
factor. The full-scale current, I

OUTFS

, is thirty-two times the value

of I

REF

DAC TRANSFER FUNCTION

The AD9762 provides complementary current outputs, I

OUTA

and I

OUTB

. I

OUTA

will provide a near full-scale current output,

OUTFS

, when all bits are high (i.e., DAC CODE = 4095) while

OUTB

, the complementary output, provides no current. The

current output appearing at I

OUTA

and I

OUTB

is a function of

both the input code and I

OUTFS

and can be expressed as:

OUTA

= (DAC CODE/4096)

× I

OUTFS

(1)

OUTB

= (4095 DAC CODE)/4096

× I

OUTFS

(2)

where DAC CODE = 0 to 4095 (i.e., Decimal Representation).

As mentioned previously, I

OUTFS

is a function of the reference

current I

REF

, which is nominally set by a reference voltage

REFIO

and external resistor R

SET

. It can be expressed as:

OUTFS

= 32

× I

REF

(3)

where I

REF

= V

REFIO

SET

(4)

The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, I

OUTA

and I

OUTB

should be directly connected to matching resistive

loads, R

LOAD

, which are tied to analog common, ACOM. Note,

LOAD

may represent the equivalent load resistance seen by

OUTA

or I

OUTB

as would be the case in a doubly terminated

or 75 cable. The single-ended voltage output appearing

at the I

OUTA

and I

OUTB

nodes is simply :

OUTA

= I

OUTA

× R

LOAD

(5)

OUTB

= I

OUTB

× R

LOAD

(6)

Note the full-scale value of V

OUTA

and V

OUTB

should not exceed

the specified output compliance range to maintain specified
distortion and linearity performance.

The differential voltage, V

DIFF

, appearing across I

OUTA

and

OUTB

is:

DIFF

= (I

OUTA

 I

OUTB

)

× R

LOAD

(7)

Substituting the values of I

OUTA

, I

OUTB

, and I

REF

; V

DIFF

can be

expressed as:

DIFF

= {(2 DAC CODE 4095)/4096}

(32 R

LOAD

SET

)

× V

REFIO

(8)

These last two equations highlight some of the advantages of
operating the AD9762 differentially. First, the differential
operation will help cancel common-mode error sources associated
with I

OUTA

and I

OUTB

such as noise, distortion and dc offsets.

Second, the differential code dependent current and subsequent
voltage, V

DIFF

, is twice the value of the single-ended voltage

output (i.e., V

OUTA

or V

OUTB

), thus providing twice the signal

power to the load.

Note, the gain drift temperature performance for a single-ended
(V

OUTA

and V

OUTB

) or differential output (V

DIFF

) of the AD9762

can be enhanced by selecting temperature tracking resistors for
R

LOAD

and R

SET

due to their ratiometric relationship as shown

in Equation 8.

DIGITAL DATA INPUTS (DB11DB0)

50pF

COMP1

+1.20V REF

AVDD

ACOM

REFLO

COMP2

PMOS

CURRENT SOURCE

ARRAY

0.1 F

+5V

SEGMENTED SWITCHES

FOR DB11DB3

LSB

SWITCHES

REFIO

FS ADJ

DVDD

DCOM

CLOCK

+5V

SET

0.1 F

IOUTA

IOUTB

0.1 F

AD9762

SLEEP

LATCHES

REF

REFIO

CLOCK

OUTB

OUTA

LOAD

OUTB

OUTA

LOAD

DIFF

= V

OUTA

 V

OUTB

Figure 39. Functional Block Diagram

AD9762

REV. B

REFERENCE OPERATION

The AD9762 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external refer-
ence. REFIO serves as either an input or output depending on
whether the internal or an external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 40, the internal
reference is activated and REFIO provides a 1.20 V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1

µF or greater from REFIO

to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100 nA if any
additional loading is required.

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

0.1 F

+5V

REFIO

FS ADJ

0.1 F

AD9762

ADDITIONAL

LOAD

OPTIONAL

EXTERNAL

REF BUFFER

Figure 40. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 41. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1

µF compensation capacitor is not required

since the internal reference is disabled, and the high input
impedance (i.e., 1 M

) of REFIO minimizes any loading of the

external reference.

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

0.1 F

AVDD

REFIO

FS ADJ

SET

AD9762

EXTERNAL

REF

REFIO

SET

AVDD

REFERENCE
CONTROL
AMPLIFIER

REFIO

Figure 41. External Reference Configuration

REFERENCE CONTROL AMPLIFIER

The AD9762 also contains an internal control amplifier that is
used to regulate the DAC's full-scale output current, I

OUTFS

The control amplifier is configured as a V-I converter as shown
in Figure 41, such that its current output, I

REF

, is determined by

the ratio of the V

REFIO

and an external resistor, R

SET

, as stated

in Equation 4. I

REF

is copied over to the segmented current

sources with the proper scaling factor to set I

OUTFS

as stated in

Equation 3.

The control amplifier allows a wide (10:1) adjustment span of
I

OUTFS

over a 2 mA to 20 mA range by setting IREF between

62.5

µA and 625 µA. The wide adjustment span of I

OUTFS

provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9762, which is
proportional to I

OUTFS

(refer to the Power Dissipation section).

The second benefit relates to the 20 dB adjustment, which is
useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is
approximately 1.4 MHz and can be reduced by connecting an
external capacitor between COMP1 and AVDD. The output of
the control amplifier, COMP1, is internally compensated via a
50 pF capacitor that limits the control amplifier small-signal
bandwidth and reduces its output impedance. Any additional
external capacitance further limits the bandwidth and acts as a
filter to reduce the noise contribution from the reference ampli-
fier. Figure 42 shows the relationship between the external
capacitor and the small signal 3 dB bandwidth of the

COMP1 CAPACITOR nF

1000

0.1

1000

BANDWIDTH

kHz

100

Figure 42. External COMP1 Capacitor vs. 3 dB Bandwidth

reference amplifier. Since the 3 dB bandwidth corresponds
to the dominant pole, and hence the time constant, the settling
time of the control amplifier to a stepped reference input
response can be approximated.

The optimum distortion performance for any reconstructed
waveform is obtained with a 0.1

µF external capacitor installed.

Thus, if I

REF

is fixed for an application, a 0.1

µF ceramic chip

capacitor is recommended. Also, since the control amplifier is
optimized for low power operation, multiplying applications
requiring large signal swings should consider using an external
control amplifier to enhance the application's overall large signal
multiplying bandwidth and/or distortion performance.

There are two methods in which I

REF

can be varied for a fixed

SET

. The first method is suitable for a single-supply system in

which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, thus allowing I

REF

to be varied for a fixed R

SET

. Since the

input impedance of REFIO is approximately 1 M

, a simple,

low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 43 using the AD7524 and an external 1.2 V reference,
the AD1580.

AD9762

REV. B

The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed and I

REF

varied by an external voltage, V

, applied to R

SET

via an ampli-

fier. An example of this method is shown in Figure 44 in which
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, V

, is

referenced to ACOM and should not exceed 1.2 V. The value
of R

SET

is such that I

REFMAX

and I

REFMIN

do not exceed 62.5

µA

and 625

µA, respectively. The associated equations in Figure 44

can be used to determine the value of R

SET

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9762

REF

OPTIONAL

BANDLIMITING

CAPACITOR

1 F

REF

= (1.2V

)/R

SET

WITH V

< V

REFIO

AND 62.5 A I

REF

625A

Figure 44. Dual-Supply Gain Control Circuit

In some applications, the user may elect to use an external con-
trol amplifier to enhance the multiplying bandwidth, distortion
performance, and/or settling time. External amplifiers capable
of driving a 50 pF load such as the AD817 are suitable for this
purpose. It is configured in such a way that it is in parallel with
the weaker internal reference amplifier as shown in Figure 45.
In this case, the external amplifier simply overdrives the weaker
reference control amplifier. Also, since the internal control
amplifier has a limited current output, it will sustain no damage
if overdriven.

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9762

REF

INPUT

EXTERNAL

CONTROL AMPLIFIER

Figure 45. Configuring an External Reference Control
Amplifier

ANALOG OUTPUTS

The AD9762 produces two complementary current outputs,
I

OUTA

and I

OUTB

, which may be configured for single-ended or

differential operation. I

OUTA

and I

OUTB

can be converted into

complementary single-ended voltage outputs, V

OUTA

and V

OUTB

via a load resistor, R

LOAD

, as described in the DAC Transfer

Function section by Equations 5 through 8. The differential
voltage, V

DIFF

, existing between V

OUTA

and V

OUTB

can also be

converted to a single-ended voltage via a transformer or differ-
ential amplifier configuration. The ac performance of the
AD9762 is optimum and specified using a differential trans-
former coupled output in which the voltage swing at I

OUTA

and

OUTB

is limited to

±0.5 V. If a single-ended unipolar output is

desirable, I

OUTA

should be selected.

The distortion and noise performance of the AD9762 can be
enhanced when the AD9762 is configured for differential opera-
tion. The common-mode error sources of both I

OUTA

and I

OUTB

can be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed wave-
form increases. This is due to the first order cancellation of
various dynamic common-mode distortion mechanisms, digital
feedthrough and noise.

Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the recon-
structed signal power to the load (i.e., assuming no source
termination). Since the output currents of I

OUTA

and I

OUTB

are

complementary, they become additive when processed differen-
tially. A properly selected transformer will allow the AD9762 to
provide the required power and voltage levels to different loads.
Refer to Applying the AD9762 section for examples of various
output configurations.

The output impedance of I

OUTA

and I

OUTB

is determined by the

equivalent parallel combination of the PMOS switches associ-
ated with the current sources and is typically 100 k

in parallel

with 5 pF. It is also slightly dependent on the output voltage
(i.e., V

OUTA

and V

OUTB

) due to the nature of a PMOS device.

As a result, maintaining I

OUTA

and/or I

OUTB

at a virtual ground

via an I-V op amp configuration will result in the optimum dc
linearity. Note, the INL/DNL specifications for the AD9762
are measured with I

OUTA

maintained at a virtual ground via an

op amp.

1.2V

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9762

REF

SET

AVDD

OPTIONAL

BANDLIMITING

CAPACITOR

REF

OUT1

OUT2

AGND

DB7DB0

AD7524

AD1580

0.1V TO 1.2V

Figure 43. Single-Supply Gain Control Circuit

AD9762

REV. B

OUTA

and I

OUTB

also have a negative and positive voltage

compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of 1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9762.

The positive output compliance range is slightly dependent
on the full-scale output current, I

OUTFS

. It degrades slightly

from its nominal 1.25 V for an I

OUTFS

= 20 mA to 1.00 V for an

OUTFS

= 2 mA. The optimum distortion performance for a

single-ended or differential output is achieved when the maximum
full-scale signal at I

OUTA

and I

OUTB

does not exceed 0.5 V.

Applications requiring the AD9762's output (i.e., V

OUTA

and/

or V

OUTB

) to extend its output compliance range should size

LOAD

accordingly. Operation beyond this compliance range

will adversely affect the AD9762's linearity performance and
subsequently degrade its distortion performance.

DIGITAL INPUTS

The AD9762's digital input consists of 12 data input pins and a
clock input pin. The 12-bit parallel data inputs follow standard
positive binary coding where DB11 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). I

OUTA

produces

a full-scale output current when all data bits are at Logic 1.
I

OUTB

produces a complementary output with the full-scale current

split between the two outputs as a function of the input code.

The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed
to support a clock rate as high as 125 MSPS. The clock can
be operated at any duty cycle that meets the specified latch
pulsewidth. The set-up and hold times can also be varied within
the clock cycle as long as the specified minimum times are met;
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is
typically achieved when the input data transitions on the falling edge
of a 50% duty cycle clock.

The digital inputs are CMOS compatible with logic thresholds,
V

THRESHOLD

set to approximately half the digital positive supply

(DVDD) or

THRESHOLD

= DVDD/2 (

±20%)

The internal digital circuitry of the AD9762 is capable of operating
over a digital supply range of 2.7 V to 5.5 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V

OH(MAX)

. A DVDD of 3 V to 3.3 V will typically ensure

proper compatibility with most TTL logic families. Figure 46
shows the equivalent digital input circuit for the data and clock
inputs. The sleep mode input is similar with the exception that
it contains an active pull-down circuit, thus ensuring that the
AD9762 remains enabled if this input is left disconnected.

DVDD

DIGITAL

INPUT

Figure 46. Equivalent Digital Input

Since the AD9762 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important
in achieving the optimum performance. The drivers of the
digital data interface circuitry should be specified to meet the
minimum set-up and hold times of the AD9762 as well as its
required min/max input logic level thresholds. Typically, the
selection of the slowest logic family that satisfies the above
conditions will result in the lowest data feedthrough and noise.

Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20

to 100 ) between the

AD9762 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to data feedthrough. For longer run lengths and high
data update rates, strip line techniques with proper termination
resistors should be considered to maintain "clean" digital
inputs. Also, operating the AD9762 with reduced logic swings
and a corresponding digital supply (DVDD) will also reduce
data feedthrough.

The external clock driver circuitry should provide the AD9762
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a recon-
structed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.

Note, the clock input could also be driven via a sine wave,
which is centered around the digital threshold (i.e., DVDD/2),
and meets the min/max logic threshold. This will typically result
in a slight degradation in the phase noise, which becomes more
noticeable at higher sampling rates and output frequencies.
Also, at higher sampling rates, the 20% tolerance of the digital
logic threshold should be considered since it will affect the
effective clock duty cycle and subsequently cut into the required
data set-up and hold times.

SLEEP MODE OPERATION

The AD9762 has a power-down function which turns off the
output current and reduces the supply current to less than
8.5 mA over the specified supply range of 2.7 V to 5.5 V and
temperature range. This mode can be activated by applying
a logic level "1" to the SLEEP pin. This digital input also
contains an active pull-down circuit that ensures the AD9762
remains enabled if this input is left disconnected. The SLEEP
input with active pull-down requires <40

µA of drive current.

The power-up and power-down characteristics of the AD9762
are dependent upon the value of the compensation capacitor
connected to COMP1. With a nominal value of 0.1

µF, the

AD9762 takes less than 5

µs to power down and approximately

3.25 ms to power back up. Note, the SLEEP MODE should not
be used when the external control amplifier is used as shown in
Figure 45.

POWER DISSIPATION

The power dissipation, P

, of the AD9762 is dependent on

several factors which include: (1) AVDD and DVDD, the power
supply voltages; (2) I

OUTFS

, the full-scale current output; (3)

CLOCK

, the update rate; (4) and the reconstructed digital input

waveform. The power dissipation is directly proportional to the
analog supply current, I

AVDD

, and the digital supply current, I

DVDD

AVDD

is directly proportional to I

OUTFS

as shown in Figure 47

and is insensitive to f

CLOCK

AD9762

REV. B

OUTFS

 mA

AVDD

Figure 47. I

AVDD

vs. I

OUTFS

Conversely, I

DVDD

is dependent on both the digital input wave-

form, f

CLOCK

, and digital supply DVDD. Figures 48 and 49

show I

DVDD

as a function of full-scale sine wave output ratios

OUT

CLOCK

) for various update rates with DVDD = 5 V and

DVDD = 3 V, respectively. Note, how I

DVDD

is reduced by more

than a factor of 2 when DVDD is reduced from 5 V to 3 V.

RATIO (f

OUT

CLK

)

0.01

0.1

DVDD

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 48. I

DVDD

vs. Ratio @ DVDD = 5 V

RATIO (f

OUT

CLK

)

0
0.01

0.1

DVDD

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 49. I

DVDD

vs. Ratio @ DVDD = 3 V

APPLYING THE AD9762

OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configura-
tions for the AD9762. Unless otherwise noted, it is assumed
that I

OUTFS

is set to a nominal 20 mA. For applications requir-

ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the
optimum high frequency performance and is recommended for
any application allowing for ac coupling. The differential op
amp configuration is suitable for applications requiring dc
coupling, a bipolar output, signal gain and/or level shifting.

A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if I

OUTA

and/or I

OUTB

is connected to an appropriately

sized load resistor, R

LOAD

, referred to ACOM. This configura-

tion may be more suitable for a single-supply system requiring
a dc coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter thus converting
I

OUTA

or I

OUTB

into a negative unipolar voltage. This configura-

tion provides the best dc linearity since I

OUTA

or I

OUTB

maintained at a virtual ground. Note, I

OUTA

provides slightly

better performance than I

OUTB

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to-
single-ended signal conversion as shown in Figure 50. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer's passband. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and noise
over a wide frequency range. It also provides electrical isolation
and the ability to deliver twice the power to the load. Trans-
formers with different impedance ratios may also be used for
impedance matching purposes. Note that the transformer
provides ac coupling only.

LOAD

AD9762

MINI-CIRCUITS

T1-1T

OPTIONAL R

DIFF

IOUTA

IOUTB

Figure 50. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both I

OUTA

and I

OUTB

. The complementary voltages appear-

ing at I

OUTA

and I

OUTB

(i.e., V

OUTA

and V

OUTB

) swing symmetri-

cally around ACOM and should be maintained with the specified
output compliance range of the AD9762. A differential resistor,
R

DIFF

, may be inserted in applications in which the output of

the transformer is connected to the load, R

LOAD

, via a passive

reconstruction filter or cable. R

DIFF

is determined by the

transformer's impedance ratio and provides the proper source
termination which results in a low VSWR. Note that approxi-
mately half the signal power will be dissipated across R

DIFF

AD9762

REV. B

DIFFERENTIAL USING AN OP AMP

An op amp can also be used to perform a differential to single-
ended conversion as shown in Figure 51. The AD9762 is
configured with two equal load resistors, R

LOAD

, of 25

The differential voltage developed across I

OUTA

and I

OUTB

converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
I

OUTA

and I

OUTB

forming a real pole in a low-pass filter. The

addition of this capacitor also enhances the op amps distortion
performance by preventing the DACs high slewing output from
overloading the op amp's input.

AD9762

IOUTA

IOUTB

OPT

500

225

500

AD8047

Figure 51. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ-
ential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate off of a
dual supply since its output is approximately

±1.0 V. A high

speed amplifier capable of preserving the differential perfor-
mance of the AD9762 while meeting other system level objec-
tives (i.e., cost, power) should be selected. The op amps
differential gain, its gain setting resistor values, and full-scale
output swing capabilities should all be considered when opti-
mizing this circuit.

The differential circuit shown in Figure 52 provides the neces-
sary level-shifting required in a single supply system. In this
case, AVDD which is the positive analog supply for both the
AD9762 and the op amp is also used to level-shift the differ-
ential output of the AD9762 to midsupply (i.e., AVDD/2). The
AD8041 is a suitable op amp for this application.

AD9762

IOUTA

IOUTB

OPT

500

225

AD8041

AVDD

Figure 52. Single-Supply DC Differential Coupled Circuit

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 53 shows the AD9762 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50

cable since the nominal full-scale current, I

OUTFS

, of

20 mA flows through the equivalent R

LOAD

of 25

. In this

case, R

LOAD

represents the equivalent load resistance seen by

OUTA

or I

OUTB

. The unused output (I

OUTA

or I

OUTB

) can be

connected to ACOM directly or via a matching R

LOAD

. Different

values of I

OUTFS

and R

LOAD

can be selected as long as the positive

compliance range is adhered to. One additional consideration in

this mode is the integral nonlinearity (INL) as discussed in the
Analog Output section of this data sheet. For optimum INL
performance, the single-ended, buffered voltage output configu-
ration is suggested.

AD9762

IOUTA

IOUTB

OUTA

= 0 TO +0.5V

OUTFS

= 20mA

Figure 53. 0 V to +0.5 V Unbuffered Voltage Output

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION

Figure 54 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9762 output current. U1 maintains I

OUTA

(or I

OUTB

) at a

virtual ground, thus minimizing the nonlinear output imped-
ance effect on the DAC's INL performance as discussed in
the Analog Output section. Although this single-ended configu-
ration typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by U1's slewing capabilities. U1 provides a negative
unipolar output voltage and its full-scale output voltage is sim-
ply the product of R

and I

OUTFS

. The full-scale output should

be set within U1's voltage output swing capabilities by scaling
I

OUTFS

and/or R

. An improvement in ac distortion perfor-

mance may result with a reduced I

OUTFS

since the signal current

U1 will be required to sink will be subsequently reduced.

IOUTA

IOUTB

OPT

200

OUT

= I

OUTFS

= 10mA

200

AD9762

Figure 54. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS

In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection;
placement and routing; and supply bypassing and grounding.
Figures 6065 illustrate the recommended printed circuit board
ground, power and signal plane layouts which are implemented
on the AD9762 evaluation board.

Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9762 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. In general, AVDD, the analog supply, should be decoupled
to ACOM, the analog common, as close to the chip as physi-
cally possible. Similarly, DVDD, the digital supply, should be
decoupled to DCOM as close as physically as possible.

AD9762

REV. B

For those applications that require a single +5 V or +3 V supply
for both the analog and digital supply, a clean analog supply
may be generated using the circuit shown in Figure 55. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained using low
ESR type electrolytic and tantalum capacitors.

100 F
ELECT.

10-22 F
TANT.

0.1 F
CER.

TTL/CMOS

LOGIC

CIRCUITS

+5V OR +3V

POWER SUPPLY

FERRITE

BEADS

AVDD

ACOM

Figure 55. Differential LC Filter for Single +5 V or +3 V
Applications

Maintaining low noise on power supplies and ground is critical
to obtaining optimum results from the AD9762. If properly
implemented, ground planes can perform a host of functions on
high speed circuit boards: bypassing, shielding, current trans-
port, etc. In mixed signal design, the analog and digital portions
of the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined to areas covering
the digital interconnects.

All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8 to
1/4 inch wide underneath or within 1/2 inch of the DAC to
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC as well as any clock signals. On the analog side, this
includes the DAC output signal, reference signal and the supply
feeders.

The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part, as well as providing
some "free" capacitive decoupling to the appropriate ground
plane. It is essential that care be taken in the layout of signal
and power ground interconnects to avoid inducing extraneous
voltage drops in the signal ground paths. It is recommended that
all connections be short, direct and as physically close to the
package as possible in order to minimize the sharing of conduc-
tion paths between different currents. When runs exceed an inch
in length, strip line techniques with proper termination resistor
should be considered. The necessity and value of this resistor
will be dependent upon the logic family used.

For a more detailed discussion of the implementation and
construction of high speed, mixed signal printed circuit boards,
refer to Analog Devices' application notes AN-280 and AN-333.

APPLICATIONS
Using the AD9762 for QAM Modulation

QAM is one of the most widely used digital modulation schemes
in digital communication systems. This modulation technique
can be found in both FDM as well as spreadspectrum (i.e.,
CDMA) based systems. A QAM signal is a carrier frequency
which is both modulated in amplitude (i.e., AM modulation)
and in phase (i.e., PM modulation). It can be generated by
independently modulating two carriers of identical frequency
but with a 90

° phase difference. This results in an in-phase (I)

carrier component and a quadrature (Q) carrier component at a
90

° phase shift with respect to the I component. The I and Q

components are then summed to provide a QAM signal at the
specified carrier frequency.

A common and traditional implementation of a QAM modu-
lator is shown in Figure 56. The modulation is performed in the
analog domain in which two DACs are used to generate the
baseband I and Q components, respectively. Each component is
then typically applied to a Nyquist filter before being applied to
a quadrature mixer. The matching Nyquist filters shape and
limit each component's spectral envelope while minimizing
intersymbol interference. The DAC is typically updated at the
QAM symbol rate or possibly a multiple of it if an interpolating
filter precedes the DAC. The use of an interpolating filter typi-
cally eases the implementation and complexity of the analog
filter, which can be a significant contributor to mismatches in
gain and phase between the two baseband channels. A quadra-
ture mixer modulates the I and Q components with in-phase
and quadrature phase carrier frequency and then sums the two
outputs to provide the QAM signal.

AD9762

CARRIER

FREQUENCY

TO
MIXER

DSP

ASIC

NYQUIST

FILTERS

QUADRATURE

MODULATOR

Figure 56. Typical Analog QAM Architecture

In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 57 helps improve
upon the matching and temperature stability characteristics
between the I and Q channels. Using a single voltage reference
derived from U1 to set the gain for both the I and Q channels
will improve the gain matching and stability. Further enhance-
ments in gain matching and stability are achieved by using
separate matching resistor networks for both R

SET

and R

LOAD

Additional trim capability via R

CAL1

and R

CAL2

can be added to

compensate for any initial mismatch in gain between the two
channels. This may be attributed to any mismatch between U1
and U2's gain setting resistor, (R

SET

); effective load resistance,

LOAD

); and/or voltage offset of each DAC's control amplifier.

The differential voltage outputs of U1 and U2 are fed into their
respective differential inputs of a quadrature mixer via matching
50

filter networks.

AD9762

REV. B

REFIO

FS ADJ

IOUTA

IOUTB

CLOCK

SET

2k *

CAL1

CLOCK

I-CHANNEL

50 **
R

LOAD

50 **
R

LOAD

TO
NYQUIST
FILTER
AND MIXER

REFIO

FS ADJ

IOUTA

IOUTB

CLOCK

SET

2k *

CAL2

100

Q-CHANNEL

50 **
R

LOAD

50 **
R

LOAD

TO
NYQUIST
FILTER
AND MIXER

0.1 F

REFLO

AVDD

* OHMTEK ORNA1001F
** OHMTEK TOMC1603-50F

Figure 57. Baseband QAM Implementation Using Two
AD9762s

It is also possible to generate a QAM signal completely in the
digital domain via a DSP or ASIC, in which case only a single
DAC of sufficient resolution and performance is required to
reconstruct the QAM signal. Also available from several vendors
are Digital ASICs which implement other digital modulation
schemes such as PSK and FSK. This digital implementation has
the benefit of generating perfectly matched I and Q components
in terms of gain and phase, which is essential in maintaining
optimum performance in a communication system. In this
implementation, the reconstruction DAC must be operating at a
sufficiently high clock rate to accommodate the highest specified
QAM carrier frequency. Figure 58 shows a block diagram of
such an implementation using the AD9762.

AD9762

LPF

TO
MIXER

STEL-1130

QAM

COS

SIN

I DATA

Q DATA

CARRIER

FREQUENCY

STEL-1177

NCO

CLOCK

Figure 58. Digital QAM Architecture

AD9762 EVALUATION BOARD
General Description

The AD9762-EB is an evaluation board for the AD9762 12-bit
D/A converter. Careful attention to layout and circuit design
combined with a prototyping area allow the user to easily and
effectively evaluate the AD9762 in any application where high
resolution, high speed conversion is required.

This board allows the user the flexibility to operate the AD9762
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting
and differential amplifier outputs. The digital inputs are designed
to be driven directly from various word generators, with the
on-board option to add a resistor network for proper load
termination. Provisions are also made to operate the AD9762
with either the internal or external reference, or to exercise
the power-down feature.

Refer to the application note AN-420 "Using the AD9760/
AD9762/AD9764-EB Evaluation Board" for a thorough
description and operating instructions for the AD9762
evaluation board.

AD9762

REV. B

10
9
8
7
6
5
4
3
2

DVDD

10
9
8
7
6
5
4
3
2

DVDD

10
9
8
7
6
5
4
3
2

DVDD

10
9
8
7
6
5
4
3
2

C19

C25

C26

C27

C28

C29

16 PINDIP

RES PK

C30

C31

C32

C33

C34

C35

C36

16 PINDIP

RES PK

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

CLOCK

DVDD

DCOM

AVDD

COMP2

IOUTA

IOUTB

ACOM

COMP1

FS ADJ

REFIO

REFLO

SLEEP

AD976x

AVDD

CT1

R15

49.9

CLK

JP1

TP1

EXTCLK

0.1

AVDD

0.1

TP8

AVDD

TP11

C11

0.1

TP10

TP9

R16

TP14

JP4

C10

0.1

OUT 1

OUT 2

TP13

R17

49.9

PDIN

AVDD

JP2

TP12

TP7

AVCC

TP6

AVEE

TP19

AGND

TP18

TP5

TP4

AVDD

TP2

DGND

TP3

DVDD

R20

49.9

C12

22pF

R14

R38

49.9

JP6A

JP6B

R13

OPEN

C13

22pF

C20

R12

OPEN

JP7B

JP7A

R10

JP8

R35

JP9

R18

AD8047

C21

0.1

C22

R36

C23

0.1

C24

AVEE

AVCC

R37

49.9

JP5

C15

0.1

AVEE

R46

C17

0.1

JP3

AVCC

R43

R45

C14

R44

EXTREFIN

R42

C16

AVCC

C18

0.1

VIN

VOUT

GND

REF43

DVDD

AD8047

OUT2

OUT1

Figure 59. AD9762 Evaluation Board Schematic

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