REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD9772

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

14-Bit, 150 MSPS TxDAC+

with 2 Interpolation Filter

FEATURES
Single 2.7 V to 3.6 V Supply
14-Bit DAC Resolution and Input Data Width
150 MSPS Input Data Rate
63.3 MHz Reconstruction Passband @ 150 MSPS
75 dBc SFDR @ 25 MHz
2 Interpolation Filter with High or Low Pass Response

73 dB Image Rejection with 0.005 dB Passband Ripple

"Zero-Stuffing" Option for Enhanced Direct IF

Performance

Internal 2 /4 Clock Multiplier
205 mW Power Dissipation; 13 mW with Power-Down

Mode

48-Lead LQFP Package

APPLICATIONS
Communication Transmit Channel

WCDMA Base Stations, Multicarrier Base Stations,

Direct IF Synthesis

Instrumentation

PRODUCT DESCRIPTION

The AD9772 is a single supply, oversampling, 14-bit digital-to-
analog converter (DAC) optimized for baseband or IF waveform
reconstruction applications requiring exceptional dynamic range.
Manufactured on an advanced CMOS process, it integrates a
complete, low distortion 14-bit DAC with a 2

digital interpola-

tion filter and clock multiplier. The on-chip PLL clock multi-
plier provides all the necessary clocks for the digital filter and the
14-bit DAC. A flexible differential clock input allows for a single-
ended or differential clock driver for optimum jitter performance.

For baseband applications, the 2

digital interpolation filter

provides a low pass response, hence providing up to a three-fold
reduction in the complexity of the analog reconstruction filter. It
does so by multiplying the input data rate by a factor of two
while simultaneously suppressing the original upper inband
image by more than 73 dB. For direct IF applications, the 2

digital interpolation filter response can be reconfigured to select
the upper inband image (i.e., high pass response) while sup-
pressing the original baseband image. To increase the signal
level of the higher IF images and their passband flatness in di-
rect IF applications, the AD9772 also features a "zero stuffing"
option in which the data following the 2

interpolation filter is

upsampled by a factor of two by inserting midscale data samples.

The AD9772 can reconstruct full-scale waveforms with band-
widths as high as 63.3 MHz while operating at an input data rate of
150 MSPS. The 14-bit DAC provides differential current out-
puts to support differential or single-ended applications. A

segmented current source architecture is combined with a propri-
etary switching technique to reduce spurious components and
enhance dynamic performance. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The differential current out-
puts may be fed into a transformer or a differential op amp
topology to obtain a single-ended output voltage using an ap-
propriate resistive load.

The on-chip bandgap reference and control amplifier are config-
ured for maximum accuracy and flexibility. The AD9772 can be
driven by the on-chip reference or by a variety of external refer-
ence voltages. The full-scale current of the AD9772 can be
adjusted over a 2 mA to 20 mA range, thus providing additional
gain ranging capabilities.

The AD9772 is available in a 48-lead LQFP package and speci-
fied for operation over the industrial temperature range of 40

to +85

PRODUCT HIGHLIGHTS

1. A flexible, low power 2

interpolation filter supporting re-

construction bandwidths of up to 63.3 MHz can be config-
ured for a low or high pass response with 73 dB of image
rejection for traditional baseband or direct IF applications.

2. A "zero-stuffing" option enhances direct IF applications.

3. A low glitch, fast settling 14-bit DAC provides exceptional

dynamic range for both baseband and direct IF waveform
reconstruction applications.

4. The AD9772 digital interface, consisting of edge-triggered

latches and a flexible differential or single-ended clock input,
can support input data rates up to 150 MSPS.

5. On-chip PLL clock multiplier generates all of the internal high

speed clocks required by the interpolation filter and DAC.

6. The current output(s) of the AD9772 can easily be configured

for various single-ended or differential circuit topologies.

TxDAC+ is a trademark of Analog Devices, Inc.

FUNCTIONAL BLOCK DIAGRAM

14-BIT DAC

ZERO

STUFF

MUX

2 FIR

INTERPOLATION

FILTER

EDGE-

TRIGGERED

LATCHES

CLOCK DISTRIBUTION

AND MODE SELECT

2 /4

MUX

CONTROL

FILTER

CONTROL

1 /2

PLL CLOCK

MULTIPLIER

+1.2V REFERENCE

AND CONTROL AMP

AD9772

CLKCOM CLKVDD

MOD0 MOD1

RESET

PLLLOCK

DIV0 DIV1

CLK+

CLK

DATA

INPUTS

(DB13...DB0)

SLEEP

DCOM

DVDD

ACOM

AVDD

REFLO

PLLCOM

LPF

PLLVDD

IOUTA

IOUTB

REFIO

FSADJ

REV. 0

AD9772SPECIFICATIONS

MIN

to T

MAX

, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = 0 V, DVDD = +3 V, I

OUTFS

= 20 mA, unless otherwise

noted)

DC SPECIFICATIONS

Parameter

Min

Typ

Max

Units

RESOLUTION

Bits

DC ACCURACY

Integral Linearity Error (INL)

3.5

LSB

Differential Nonlinearity (DNL)

2.0

LSB

Monotonicity (12-Bit)

Guaranteed Over Specified Temperature Range

ANALOG OUTPUT

Offset Error

0.025

+0.025

% of FSR

Gain Error (Without Internal Reference)

0.5

% of FSR

Gain Error (With Internal Reference)

1.5

% of FSR

Full-Scale Output Current

Output Compliance Range

1.0

+1.25

Output Resistance

200

Output Capacitance

REFERENCE OUTPUT

Reference Voltage

1.14

1.20

1.26

Reference Output Current

REFERENCE INPUT

Input Compliance Range

0.1

1.25

Reference Input Resistance (REFLO = 3 V)

Small Signal Bandwidth

0.5

MHz

TEMPERATURE COEFFICIENTS

Unipolar Offset Drift

ppm of FSR/

Gain Drift (Without Internal Reference)

ppm of FSR/

Gain Drift (With Internal Reference)

100

ppm of FSR/

Reference Voltage Drift

ppm/

POWER SUPPLY

AVDD

Voltage Range

2.7

3.0

3.6

Analog Supply Current (I

AVDD

)

Analog Supply Current in SLEEP Mode (I

AVDD

)

4.3

PLLVDD

Voltage Range

2.7

3.0

3.6

PLL Clock Multiplier Supply Current (I

PLLVDD

)

4.5

CLKVDD

Voltage Range

2.7

3.0

3.6

Clock Supply Current (I

CLKVDD

)

5.5

DVDD

Voltage Range

2.7

3.0

3.6

Digital Supply Current (I

DVDD

)

Nominal Power Dissipation

205

231

Power Supply Rejection Ratio (PSRR)

AVDD

0.6

+0.6

% of FSR/V

Power Supply Rejection Ratio (PSRR)

DVDD

0.025

+0.025

% of FSR/V

OPERATING RANGE

+85

NOTES

Measured at IOUTA driving a virtual ground.

Nominal full-scale current, I

OUTFS

, is 32

the I

REF

current.

Use an external amplifier to drive any external load.

Measured at f

DATA

= 100 MSPS and f

OUT

= 1 MHz, PLLVDD = 3.0 V.

Measured at f

DATA

= 50 MSPS and f

OUT

= 1 MHz.

Measured over a 2.7 V to 3.6 V range.

Specifications subject to change without notice.

REV. 0

AD9772

MIN

to T

MAX

, AVDD = +3 V, CLKVDD = +3 V, DVDD = +3 V, PLLVDD = 0 V, I

OUTFS

= 20 mA,

Differential Transformer Coupled Output, 50

Doubly Terminated, unless otherwise noted)

DYNAMIC SPECIFICATIONS

Parameter

Min

Typ

Max

Units

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f

DAC

)

400

MSPS

Output Settling Time (t

) (to 0.025%)

Output Propagation Delay

)

Output Rise Time (10% to 90%)

0.8

Output Fall Time (10% to 90%)

0.8

Output Noise (I

OUTFS

= 20 mA)

pA/

AC LINEARITYBASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f

OUT

= 0 dBFS)

DATA

= 65 MSPS; f

OUT

= 1.01 MHz

dBc

DATA

= 65 MSPS; f

OUT

= 10.01 MHz

dBc

DATA

= 65 MSPS; f

OUT

= 26.01 MHz

dBc

DATA

= 150 MSPS; f

OUT

= 2.02 MHz

dBc

DATA

= 150 MSPS; f

OUT

= 20.02 MHz

dBc

DATA

= 150 MSPS; f

OUT

= 52.02 MHz

dBc

Two-Tone Intermodulation (IMD) to Nyquist (f

OUT1

= f

OUT2

= 6 dBFS)

DATA

= 65 MSPS; f

OUT1

= 5.01 MHz; f

OUT2

= 6.01 MHz

dBc

DATA

= 65 MSPS; f

OUT1

= 15.01 MHz; f

OUT2

= 17.51 MHz

dBc

DATA

= 65 MSPS; f

OUT1

= 24.1 MHz; f

OUT2

= 26.2 MHz

dBc

DATA

= 150 MSPS; f

OUT1

= 10.02 MHz; f

OUT2

= 12.02 MHz

dBc

DATA

= 150 MSPS; f

OUT1

= 30.02 MHz; f

OUT2

= 35.02 MHz

dBc

DATA

= 150 MSPS; f

OUT1

= 48.2 MHz; f

OUT2

= 52.4 MHz

dBc

Total Harmonic Distortion (THD)

DATA

= 50 MSPS; f

OUT

= 1.0 MHz; 0 dBFS

DATA

= 65 MSPS; f

OUT

= 10.01 MHz; 0 dBFS

Signal-to-Noise Ratio (SNR)

DATA

= 65 MSPS; f

OUT

= 16.26 MHz; 0 dBFS

DATA

= 100 MSPS; f

OUT

= 25.1 MHz; 0 dBFS

Adjacent Channel Power Ratio (ACPR)

WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing

IF = 16 MHz, f

DATA

= 65.536 MSPS

dBc

IF = 32 MHz, f

DATA

= 131.072 MSPS

dBc

Four-Tone Intermodulation

15.6 MHz, 15.8 MHz, 16.2 MHz and 16.4 MHz at 12 dBFS

dBFS

DATA

= 65 MSPS, Missing Center

AC LINEARITYIF MODE

Four-Tone Intermodulation at IF = 70 MHz

68.1 MHz, 69.3 MHz, 71.2 MHz and 72.0 MHz at 20 dBFS

dBFS

DATA

= 52 MSPS, f

DAC

= 208 MHz

NOTES

Propagation delay is delay from CLK input to DAC update.

Measured single-ended into 50

load.

Specifications subject to change without notice.

REV. 0

AD9772SPECIFICATIONS

DIGITAL SPECIFICATIONS

MIN

to T

MAX

, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = +0 V, DVDD = +3 V, I

OUTFS

= 20 mA, unless

otherwise noted)

Parameter

Min

Typ

Max

Units

DIGITAL INPUTS

Logic "1" Voltage

2.1

Logic "0" Voltage

0.9

Logic "1" Current

+10

Logic "0" Current

+10

Input Capacitance

CLOCK INPUTS

Input Voltage Range

Common-Mode Voltage

0.75

1.5

2.25

Differential Voltage

0.5

1.5

PLL CLOCK ENABLED--FIGURE 1a

Input Setup Time (t

)

1.0

Input Hold Time (t

)

2.5

Latch Pulsewidth (t

LPW

)

1.5

PLL CLOCK DISABLED--FIGURE 1b

Input Setup Time (t

)

1.0

Input Hold Time (t

)

2.5

Latch Pulsewidth (t

LPW

)

1.5

CLK/PLLLOCK Delay (t

)

NOTES

MOD1 and MOD0 have typical input currents of 120

A while SLEEP has a typical input current of 15

Specifications subject to change without notice.

0.025%

DB0DB13

CLK+ CLK

IOUTA

IOUTB

LPW

Figure 1a. Timing Diagram--PLL Clock Multiplier Enabled

DB0DB13

0.025%

IOUTA

IOUTB

PLLLOCK

CLK+ CLK

LPW

Figure 1b. Timing Diagram--PLL Clock Multiplier Disabled

REV. 0

AD9772

DIGITAL FILTER SPECIFICATIONS

MIN

to T

MAX

, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = 0 V, DVDD = +3 V,

OUTFS

= 20 mA, Differential Transformer Coupled Output, 50

Doubly Terminated, unless otherwise noted)

Parameter

Min

Typ

Max

Units

MAXIMUM INPUT DATA RATE (f

DATA

)

150

MSPS

DIGITAL FILTER CHARACTERISTICS

Passband Width

: 0.005 dB

0.401

OUT

DATA

Passband Width: 0.01 dB

0.404

OUT

DATA

Passband Width: 0.1 dB

0.422

OUT

DATA

Passband Width: 3 dB

0.479

OUT

DATA

LINEAR PHASE (FIR IMPLEMENTATION)

STOPBAND REJECTION

0.606 f

CLOCK

to 1.394 f

CLOCK

GROUP DELAY

Input Clocks

IMPULSE RESPONSE DURATION

40 dB

Input Clocks

60 dB

Input Clocks

NOTES

Excludes sin(x)/x characteristic of DAC.

Defined as the number of data clock cycles between impulse input and peak of output response.

Specifications subject to change without notice.

FREQUENCY DC TO f

DATA

140

0.1

OUTPUT dB

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

20

40

60

80

100

120

Figure 2a. FIR Filter Frequency Response--Baseband Mode

TIME Samples

0.4

NORMALIZED OUTPUT

0.8

0.6

0.4

0.2

Figure 2b. FIR Filter Impulse Response--Baseband Mode

Table I. Integer Filter Coefficients for Interpolation Filter
(43-Tap Half-Band FIR Filter)

Lower

Upper

Integer

Coefficient

Value

H(1)

H(43)

H(2)

H(42)

H(3)

H(41)

H(4)

H(40)

H(5)

H(39)

H(6)

H(38)

H(7)

H(37)

138

H(8)

H(36)

H(9)

H(35)

248

H(10)

H(34)

H(11)

H(33)

419

H(12)

H(32)

H(13)

H(31)

678

H(14)

H(30)

H(15)

H(29)

1083

H(16)

H(28)

H(17)

H(27)

1776

H(18)

H(26)

H(19)

H(25)

3282

H(20)

H(24)

H(21)

H(23)

10364

H(22)

16384

REV. 0

AD9772

ABSOLUTE MAXIMUM RATINGS*

Parameter

With Respect to

Min

Max

Units

AVDD, DVDD, CLKVDD, PLLVDD

ACOM, DCOM, CLKCOM, PLLCOM

0.3

+4.0

AVDD, DVDD, CLKVDD, PLLVDD

4.0

+4.0

ACOM, DCOM, CLKCOM, PLLCOM

0.3

+0.3

REFIO, REFLO, FSADJ, SLEEP

ACOM

0.3

AVDD + 0.3

IOUTA, IOUTB

ACOM

1.0

AVDD + 0.3

DB0DB13, MOD0, MOD1

DCOM

0.3

DVDD + 0.3

CLK+, CLK, PLLLOCK

CLKCOM

0.3

CLKVDD + 0.3

DIV0, DIV1, RESET

CLKCOM

0.3

CLKVDD + 0.3

LPF

PLLCOM

0.3

PLLVDD + 0.3

Junction Temperature

+150

Storage Temperature

+150

Lead Temperature (10 sec)

+300

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device

at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended
periods may effect device reliability.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9772 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option*

AD9772AST

C to +85

48-Lead LQFP

ST-48

AD9772EB

Evaluation Board

*ST = Thin Plastic Quad Flatpack.

THERMAL CHARACTERISTIC
Thermal Resistance

48-Lead LQFP

= 91

C/W

= 28

C/W

REV. 0

AD9772

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

Description

1, 2, 19, 20

DCOM

Digital Common.

DB13

Most Significant Data Bit (MSB).

415

DB12DB1

Data Bits 112.

DB0

Least Significant Data Bit (LSB).

MOD0

Invokes digital high-pass filter response (i.e., "half-wave" digital mixing mode). Active High.

MOD1

Invokes "zero-stuffing" mode. Active High. Note, "quarter-wave" digital mixing occurs with
MOD0 also set HIGH.

23, 24

No Connect, Leave Open.

21, 22, 47, 48

DVDD

Digital Supply Voltage (+2.7 V to +3.6 V).

PLLLOCK

Phase Lock Loop Lock Signal when PLL clock multiplier is enabled. High indicates PLL is
locked to input clock. Provides 1

clock output when PLL clock multiplier is disabled. Maxi-

mum fanout is one (i.e., <10 pF).

RESET

Resets internal divider by bringing momentarily high when PLL is disabled to synchronize inter-
nal 1

clock to the input data and/or multiple AD9772 devices.

27, 28

DIV1, DIV0

DIV1 along with DIV0 sets the PLL's prescaler divide ratio (refer to Table III.)

CLK+

Noniverting input to differential clock. Bias to midsupply (i.e., CLKVDD/2).

CLK

Inverting input to differential clock. Bias to midsupply (i.e., CLKVDD/2).

CLKCOM

Clock Input Common.

CLKVDD

Clock Input Supply Voltage (+2.7 V to +3.6 V).

PLLCOM

Phase Lock Loop Common.

PLLVDD

Phase Lock Loop (PLL) Supply Voltage (+2.7 V to +3.6 V). To disable PLL clock multiplier,
connect PLLVDD to PLLCOM.

LPF

PLL Loop Filter Node.

SLEEP

Power-Down Control Input. Active High. Connect to ACOM if not used.

37, 41, 44

ACOM

Analog Common.

REFLO

Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal
reference.

REFIO

Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie
REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie
REFLO to ACOM). Requires 0.1

F capacitor to ACOM when internal reference activated.

FSADJ

Full-Scale Current Output Adjust.

IOUTB

Complementary DAC Current Output. Full-scale current when all data bits are 0s.

IOUTA

DAC Current Output. Full-scale current when all data bits are 1s.

45, 46

AVDD

Analog Supply Voltage (+2.7 V to +3.6 V).

PIN CONFIGURATION

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

SLEEP

LPF

PLLVDD

PLLCOM

CLKVDD

CLKCOM

CLK

DCOM

(MSB) DB13

DB12

DB11

DB10

DB9

NC = NO CONNECT

DB8

DB7

DB6

DB5

CLK+

DIV0

DIV1

RESET

AD9772

DB4

PLLLOCK

DVDD

AVDD

ACOM

IOUTA

IOUTB

ACOM

FSADJ

REFIO

REFLO

ACOM

DB3

DB2

DB1

(LSB) DB0

MOD0

MOD1

DCOM

DVDD

REV. 0

AD9772

DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normal-
ized to full scale, associated with a 1 LSB change in digital input
code.

Monotonicity

A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.

Offset Error

The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.

Gain Error

The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.

Output Compliance Range

The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.

Temperature Drift

Temperature drift is specified as the maximum change from the
ambient (+25

C) value to the value at either T

MIN

or T

MAX

For offset and gain drift, the drift is reported in ppm of full-
scale range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.

Power Supply Rejection

The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.

Settling Time

The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).

Signal-to-Noise Ratio (SNR)

S/N is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.

Passband

Frequency band in which any input applied therein passes
unattenuated to the DAC output.

Stopband Rejection

The amount of attenuation of a frequency outside the passband
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the passband.

Group Delay

Number of input clocks between an impulse applied at the
device input and peak DAC output current.

Impulse Response

Response of the device to an impulse applied to the input.

Adjacent Channel Power Ratio (or ACPR)

A ratio in dBc between the measured power within a channel
relative to its adjacent channel.

AD9772

3.0V

FROM HP8644A

SIGNAL GENERATOR

3.0V

CLKVDD

CLKCOM

CLK+

FILTER

CONTROL

MUX

CONTROL

MOD0

MOD1

RESET

PLLLOCK

DIV0

DIV1

PLLCOM

LPF

PLLVDD

IOUTA

IOUTB

REFIO

FSADJ

REFLO

AVDD

ACOM

DVDD

DCOM

SLEEP

EDGE-

TRIGGERED

LATCHES

ZERO

STUFF

MUX

14-BIT DAC

100

MINI-CIRCUITS

T11T

20pF

1.91k

0.1 F

+1.2V REFERENCE

AND CONTROL AMP

AWG2021

DG2020

DIGITAL

DATA

EXT.

CLOCK

HP8130

PULSE GENERATOR

CH1

CH2

EXT. INPUT

PLLCLOCK

MULTIPLIER

2 /4

CLK

1 /2

CLOCK DISTRIBUTION

AND MODE SELECT

2 FIR

INTERPOLATION

FILTER

TO FSEA30

SPECTRUM

ANALYZER

Figure 3. Basic AC Characterization Test Setup

REV. 0

AD9772

Typical AC Characterization Curves

(AVDD = +3 V, CLKVDD = +3 V, PLLVDD = 0 V, DVDD = +3 V, I

OUTFS

= 20 mA, PLL Disabled)

FREQUENCY MHz

dBm

90

30

40

50

60

10

20

70

80

INBAND

OUT-OF-BAND

Figure 4. Single-Tone Spectral Plot
@ f

DATA

= 25 MSPS with f

OUT

= f

DATA

FREQUENCY MHz

dBm

90

30

50

10

70

100

120

20

40

60

80

INBAND

OUT-OF-BAND

Figure 7. Single-Tone Spectral Plot
@ f

DATA

= 65 MSPS with f

OUT

= f

DATA

FREQUENCY MHz

dBm

90

30

50

10

70

100

150

200

250

300

INBAND

OUT-OF-BAND

Figure 10. Single-Tone Spectral Plot
@ f

DATA

= 150 MSPS with f

OUT

= f

DATA

OUT

 MHz

SFDR dBc

0dBFS

12dBFS

6dBFS

Figure 5. "In-Band" SFDR vs. f

OUT

@ f

DATA

= 25 MSPS

OUT

 MHz

SFDR dBc

0dBFS

12dBFS

6dBFS

Figure 8. "In-Band" SFDR vs. f

OUT

@ f

DATA

= 65 MSPS

OUT

 MHz

SFDR dBc

0dBFS

12dBFS

6dBFS

Figure 11. "In-Band" SFDR vs. f

OUT

@ f

DATA

= 150 MSPS

OUT

 MHz

SFDR dBc

0dBFS

12dBFS

6dBFS

Figure 6. "Out-of-Band" SFDR vs.
f

OUT

@ f

DATA

= 25 MSPS

OUT

 MHz

SFDR dBc

0dBFS

12dBFS

6dBFS

Figure 9. "Out-of-Band" SFDR vs.
f

OUT

@ f

DATA

= 65 MSPS

OUT

 MHz

SFDR dBc

0dBFS

12dBFS

6dBFS

Figure 12. "Out-of-Band" SFDR vs.
f

OUT

@ f

DATA

= 150 MSPS

REV. 0

AD9772

OUT

 dBFS

SFDR dBc

25

20

15

10

DATA

= 25MSPS

DATA

= 10MSPS

DATA

= 65MSPS

DATA

= 150MSPS

Figure 13. "In-Band" Single-Tone
SFDR vs. A

OUT

@ f

OUT

= f

DATA

/11

OUT

 dBFS

SFDR dBc

25

20

15

10

DATA

= 25MSPS

DATA

= 10MSPS

DATA

= 65MSPS

DATA

= 150MSPS

Figure 16. "In-Band" Single-Tone
SFDR vs. A

OUT

@ f

OUT

= f

DATA

TEMPERATURE C

SFDR dBc

50

10

DATA

@ 150MSPS

30

110

Figure 19. "In-Band" Single-Tone
SFDR vs. Temperature @ f

OUT

= 5 MHz,

OUT

= 0 dBFS

OUT

 dBFS

SFDR dBc

25

20

15

10

DATA

= 25MSPS

DATA

= 10MSPS

DATA

= 65MSPS

DATA

= 150MSPS

Figure 14 "In-Band" Dual-Tone SFDR
vs. A

OUT

@ f

OUT

= f

DATA

/11

OUT

 dBFS

SFDR dBc

25

20

15

10

DATA

= 25MSPS

DATA

= 10MSPS

DATA

= 65MSPS

DATA

= 150MSPS

Figure 17. "In-Band" Dual-Tone
SFDR vs. A

OUT

@ f

OUT

= f

DATA

AVDD Volts

SFDR dBc

2.5

3.7

2.7

2.9

3.1

3.3

3.5

DATA

= 25MSPS

DATA

= 10MSPS

DATA

= 65MSPS

DATA

= 150MSPS

Figure 20. "In-Band" Dual-Tone
SFDR vs. AVDD @ f

OUT

= f

DATA

/4,

OUT

= 0 dBFS

OUT

 dBFS

SNR dBFS

25

20

15

10

DATA

@ 150MSPS

DATA

@ 65MSPS

DATA

@ 25MSPS

Figure 15. "In-Band" Single-Tone
SNR vs. A

OUT

@ f

OUT

= f

DATA

/11

OUT

 dBFS

SNR dBFS

25

20

15

10

DATA

@ 150MSPS

DATA

@ 65MSPS

DATA

@ 25MSPS

Figure 18. "In-Band" Dual-Tone
SNR vs. A

OUT

@ f

OUT

= f

DATA

TEMPERATURE C

SFDR dBc

50

30

10

110

DATA

= 25MSPS

DATA

= 10MSPS

DATA

= 65MSPS

DATA

= 150MSPS

Figure 21. "In-Band" Single-Tone
SFDR vs. Temperature @ f

OUT

DATA

/11, A

OUT

= 0 dBFS

REV. 0

AD9772

FUNCTIONAL DESCRIPTION

Figure 22 shows a simplified block diagram of the AD9772.
The AD9772 is a complete, 2

oversampling, 14-bit DAC that

includes a 2

interpolation filter, a phase-locked loop (PLL)

clock multiplier and a 1.20 V bandgap voltage reference. While
the AD9772's digital interface can support input data rates as
high as 150 MSPS, its internal DAC can operate up to 400 MSPS,
thus providing direct IF conversion capabilities. The 14-bit
DAC provides two complementary current outputs whose full-
scale current is determined by an external resistor. The AD9772
features a flexible, low jitter, differential clock input providing
excellent noise rejection while accepting a sine wave input. An
on-chip PLL clock multiplier produces all of the necessary
synchronized clocks from an external reference clock source.
Separate supply inputs are provided for each functional block to
ensure optimum noise and distortion performance. A SLEEP
mode is also included for power savings.

14-BIT DAC

ZERO

STUFF

MUX

2 FIR

INTERPOLATION

FILTER

EDGE-

TRIGGERED

LATCHES

CLOCK DISTRIBUTION

AND MODE SELECT

2 /4

MUX

CONTROL

FILTER

CONTROL

1 /2

PLL CLOCK

MULTIPLIER

+1.2V REFERENCE

AND CONTROL AMP

AD9772

CLKCOM CLKVDD

MOD0 MOD1

RESET

PLLLOCK

DIV0 DIV1

CLK+

CLK

DATA

INPUTS

(DB13...DB0)

SLEEP

DCOM

DVDD

ACOM

AVDD

REFLO

PLLCOM

LPF

PLLVDD

IOUTA

IOUTB

REFIO

FSADJ

Figure 22. Functional Block Diagram

Preceding the 14-bit DAC is a 2

digital interpolation filter that

can be configured for a low pass (i.e., baseband mode) or high
pass (i.e., direct IF mode) response. The input data is latched
into the edge-triggered input latches on the rising edge of the
differential input clock as shown in Figure 1a and then interpo-
lated by a factor of two by the digital filter. For traditional base-
band applications, the 2

interpolation filter has a low pass

response. For direct IF applications, the filter's response can be
converted into a high pass response to extract the higher image.
The output data of the 2

interpolation filter can update the

14-bit DAC directly or undergo a "zero-stuffing" process to
increase the DAC update rate by another factor of two. This
action enhances the relative signal level and passband flatness of
the higher images.

DIGITAL MODES OF OPERATION

The AD9772 features four different digital modes of operation
controlled by the digital inputs, MOD0 and MOD1. MOD0
controls the 2

digital filter's response (i.e., low pass or high

pass), while MOD1 controls the "zero-stuffing" option. The
selected mode as shown in Table II will depend on whether the
application requires the reconstruction of a baseband or IF signal.

Table II. Digital Modes

Digital

Zero-

Mode

MOD0

MOD1

Filter

Stuffing

Baseband

Low

Baseband

Low

Yes

Direct IF

High

Direct IF

High

Yes

Applications requiring the highest dynamic range over a wide
bandwidth should consider operating the AD9772 in a baseband
mode. Note, the "zero-stuffing" option can also be used in this
mode although the ratio of signal to image power will be re-
duced. Applications requiring the synthesis of IF signals should
consider operating the AD9772 in a Direct IF mode. In this
case, the "zero-stuffing" option should be considered when
synthesizing and selecting IFs beyond the input data rate, f

DATA

If the reconstructed IF falls below f

DATA

, the "zero-stuffing"

option may or may not be beneficial. Note, the dynamic range
(i.e., SNR/SFDR) is also optimized by disabling the PLL Clock
Multiplier (i.e., PLLVDD to PLLCOM) and using an external
low jitter clock source operating at the DAC update rate, f

DAC

2 Interpolation Filter Description

The 2

interpolation filter is based on a 43-tap half-band sym-

metric FIR topology that can be configured for a low or high
pass response, depending on state of the MOD0 control input.
The low pass response is selected with MOD0 LOW while the
high pass response is selected with MOD0 HIGH. The low pass
frequency and impulse response of the half-band interpolation
filter are shown in Figures 2a and 2b, while Table I lists the
idealized filter coefficients. Note, a FIR filter's impulse response
is also represented by its idealized filter coefficients.

The 2

interpolation filter essentially multiplies the input data

rate to the DAC by a factor of two, relative to its original input
data rate, while simultaneously reducing the magnitude of the
1st image associated with the original input data rate occurring
at f

DATA

FUNDAMENTAL

. Note, as a result of the 2

interpola-

tion, the digital filter's frequency response is uniquely defined
over its Nyquist zone of dc to f

DATA

, with mirror images occur-

ring in adjacent Nyquist zones.

The benefits of an interpolation filter are clearly seen in Figure
23, which shows an example of the frequency and time domain
representation of a discrete time sine wave signal before and
after it is applied to the 2

digital interpolation filter in a low

pass configuration. Images of the sine wave signal appear around
multiples of the DAC's input data rate (i.e., f

DATA

) as predicted

by sampling theory. These undesirable images will also appear
at the output of a reconstruction DAC, although attenuated by
the DAC's sin(x)/x roll-off response.

In many bandlimited applications, the images from the recon-
struction process must be suppressed by an analog filter follow-
ing the DAC. The complexity of this analog filter is typically
determined by the proximity of the desired fundamental to the
first image and the required amount of image suppression. Add-
ing to the complexity of this analog filter may be the require-
ment of compensating for the DAC's sin(x)/x response.

REV. 0

AD9772

Referring to Figure 23, the "new" 1st image associated with the
DAC's higher data rate after interpolation is "pushed" out fur-
ther relative to the input signal, since it now occurs at 2

DATA

FUNDAMENTAL

. The "old" first image associated with the lower

DAC data rate before interpolation is suppressed by the digital
filter. As a result, the transition band for the analog reconstruc-
tion filter is increased, thus reducing the complexity of the ana-
log filter. Furthermore, the sin(x)/x roll-off over the original
input data passband (i.e., dc to f

DATA

/2) is significantly reduced.

As previously mentioned, the 2

interpolation filter can be con-

verted into a high pass response, thus suppressing the "funda-
mental" while passing the "original" 1st image occurring at
f

DATA

FUNDAMENTAL

. Figure 24 shows the time and frequency

representation for a high pass response of a discrete time sine
wave. This action can also be modeled as a "1/2 wave" digital
mixing process in which the impulse response of the low-pass
filter is digitally mixed with a square wave having a frequency of

INTERPOLATION FILTER

DATA

INPUT DATA LATCH

DATA

DAC

DATA

DAC'S SIN (X)/X

RESPONSE

IMAGE

SUPPRESSED

IMAGE

DATA

FUNDAMENTAL

DIGITAL

FILTER

RESPONSE

NEW

IMAGE

DATA

FUNDAMENTAL

FREQUENCY

DOMAIN

1/ 2

DATA

TIME

DOMAIN

Figure 23. Time and Frequency Domain Example of Low-Pass 2

Digital Interpolation Filter

2 INTERPOLATION FILTER

DATA

INPUT DATA LATCH

DATA

DAC

DATA

DAC'S SIN (X)/X

RESPONSE

IMAGE

SUPPRESSED

FUNDAMENTAL

DATA

DIGITAL

FILTER

RESPONSE

UPPER AND

LOWER

IMAGE

DATA

FUNDAMENTAL

FREQUENCY

DOMAIN

DATA

TIME

DOMAIN

Figure 24. Time and Frequency Domain Example of High-Pass 2

Digital Interpolation Filter

exactly f

DATA

/2. Since the even coefficients have a zero value

(refer to Table I), this process simplifies into inverting the cen-
ter coefficient of the low-pass filter (i.e., invert H(18)). Note,
this also corresponds into inverting the peak of the impulse
response shown in Figure 2a. The resulting high pass frequency
response becomes the frequency inverted mirror image of the
low-pass filter response shown in Figure 2b.

It is worth noting that the "new" 1st image now occurs at
f

DATA

+ f

FUNDAMENTAL

. A reduced transition region of 2

FUNDAMENTAL

exists for image selection, thus mandating that

the f

FUNDAMENTAL

be placed sufficiently high for practical filter-

ing purposes in direct IF applications. Also, the "lower sideband
images" occurring at f

DATA

FUNDAMENTAL

and its multiples

(i.e., N

DATA

FUNDAMENTAL

) experience a frequency inver-

sion while the "upper sideband images" occurring at f

DATA

FUNDAMENTAL

and its multiples (i.e., N

DATA

+ f

FUNDAMENTAL

)

do not.

REV. 0

AD9772

"Zero Stuffing" Option Description
As shown in Figure 25, a "zero" or null in the frequency re-
sponses (after interpolation and DAC reconstruction) occurs at
the final DAC update rate (i.e., 2

DATA

) due to the DAC's

inherent sin(x)/x roll-off response. In baseband applications, this
roll-off in the frequency response may not be as problematic
since much of the desired signal energy remains below f

DATA

and the amplitude variation is not as severe. However, in direct
IF applications interested in extracting an image above f

DATA

/2,

this roll-off may be problematic due to the increased passband
amplitude variation as well as the reduced signal level of the
higher images.

FREQUENCY 

DATA

10

40

0.5

1.5

2.5

3.5

20

30

WITH

"ZERO-STUFFING"

WITHOUT

"ZERO-STUFFING"

BASEBAND

REGION

dBFS

Figure 25. Effects "Zero-Stuffing" on DAC's Sin(x)/x
Response

For instance, if the digital data into the AD9772 represented a
baseband signal centered around f

DATA

/4 with a passband of

DATA

/10, the reconstructed baseband signal out of the AD9772

would experience only a 0.18 dB amplitude variation over its
passband with the "1st image" occurring at 7/4 f

DATA

with 17 dB

of attenuation relative to the fundamental. However, if the high-
pass filter response was selected, the AD9772 would now pro-
duce pairs of images at [(2N + 1)

DATA

]

DATA

/4 where N =

0, 1 . . .. Note, due to the DAC's sin(x)/x response, only the
lower or upper sideband images centered around f

DATA

may be

useful although they would be attenuated by 2.1 dB and
6.54 dB respectively as well as experience a passband ampli-
tude roll-off of 0.6 dB and 1.3 dB.

To improve upon the passband flatness of the desired image
and/or to extract higher images (i.e., 3

DATA

FUNDAMENTAL

)

the "zero-stuffing" option should be employed by bringing the
MOD1 pin HIGH. This option increases the effective DAC
update rate by another factor of two since a "midscale" sample
(i.e., 10 0000 0000 0000) is inserted after every data sample
originating from the 2

interpolation filter. A digital multiplexer

switching at a rate of 4

DATA

between the interpolation filter's

output and a data register containing the "midscale" data sample is
used to implement this option as shown in Figure 24. Hence,
the DAC output is now forced to return to its differential mid-
scale current value (i.e., IOUTAIOUTB

0 mA) after recon-

structing each data sample from the digital filter.

The net effect is to increase the DAC update rate such that the
"zero" in the sin(x)/x frequency response now occurs at 4

DATA

along with a corresponding reduction in output power as

shown in Figure 25. Note, if the 2

interpolation filter's high

pass response is also selected, this action can be modeled as a
"1/4 wave" digital mixing process since this is equivalent to
digitally mixing the impulse response of the low-pass filter with
a square wave having a frequency of exactly f

DATA

(i.e., f

DAC

/4).

It is important to realize that the "zero stuffing" option by itself
does not change the location of the images but rather their signal
level, amplitude flatness and relative weighting. For instance, in
the previous example, the passband amplitude flatness of the
lower and upper sideband images centered around f

DATA

are

improved to 0.14 dB and 0.24 dB respectively, while the signal
level has changed to 6.5 dBFS and 7.5 dBFS. The lower or
upper sideband image centered around 3

DATA

will exhibit an

amplitude flatness of 0.77 dB and 1.29 dB with signal levels of
approximately 14.3 dBFS and 19.2 dBFS.

PLL CLOCK MULTIPLIER OPERATION

The Phase Lock Loop (PLL) clock multiplier circuitry along
with the clock distribution circuitry can produce the neces-
sary internally synchronized 1

, 2

, and 4

clocks for the edge

triggered latches, 2

interpolation filter, "zero stuffing" multi-

plier, and DAC. Figure 26 shows a functional block diagram of
the PLL clock multiplier, which consists of a phase detector, a
charge pump, a voltage controlled oscillator (VCO), a prescaler,
and digital control inputs/outputs. The clock distribution
circuitry generates all the internal clocks for a given mode of
operation. The charge pump and VCO are powered from
PLLVDD while the differential clock input buffer, phase detec-
tor, prescaler and clock distribution circuitry are powered from
CLKVDD. To ensure optimum phase noise performance from
the PLL clock multiplier and clock distribution circuitry,
PLLVDD and CLKVDD must originate from the same clean
analog supply.

EXT/INT

CLOCK CONTROL

PRESCALER

CHARGE

PUMP

PHASE

DETECTOR

CLKVDD

OUT1

CLKCOM

MOD1

MOD0

RESET

CLK+

LPF

PLL

VDD

392

1.0 F

+2.7V TO
+3.6V

PLL

COM

DIV1

DIV0

CLOCK

DISTRIBUTION

PLLLOCK

CLK

VCO

AD9772

Figure 26. Clock Multiplier with PLL Clock Multiplier
Enabled

REV. 0

AD9772

The PLL clock multiplier has two modes of operation. It can be
enabled for less demanding applications providing a reference
clock meeting the minimum specified input data rate of 6 MSPS.
It can be disabled for applications below this data rate or for
applications requiring higher phase noise performance. In this
case, a reference clock at twice the input data rate (i.e., 2

DATA

)

must be provided without the "zero stuffing" option selected and
four times the input data rate (i.e., 4

DATA

) with the "zero

stuffing" option selected. Note, multiple AD9772 devices can
be synchronized in either mode if driven by the same reference
clock since the PLL clock multiplier when enabled ensures
synchronization. RESET can be used for synchronization if the
PLL clock multiplier is disabled.

Figure 26 shows the proper configuration used to enable the
PLL clock multiplier. In this case, the external clock source is
applied to CLK+ (and/or CLK) and the PLL clock multiplier is
fully enabled by connecting PLLVDD to CLKVDD. An external
PLL loop filter consisting of a series resistor and ceramic capaci-
tor connected from the output of the charge pump (i.e., LPF) to
PLLVDD is required for stability of the PLL. Also, a shield
surrounding these components is recommended to minimize
external noise coupling into the VCO input.

The components values shown (i.e., 392

and

1.0

F) were

selected to optimize the phase noise vs. settling/acquisition time
characteristics of the PLL. The settling/acquisition time character-
istics are also dependent on the divide-by-N ratio as well as the
input data rate. In general, the acquisition time increases with
increasing data rate (for fixed divide-by-N ratio) or increasing
divide-by-N ratio (for fixed input data rate).

Since the VCO can operate over a 96 MHz400 MHz range,
the prescaler divide-by-ratio following the VCO must be set
according to Table III for a given input data rate (i.e., f

DATA

)

to ensure optimum phase noise and successful "locking." In
general, the best phase noise performance for any prescaler
setting is achieved with the VCO operating near its maximum
output frequency of 400 MHz. Note, the divide-by-N ratio
also depends on whether the "zero stuffing" option is enabled
since this option requires the DAC to operate at four times
the input data rate. The divide-by-N ratio is set by DIV1 and
DIV0.

Table III. Recommended Prescaler Divide-by-N Ratio Settings

DATA

Divide-by-N

(MSPS)

MOD1

DIV1

DIV0

Ratio

48150

24100

1250

625

24100

1250

625

312.5

With the PLL clock multiplier enabled, PLLLOCK serves as an
active HIGH control output which may be monitored upon sys-
tem power-up to indicate that the PLL is successfully "locked" to
the input clock. Note, when the PLL clock multiplier is NOT
locked, PLLLOCK will toggle between logic HIGH and LOW
in an asynchronous manner until locking is finally achieved.

As a result, it is recommended that PLLLOCK, if monitored,
be sampled several times to detect proper locking 100 ms
upon power-up.

As stated earlier, applications requiring input data rates below
6 MSPS must disable the PLL clock multiplier and provide an
external reference clock. However, applications already contain-
ing a low phase noise (i.e., jitter) reference clock that is twice
(or four times) the input data rate should consider disabling the
PLL clock multiplier to achieve the best SNR performance from
the AD9772. Note, the SFDR performance and wideband noise
performance of the AD9772 remains unaffected with or without
the PLL clock multiplier enabled.

The effects of phase noise on the AD9772's SNR performance
becomes more noticeable at higher reconstructed output fre-
quencies and signal levels. Figure 27 compares the phase noise
of a full-scale sine wave at exactly f

DATA

/4 at different data rates

(hence carrier frequency) with the optimum DIV1, DIV0 set-
ting. The effects of phase noise, and its effect on a signal's CNR
performance, becomes even more evident at higher IF fre-
quencies as shown in Figure 28. In both instances, it is the
"narrowband" phase noise that limits the CNR performance.

FREQUENCY OFFSET MHz

20

100

40

60

80

50 MSPS WITH DIV4

100 MSPS WITH DIV2

75 MSPS WITH DIV2

WITHOUT PLL

150 MSPS WITH DIV1

dBm

Figure 27. Phase Noise of PLL Clock Multiplier @ Exactly
f

OUT

= f

DATA

/4 at Different f

DATA

Settings with Optimum

DIV0/DIV1 Settings Using R & S FSEA30 Spectrum
Analyzer

FREQUENCY MHz

20

100

150

110

120

130

140

40

60

80

dBm

PLL WITH DIV = 8

WITHOUT PLL

Figure 28. Direct IF Mode Reveals Phase Noise Degrada-
tion With and Without PLL Clock Multiplier (IF = 125 MHz
and f

DATA

= 100 MSPS)

REV. 0

AD9772

To disable the PLL Clock Multiplier, connect PLLVDD to
PLLCOM as shown in Figure 29. LPF may remain open since
this portion of the PLL circuitry is now disabled. The differen-
tial clock input should be driven with a reference clock twice the
data input rate in baseband applications and four time the data
input rate in direct IF applications in which the "1/4 wave"
mixing option is employed (i.e., MOD1 and MOD0 active
HIGH). The clock distribution circuitry remains enabled pro-
viding a 1

internal clock at PLLLOCK. Since the digital input

data is latched into the AD9772 with respect to the rising edge
of the 1

clock appearing at PLLLOCK, adequate setup and

hold time for the input data as shown in Figure 1b should be
allowed. Since PLLLOCK contains a weak driver output, its
output delay (t

) is sensitive to output capacitance loading.

Thus PLLLOCK should be buffered for fanouts greater than
one and/or load capacitance greater than 10 pF. If a data timing
issue exists between the AD9772 and its external driver device,
the 1

clock appearing at PLLLOCK can be inverted via an

external gate to ensure proper setup and hold time.

EXT/INT

CLOCK CONTROL

PRESCALER

CHARGE

PUMP

PHASE

DETECTOR

CLKVDD

OUT1

CLKCOM

MOD1

MOD0

RESET

CLK+

LPF

PLL

VDD

PLL

COM

DIV1

DIV0

CLOCK

DISTRIBUTION

PLLLOCK

VCO

AD9772

CLK

Figure 29. Clock Multiplier with PLL CLOCK Multiplier
Disabled

CLOCK DOUBLER APPLICATION

A low phase noise 2

clock can be derived from a 1

clock by

using the clock doubler circuit shown in Figure 30. This circuit
is based on a low cost mixer (i.e., Mini-Circuits ADE-1) whose
IF and LO ports are driven with the same single-ended 1

sine

wave source via R-C quadrature phase shifting networks. Note it
is necessary to drive the IF and LO port with quadrature sine
waves to optimize the 2

clock signal level appearing at the RF

port. The value of R should be selected to match the source
resistance of the sine wave source (i.e., 50

) while the value of

C should be selected such that the R-C cut-off frequency (i.e.,
f

3 dB

) occurs at approximately the 1

clock frequency. The

AD9772 differential CLK input is driven single-ended by the
mixer's RF port while a low impedance common-mode voltage
of CLKVDD/2 for both devices is established by a 1 k

resistor

divider and 0.1

F capacitor. The AD9772 experiences negli-

gible degradation in its noise floor due to additive clock jitter
with this clock doubler circuit as long as it is driven by a low
noise sine wave source.

0.1 F

C
33pF

33pF

CLKVDD

CLK+

CLK

AD9772

SINE

WAVE

CLOCK

MINI-CIRCUITS

ADE-1

Figure 30. Low Cost Clock Doubler Circuit Achieves Low
Phase Noise Performance

DAC OPERATION

The 14-bit DAC along with the 1.2 V reference and reference
control amplifier is shown in Figure 31. The DAC consists of a
large PMOS current source array capable of providing up to
20 mA of full-scale current, I

OUTFS

. The array is divided into

thirty-one equal currents that make up the five most significant
bits (MSBs). The next four bits, or middle bits, consist of 15
equal current sources whose values are 1/16th of an MSB
current source. The remaining LSBs are binary weighted frac-
tions of the middle-bits' current sources. All of these current
sources are switched to one or the other of two output nodes
(i.e., IOUTA or IOUTB) via PMOS differential current switches.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
DAC's high output impedance.

The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, R

SET

. The external resistor, in combination with

both the reference control amplifier and voltage reference,
REFIO, sets the reference current, I

REF

, which is mirrored over

to the segmented current sources with the proper scaling factor.
The full-scale current, I

OUTFS

, is exactly thirty-two times the

value of I

REF

REFIO

FSADJ

250pF

REFLO

AVDD

AD9772

SET

0.1 F

ACOM

CURRENT

SOURCE

ARRAY

IOUTA

IOUTB

INTERPOLATED

DIGITAL DATA

LOAD

DIFF

= V

OUTA

 V

OUTB

IOUTA

IOUTB

SEGMENTED

SWITCHES

LSB

SWITCHES

+1.2V REF

+2.7V TO +3.6V

REF

Figure 31. Block Diagram of Internal DAC, 1.2 V Refer-
ence, and Reference Control Circuits

DAC TRANSFER FUNCTION

The AD9772 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current out-
put, I

OUTFS

, when all bits are high (i.e., DAC CODE = 16383)

while IOUTB, the complementary output, provides no current.

REV. 0

AD9772

The current output appearing at IOUTA and IOUTB is a func-
tion of both the input code and I

OUTFS

and can be expressed as:

IOUTA = (DAC CODE/16384)

OUTFS

(1)

IOUTB = (16383 DAC CODE)/16384

OUTFS

(2)

where DAC CODE = 0 to 16383 (i.e., Decimal Representation).

As previously mentioned, I

OUTFS

is a function of the reference

current I

REF

, which is nominally set by a reference voltage

REFIO

, and external resistor, R

SET

. It can be expressed as:

OUTFS

= 32

REF

(3)

where

REF

= V

REFIO

SET

(4)

The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R

LOAD

, that are tied to analog common, ACOM. Note

that R

LOAD

may represent the equivalent load resistance seen by

IOUTA or IOUTB as would be the case in a doubly terminated
50

or 75

cable. The single-ended voltage output appearing

at the IOUTA and IOUTB nodes is simply:

OUTA

= IOUTA

LOAD

(5)

OUTB

= IOUTB

LOAD

(6)

Note that the full-scale value of V

OUTA

and V

OUTB

should not

exceed the specified output compliance range of 1.25 V to pre-
vent signal compression. To maintain optimum distortion and
linearity performance, the maximum voltages at V

OUTA

and

OUTB

should not exceed

500 mV p-p.

The differential voltage, V

DIFF

, appearing across IOUTA and

IOUTB, is:

DIFF

= (IOUTA IOUTB)

LOAD

(7)

Substituting the values of IOUTA, IOUTB and I

REF

; V

DIFF

can

be expressed as:

DIFF

= [(2 DAC CODE 16383)/16384]

(32 R

LOAD

SET

)

REFIO

(8)

The last two equations highlight some of the advantages of
operating the AD9772 differentially. First, the differential
operation will help cancel common-mode error sources such as
noise, distortion and dc offsets associated with IOUTA and
IOUTB. Second, the differential code-dependent current and
subsequent voltage, V

DIFF

, is twice the value of the single-ended

voltage output (i.e., V

OUTA

or V

OUTB

), thus providing twice the

signal power to the load.

Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (V

DIFF

) of

the AD9772 can be enhanced by selecting temperature tracking
resistors for R

LOAD

and R

SET

due to their ratiometric relation-

ship as shown in Equation 8.

REFERENCE OPERATION

The AD9772 contains an internal 1.20 V bandgap reference
that can easily be disabled and overridden by an external
reference. REFIO serves as either an output or input, depending
on whether the internal or external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 32, the internal
reference is activated, and REFIO provides a 1.20 V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1

F or greater from REFIO

to REFLO. If any additional loading is required, REFIO should
be buffered with an external amplifier having an input bias cur-
rent less than 100 nA.

+1.2V REF

REFIO

FSADJ

CURRENT

SOURCE

ARRAY

250pF

REFLO

AVDD

AD9772

0.1 F

ADDITIONAL

LOAD

OPTIONAL

EXTERNAL

REF BUFFER

+2.7V TO +3.6V

Figure 32. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external 1.2 V reference such as the
AD1580 may then be applied to REFIO as shown in Figure 33.
The external reference may provide either a fixed reference
voltage to enhance accuracy and drift performance or a varying
reference voltage for gain control. Note that the 0.1

F compen-

sation capacitor is not required since the internal reference is
disabled, and the high input impedance of REFIO minimizes
any loading of the external reference.

+1.2V REF

REFIO

FSADJ

CURRENT

SOURCE

ARRAY

250pF

REFLO

AVDD

AD9772

AD1580

+2.7 TO +3.6V

REFERENCE

CONTROL

AMPLIFIER

SET

REF

REFIO

SET

10k

REFIO

Figure 33. External Reference Configuration

REFERENCE CONTROL AMPLIFIER

The AD9772 also contains an internal control amplifier that is
used to regulate the DAC's full-scale output current, I

OUTFS

The control amplifier is configured as a V-I converter, as shown
in Figure 33, such that its current output, I

REF

, is determined by

the ratio of the V

REFIO

and an external resistor, R

SET

, as stated

in Equation 4. I

REF

is copied over to the segmented current

sources with the proper scaling factor to set I

OUTFS

as stated in

Equation 3.

The control amplifier allows a wide (10:1) adjustment span of
I

OUTFS

over a 2 mA to 20 mA range by setting I

REF

between

62.5

A and 625

A. The wide adjustment span of I

OUTFS

provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9772's DAC, which
is proportional to I

OUTFS

(refer to the Power Dissipation sec-

tion). The second benefit relates to the 20 dB adjustment, which
is useful for system gain control purposes.

REF

can be controlled using the single-supply circuit shown in

Figure 34 for a fixed R

SET

. In this example, the internal refer-

ence is disabled, and the voltage of REFIO is varied over its
compliance range of 1.25 V to 0.10 V. REFIO can be driven

REV. 0

AD9772

by a single-supply DAC or digital potentiometer, thus allowing
I

REF

to be digitally controlled for a fixed R

SET

. This particular

example shows the AD5220, an 8-bit serial input digital potenti-
ometer, along with the AD1580 voltage reference. Note, since
the input impedance of REFIO does interact and load the digi-
tal potentiometer wiper to create a slight nonlinearity in the
programmable voltage divider ratio, a digital potentiometer with
10 k

or less of resistance is recommended.

+1.2V REF

REFIO

FSADJ

CURRENT

SOURCE

ARRAY

250pF

REFLO

AVDD

AD9772

AD1580

+2.7 TO +3.6V

SET

10k

AD5220

1.2V

Figure 34. Single-Supply Gain Control Circuit

ANALOG OUTPUTS

The AD9772 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-ended
or differential operation. IOUTA and IOUTB can be converted
into complementary single-ended voltage outputs, V

OUTA

and

OUTB

, via a load resistor, R

LOAD

, as described in the DAC

Transfer Function section, by Equations 5 through 8. The
differential voltage, V

DIFF

, existing between V

OUTA

and V

OUTB

can also be converted to a single-ended voltage via a transformer
or differential amplifier configuration.

Figure 35 shows the equivalent analog output circuit of the
AD9772, consisting of a parallel combination of PMOS differ-
ential current switches associated with each segmented current
source. The output impedance of IOUTA and IOUTB is deter-
mined by the equivalent parallel combination of the PMOS
switches and is typically 200 k

in parallel with 3 pF. Due to

the nature of a PMOS device, the output impedance is also
slightly dependent on the output voltage (i.e., V

OUTA

and V

OUTB

)

and, to a lesser extent, the analog supply voltage, AVDD, and
full-scale current, I

OUTFS

. Although the output impedance's

signal dependency can be a source of dc nonlinearity and ac linear-
ity (i.e., distortion), its effects can be limited if certain precau-
tions are noted.

AD9772

AVDD

IOUTA

IOUTB

LOAD

Figure 35. Equivalent Analog Output Circuit

IOUTA and IOUTB also have a negative and positive voltage
compliance range. The negative output compliance range of
1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a break-
down of the output stage and affect the reliability of the AD9772.
The positive output compliance range is slightly dependent on
the full-scale output current, I

OUTFS

. Operation beyond the

positive compliance range will induce clipping of the output
signal, which severely degrades the AD9772's linearity and
distortion performance.

Operating the AD9772 with reduced voltage output swings at
IOUTA and IOUTB in a differential or single-ended output
configuration reduces the signal dependency of its output im-
pedance, thus enhancing distortion performance. Although the
voltage compliance range of IOUTA and IOUTB extends from
1.0 V to +1.25 V, optimum distortion performance is achieved
when the maximum full-scale signal at IOUTA and IOUTB
does not exceed approximately 0.5 V. A properly selected trans-
former with a grounded center-tap will allow the AD9772 to
provide the required power and voltage levels to different loads
while maintaining reduced voltage swings at IOUTA and
IOUTB. DC-coupled applications requiring a differential or
single-ended output configuration should size R

LOAD

accord-

ingly. Refer to Applying the AD9772 section for examples of
various output configurations.

The most significant improvement in the AD9772's distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both IOUTA
and IOUTB can be substantially reduced by the common-mode
rejection of a transformer or differential amplifier. These
common-mode error sources include even-order distortion
products and noise. The enhancement in distortion performance
becomes more significant as the reconstructed waveform's
frequency content increases and/or its amplitude decreases.
The distortion and noise performance of the AD9772 is also
dependent on the full-scale current setting, I

OUTFS

. Although

OUTFS

can be set between 2 mA and 20 mA, selecting an I

OUTFS

of 20 mA will provide the best distortion and noise performance.

In summary, the AD9772 achieves the optimum distortion and
noise performance under the following conditions:

1. Positive voltage swing at IOUTA and IOUTB limited to

+0.5 V.

2. Differential Operation.

3. I

OUTFS

set to 20 mA.

4. PLL Clock Multiplier Disabled

Note the majority of the AC Characterization Curves for the
AD9772 are performed under the above-mentioned operating
conditions.

DIGITAL INPUTS/OUTPUTS

The AD9772 consists of several digital input pins used for data,
clock and control purposes. It also contains a single digital out-
put pin, PLLLOCK, used to monitor the status of the internal
PLL clock multiplier or provide a 1

clock output. The 14-bit

parallel data inputs follow standard positive binary coding where
DB13 is the most significant bit (MSB), and DB0 is the least
significant bit (LSB). IOUTA produces a full-scale output
current when all data bits are at Logic 1. IOUTB produces a

REV. 0

AD9772

complementary output with the full-scale current split between
the two outputs as a function of the input code.

The digital interface is implemented using an edge-triggered
master slave latch and is designed to support an input data rate
as high as 150 MSPS. The clock can be operated at any duty
cycle that meets the specified latch pulsewidth as shown in Figures
1a and 1b. The setup and hold times can also be varied within
the clock cycle as long as the specified minimum times are
met. The digital inputs (excluding CLK+ and CLK) are CMOS-
compatible with its logic thresholds, V

THRESHOLD,

set to approxi-

mately half the digital positive supply (i.e., DVDD or CLKVDD)
or

THRESHOLD

= DVDD/2 (

20%)

The internal digital circuitry of the AD9772 is capable of operating
over a digital supply range of 2.7 V to 3.6 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V

OH(MAX)

. Although a DVDD of 3.3 V will typically

ensure proper compatibility with most TTL logic families, a
series 200

resistors are recommended between the TTL logic

driver and digital inputs to limit the peak current through the
ESD protection diodes if V

OH(MAX)

exceeds DVDD by more

than 300 mV. Figure 36 shows the equivalent digital input cir-
cuit for the data and control inputs.

DIGITAL

INPUT

DVDD

Figure 36. Equivalent Digital Input

The AD9772 features a flexible differential clock input operat-
ing from separate supplies (i.e., CLKVDD, CLKCOM) to
achieve optimum jitter performance. The two clock inputs,
CLK+ and CLK, can be driven from a single-ended or
differential clock source. For single-ended operation, CLK+
should be driven by a single-ended logic source while CLK
should be set to the logic source's threshold voltage via a resistor
divider/capacitor network referenced to CLKVDD as shown in
Figure 37. For differential operation, both CLK+ and CLK
should be biased to CLKVDD/2 via a resistor divider network
as shown in Figure 38. An RF transformer as shown in Figure 3
can also be used to convert a single-ended clock input to a dif-
ferential clock input.

SERIES

THRESHHOLD

AD9772

CLK+

CLKVDD

CLK

CLKCOM

0.1 F

Figure 37. Single-Ended Clock Interface

AD9772

CLK+

CLKVDD

CLK

CLKCOM

0.1 F

ECL/PECL

Figure 38. Differential Clock Interface

The quality of the clock and data input signals are important in
achieving the optimum performance. The external clock driver
circuitry should provide the AD9772 with a low jitter clock
input meeting the min/max logic levels while providing fast
edges. Although fast clock edges help minimize any jitter that
will manifest itself as phase noise on a reconstructed waveform,
the high gain-bandwidth product of the AD9772's differential
comparator can tolerate sine wave inputs as low as 0.5 V p-p,
with minimal degradation in its output noise floor.

Digital signal paths should be kept short and run lengths matched
to avoid propagation delay mismatch. The insertion of a low
value resistor network (i.e., 50

to 200

) between the AD9772

digital inputs and driver outputs may be helpful in reducing any
overshooting and ringing at the digital inputs that contribute to
data feedthrough.

SLEEP MODE OPERATION

The AD9772 has a SLEEP function that turns off the output
current and reduces the analog supply current to less than
6 mA over the specified supply range of 2.7 V to 3.6 V. This
mode can be activated by applying a Logic Level "1" to the
SLEEP pin. The AD9772 takes less than 50 ns to power down
and approximately 15

s to power back up.

POWER DISSIPATION

The power dissipation, P

, of the AD9772 is dependent on

several factors, including:

1. AVDD, PLLVDD, CLKVDD and DVDD, the power supply

voltages

2. I

OUTFS

, the full-scale current output

3. f

DATA

, the update rate

4. the reconstructed digital input waveform.

The power dissipation is directly proportional to the analog
supply current, I

AVDD

, and the digital supply current, I

DVDD

AVDD

is directly proportional to I

OUTFS,

and is insensitive to

DATA

Conversely, I

DVDD

is dependent on both the digital input wave-

form and f

DATA

. Figure 39 shows I

DVDD

as a function of full-

scale sine wave output ratios (f

OUT

DATA

) for various update

rates with DVDD = 3 V. The supply current from CLKVDD
and PLLVDD is relatively insensitive to the digital input wave-
form, but shown directly proportional to the update rate as
shown in Figure 40.

REV. 0

AD9772

RATIO f

OUT

DATA

120

0.45

0.05

DVDD

 mA

0.1

0.15

0.2

0.25

0.3

0.35

0.4

100

DATA

= 25MSPS

DATA

= 65MSPS

DATA

= 150MSPS

DATA

= 125MSPS

DATA

= 100MSPS

DATA

= 50MSPS

Figure 39. I

DVDD

vs. Ratio @ DVDD = 3 V

DATA

 MSPS

160

I mA

100

120

140

CLKVDD

PLLVDD

Figure 40. I

PLLVDD

and I

CLKVDD

vs. f

DATA

APPLYING THE AD9772

OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configura-
tions for the AD9772. Unless otherwise noted, it is assumed
that I

OUTFS

is set to a nominal 20 mA for optimum performance.

For applications requiring the optimum dynamic performance, a
differential output configuration is highly recommended. A
differential output configuration may consist of either an RF
transformer or a differential op amp configuration. The trans-
former configuration provides the optimum high frequency
performance and is recommended for any application allowing
for ac coupling. The differential op amp configuration is suitable
for applications requiring dc coupling, a bipolar output, signal
gain and/or level shifting.

A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, R

LOAD

, referred to ACOM. This configura-

tion may be more suitable for a single-supply system requiring a
dc-coupled, ground-referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus convert-
ing IOUTA or IOUTB into a negative unipolar voltage. This
configuration provides the best dc linearity since IOUTA or
IOUTB is maintained at a virtual ground.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to-
single-ended signal conversion as shown in Figure 41. A
differentially-coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer's passband. An RF transformer such
as the Mini-Circuits T1-1T provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and noise
over a wide frequency range. It also provides electrical isolation
and the ability to deliver twice the power to the load. Trans-
formers with different impedance ratios may also be used for
impedance matching purposes. Note that the transformer
provides ac coupling only and its linearity performance degrades
at the low end of its frequency range due to core saturation.

OPTIONAL
R

DIFF

LOAD

MINI-CIRCUITS

T1-1T

AD9772

IOUTA

IOUTB

Figure 41. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., V

OUTA

and V

OUTB

)

swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9772. A
differential resistor, R

DIFF

, may be inserted in applications in

which the output of the transformer is connected to the load,
R

LOAD

, via a passive reconstruction filter or cable. R

DIFF

is deter-

mined by the transformer's impedance ratio and provides the
proper source termination that results in a low VSWR (Voltage
Standing Wave Ratio). Note that approximately half the signal
power will be dissipated across R

DIFF

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-single-
ended conversion as shown in Figure 42. The AD9772 is con-
figured with two equal load resistors, R

LOAD

, of 25

. The

differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter.
The addition of this capacitor also enhances the op amp's dis-
tortion performance by preventing the DAC's high slewing
output from overloading the op amp's input.

AD9772

IOUTA

IOUTB

AD8055

OPT

225

500

Figure 42. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differ-
ential op amp circuit using the AD8055 is configured to provide

REV. 0

AD9772

some additional signal gain. The op amp must operate from a
dual supply since its output is approximately

1.0 V. A high

speed amplifier, capable of preserving the differential perform-
ance of the AD9772 while meeting other system level objectives
(i.e., cost, power), should be selected. The op amp's differential
gain, its gain setting resistor values and full-scale output swing
capabilities should all be considered when optimizing this circuit.

The differential circuit shown in Figure 43 provides the neces-
sary level shifting required in a single supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9772 and the op amp, is also used to level-shift the differ-
ential output of the AD9772 to midsupply (i.e., AVDD/2). The
AD8057 is a suitable op amp for this application.

AD9772

IOUTA

IOUTB

AD8057

OPT

225

500

AVDD

Figure 43. Single Supply DC Differential Coupled Circuit

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 44 shows the AD9772 configured to provide a unipolar
output range of approximately 0 V to +0.5 V for a doubly termi-
nated 50

cable since the nominal full-scale current, I

OUTFS

, of

20 mA flows through the equivalent R

LOAD

of 25

. In this case,

LOAD

represents the equivalent load resistance seen by IOUTA.

The unused output (IOUTB) can be connected to ACOM
directly. Different values of I

OUTFS

and R

LOAD

can be selected as

long as the positive compliance range is adhered to. One addi-
tional consideration in this mode is the integral nonlinearity
(INL) as discussed in the Analog Output section of this data
sheet. For optimum INL performance, the single-ended, buff-
ered voltage output configuration is suggested.

AD9772

IOUTA

IOUTB

OUTA

= 0V TO +0.5V

OUTFS

= 20mA

Figure 44. 0 V to +0.5 V Unbuffered Voltage Output

SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
CONFIGURATION

Figure 45 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9772
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, thus minimizing the nonlinear output impedance effect
on the DAC's INL performance as discussed in the Analog
Output section. Although this single-ended configuration typi-
cally provides the best dc linearity performance, its ac distortion
performance at higher DAC update rates is often limited by
U1's slewing capabilities. U1 provides a negative unipolar output
voltage and its full-scale output voltage is simply the product of
R

and I

OUTFS

. The full-scale output should be set within U1's

voltage output swing capabilities by scaling I

OUTFS

and/or R

An improvement in ac distortion performance may result with a

reduced I

OUTFS

since the signal current U1 will be required to

sink will be subsequently reduced.

AD9772

IOUTA

IOUTB

200

OPT

OUTFS

= 10mA

OUT

= I

OUTFS

Figure 45. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS

The AD9772 contains the four following power supply inputs:
AVDD, DVDD, CLKVDD and PLLVDD. The AD9772 is
specified to operate over a 2.7 V to 3.6 V supply range, thus
accommodating +3.0 V and/or 3.3 V power supplies with up to

10% regulation. However, the following two conditions must

be adhered to when selecting power supply sources for AVDD,
DVDD, CLKVDD, and PLLVDD:

1. PLLVDD = CLKVDD when PLL Clock Multiplier enabled.

(Otherwise PLLVDD = PLLCOM)

2. DVDD = CLKVDD

0.30 V

To meet the first condition, PLLVDD must be driven by the
same power source as CLKVDD with each supply input inde-
pendently decoupled with a 0.1

F capacitor to its respective

grounds. To meet the second condition, CLKVDD can share
the power supply source as DVDD, using the decoupling net-
work shown in Figure 46 to isolate digital noise from the sensi-
tive CLKVDD (and PLLVDD) supply. Alternatively, separate
precision voltage regulators can be used to ensure that condition
two is met.

In systems seeking to simultaneously achieve high speed and
high performance, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection,
placement and routing and supply bypassing and grounding.
Figures 5461 illustrate the recommended printed circuit board
ground, power and signal plane layouts that are implemented on
the AD9772 evaluation board.

Proper grounding and decoupling should be a primary objective
in any high speed, high resolution system. The AD9772 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a
system. AVDD, CLKVDD, and PLLVDD must be powered from
a clean analog supply and decoupled to their respective analog
common (i.e., ACOM, CLKCOM and PLLCOM) as close to
the chip as physically possible. Similarly, DVDD, the digital
supply, should be decoupled to DCOM.

For those applications requiring a single +3 V or +3.3 V supply
for both the analog, digital supply and Phase Lock Loop supply,
a clean AVDD and/or CLKVDD may be generated using the
circuit shown in Figure 46. The circuit consists of a differential
LC filter with separate power supply and return lines. Lower
noise can be attained using low ESR-type electrolytic and tanta-
lum capacitors.

REV. 0

AD9772

100 F
ELECTROLYTIC

10 F22 F
TANTALUM

0.1 F
CERAMIC

AVDD

ACOM

TTL/CMOS

LOGIC

CIRCUITS

+3.0V OR +3.3V

POWER SUPPLY

FERRITE

BEADS

Figure 46. Differential LC Filter for +3 V or 3.3 V
Applications

Maintaining low noise on power supplies and ground is critical
to obtain optimum results from the AD9772. If properly
implemented, ground planes can perform a host of functions on
high speed circuit boards: bypassing, shielding current trans-
port, etc. In mixed signal design, the analog and digital portions
of the board should be distinct from each other, with the analog
ground plane confined to the areas covering the analog signal
traces, and the digital ground plane confined to areas covering
the digital interconnects.

All analog ground pins of the DAC, reference and other analog
components should be tied directly to the analog ground plane.
The two ground planes should be connected by a path 1/8 to
1/4 inch wide underneath or within 1/2 inch of the DAC to
maintain optimum performance. Care should be taken to ensure
that the ground plane is uninterrupted over crucial signal paths.
On the digital side, this includes the digital input lines running
to the DAC. On the analog side, this includes the DAC output
signal, reference signal and the supply feeders.

The use of wide runs or planes in the routing of power lines is
also recommended. This serves the dual role of providing a low
series impedance power supply to the part, as well as providing
some "free" capacitive decoupling to the appropriate ground
plane. It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous volt-
age drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the pack-
age as possible in order to minimize the sharing of conduction
paths between different currents. When runs exceed an inch in
length, strip line techniques with proper termination resistors
should be considered. The necessity and value of this resistor
will be dependent upon the logic family used.

For a more detailed discussion of the implementation and con-
struction of high speed, mixed signal printed circuit boards,
refer to Analog Devices' application notes AN-280 and AN-333.

APPLICATIONS

MULTICARRIER

The AD9772's wide dynamic range performance makes it well
suited for next generation base station applications in which it
reconstructs multiple modulated carriers over a designated
frequency band. Cellular multicarrier and multimode radios are
often referred to as software radios since the carrier tuning and
modulation scheme is software programmable and performed
digitally. The AD9772 is the recommended TxDAC in Analog
Device's Softcell chipset which comprises the AD6622, Quadra-
ture Digital Upconverter IC, along with its companion Rx Digi-
tal Downconverter IC, the AD6624, and 14-bit, 65 MSPS
ADC, the AD6644. Figure 47 shows a generic software radio
Tx signal chain based on the AD9772/AD6622.

OTHER AD6622's FOR
INCREASED CHANNEL
CAPACITY

AD9772

PLLLOCK

CLK

SUMMATION

SPORT

RCF

CIC

FILTER

NCO

QAM

SPORT

RCF

CIC

FILTER

NCO

QAM

SPORT

RCF

CIC

FILTER

NCO

QAM

SPORT

RCF

CIC

FILTER

NCO

QAM

CLK

JTAG

PORT

AD6622

Figure 47. Generic Multicarrier Signal Chain Using the
AD6622 and AD9772

Figure 48 shows a spectral plot of the AD9772 operating at
64.54 MSPS reconstructing eight IS-136 modulated carriers
spread over a 25 MHz band. For this particular test scenario,
the AD9772 exhibited 74 dBc SFDR performance along with a
carrier-to-noise ratio (CNR) of 73 dB. Figure 49 shows a spec-
tral plot of the AD9772 operating at 52 MSPS reconstructing
four equal GSM carriers spread over a 15 MHz band. The
SFDR and CNR (in 100 kHz BW) measured to be 76 dBc and
83.4 dB respectively along with a channel power of 13.5 dBFS.
Note, the test vectors were generated using Rohde & Schwarz's
WinIQSIM software.

FREQUENCY MHz

10

20

30

40

50

60

70

80

90

POWER dBm

100

Figure 48. Spectral Plot of AD9772 Reconstructing
Eight IS-136 Modulated Carriers @ f

DATA

= 64.54 MSPS,

PLLVDD = 0

REV. 0

AD9772

FREQUENCY MHz

POWER dBm

10

20

30

40

50

60

70

80

90

100

Figure 49. Spectral Plot of AD9772 Reconstructing Four
GSM Modulated Carriers @ f

DATA

= 52 MSPS, PLLVDD = 0

Although the above IS-136 and GSM spectral plots are repre-
sentative of the AD9772's performance for a particular set of
test conditions, the following recommendations are offered to
maximize the performance and system integration of the AD9772
into multicarrier applications:

1. To achieve the highest possible CNR, the PLL Clock Multi-

plier should be disabled (i.e., PLLVDD to PLLCOM) and
the AD9772's clock input driven with a low jitter/phase noise
clock source at twice the input data rate. In this case, the
divide-by-two clock appearing at PLLLOCK should serve as
the master clock for the digital upconverter IC(s) such as the
AD6622. PLLLOCK should be limited to a fanout of one.

2. The AD9772 achieves its optimum noise and distortion

performance when configured for baseband operation along
with a differential output and a full-scale current, I

OUTFS

, set

to approximately 20 mA.

3. Although the 2

interpolation filters frequency roll-off pro-

vides a maximum reconstruction bandwidth of 0.422

DATA,

the optimum adjacent image rejection (due to the interpola-
tion process) is achieved (i.e., > 73 dBc) if the maximum
channel assignment is kept below 0.400

DATA.

4. To simplify the subsequent IF stages filter requirements (i.e.,

mixer image and LO rejection), it is often advantageous to
offset the frequency band from dc to relax the transition
band requirements of the IF filter.

5. Oversampling the frequency band often results in improved

SFDR and CNR performance. This implies that the data
input rate to the AD9772 is greater than f

PASSBAND

/0.4 where

PASSBAND

is the maximum bandwidth in which the AD9772

will be required to reconstruct and place carriers. The im-
proved noise performance results in a reduction in the
TxDAC's noise spectral density due to the added process
gain realized with oversampling. Also, higher oversampling
ratios provide greater flexibility in the frequency planning.

BASEBAND SINGLE-CARRIER

The AD9772 is also well suited for wideband single-carrier
applications such as WCDMA and multilevel QAM whose
modulation scheme requires wide dynamic range from the re-
construction DAC to achieve the out-of-band spectral mask as
well as the in-band CNR performance. Many of these applica-
tions strategically place the carrier frequency at one quarter of
the DAC's input data rate (i.e., f

DATA

/4) to simplify the digital

modulator design. Since this constitutes the first fixed IF fre-
quency, the frequency tuning is accomplished at a later IF stage.
To enhance the modulation accuracy as well as reduce the shape
factor of the second IF SAW filter, many applications will often
specify the passband of the IF SAW filter be greater than the
channel bandwidth. The trade-off is that the TxDAC must now
meet the particular application's spectral mask requirements
within the extended passband of the 2nd IF, which may include
two or more adjacent channels.

Figure 50 shows a spectral plot of the AD9772 reconstructing a
test vector similar to those encountered in WCDMA applica-
tions with the following exception. WCDMA applications pre-
scribe a root raised cosine filter with an alpha = 0.22, which
limits the theoretical ACPR of the TxDAC to about 70 dB. This
particular test vector represents white noise that has been band-
limited by a "brickwall" bandpass filter with the same passband
such that its maximum ACPR performance is theoretically
83 dB and its peak-to-rms ratio is 12.4 dB. As Figure 50 re-
veals, the AD9772 is capable of approximately 78 dB ACPR
performance when one accounts for the additive noise/distortion
contributed by the FSEA30 spectrum analyzer.

FREQUENCY MHz

8.1922

POWER dBm

20

40

60

80

100

120

10.2402 12.2882 14.3362 16.3842 18.4322 20.4802 22.5282 24.5762

ACPR LOW =

78.3dB

CH PWR =

12.25dBm

ACPR UP =

77.7dB

Figure 50. AD9772 Achieves 78 dB ACPR Performance
Reconstructing a "WCDMA-Like" Test Vector with
f

DATA

= 65.536 MSPS and PLLVDD = 0

REV. 0

AD9772

DIRECT IF

As discussed in the Digital Modes of Operation section, the
AD9772 can be configured to transform digital data represent-
ing baseband signals into IF signals appearing at odd multiples
of the input data rate (i.e., N

DATA

where N = 1, 3, . . .). This

is accomplished by configuring the MOD1 and MOD0 digital
inputs HIGH. Note, the maximum DAC update rate of 400 MSPS
limits the data input rate in this mode to 100 MSPS when the
"zero-stuffing operation" is enabled (i.e., MOD1 High). Appli-
cations requiring higher IFs (i.e., 140 MHz) using higher data
rates should disable the "zeros-stuffing" operation. Also, to
minimize the effects of the PLL Clock Multipliers phase noise
as shown in Figure 27, an external low jitter/phase noise clock
source equal to 4

DATA

is recommended.

Figure 51 shows the actual output spectrum of the AD9772
reconstructing a 16-QAM test vector with a symbol rate of
5 MSPS. The particular test vector was centered at f

DATA

/4 with

DATA

= 100 MSPS, and f

DAC

= 400 MHz. For many applica-

tions, the pair of images appearing around f

DATA

will be more

attractive since they have the flattest passband and highest signal
power. Higher images can also be used with the realization that
these images will have reduced passband flatness, dynamic
range, and signal power, thus reducing the CNR and ACP per-
formance. Figure 52 shows a dual tone SFDR amplitude sweep
at the various IF images with f

DATA

= 100 MSPS and f

DAC

400 MHz and the two tones centered around f

DATA

/4. Note,

since an IF filter is assumed to precede the AD9772, the SFDR
was measured over a 25 MHz window around the images occur-
ring at 75 MHz, 125 MHz, 275 MHz and 325 MHz.

FREQUENCY MHz

20

40

60

80

100

120

100

150

200

250

300

350

400

Figure 51. Spectral Plot of 16-QAM Signal in Direct IF
Mode at f

DATA

= 100 MSPS

OUT

 dBFS

15

12

SFDR (IN 25MHz WINDOW) dBFS

IF @ 275MHz

IF @ 75MHz

IF @ 125MHz

IF @ 325MHz

Figure 52. Dual Tone "Windowed" SFDR vs. A

OUT

DATA

= 100 MSPS

Regardless of what image is selected for a given application, the
adjacent images must be sufficiently filtered. In most cases, a
SAW filter providing differential inputs represents the opti-
mum device for this purpose. For single-ended SAW filters, a
balanced-to-unbalanced RF transformer is recommended. The
AD9772's high output impedance provides a certain amount of
flexibility in selecting the optimum resistive load, R

LOAD

, as well

as any matching network.

For many applications, the data update rate to the DAC (i.e.,
f

DATA

) must be some fixed integer multiple of some system

reference clock (i.e., GSM 13 MHz). Furthermore, these
applications prefer to use standard IF frequencies which offer a
large selection of SAW filter choices of varying passbands (i.e.,
70 MHz). These applications may still benefit from the AD9772's
direct IF mode capabilities when used in conjunction with a
digital upconverter such as the AD6622. Since the AD6622 can
digitally synthesize and tune up to four modulated carriers, it is
possible to judiciously tune these carriers in a region which may
fall within an IF filter's passband upon reconstruction by the
AD9772. Figure 53 shows an example in which four carriers
were tuned around 18 MHz with a digital upconverter operating
at 52 MSPS such that when reconstructed by the AD9772 in
the IF MODE, these carriers fall around a 70 MHz IF.

FREQUENCY MHz

10

20

30

40

50

60

67.5

72.5

70

80

90

POWER dBm

100

Figure 53. Spectral Plot of Four Carriers at 70 MHz IF with
f

DATA

= 52 MSPS, PLLVDD = 0

REV. 0

AD9772

AD9772 EVALUATION BOARD

The AD9772-EB is an evaluation board for the AD9772 TxDAC.
Careful attention to layout and circuit design, combined with
prototyping area, allows the user to easily and effectively evalu-
ate the AD9772 in different modes of operation.

Referring to Figures 54 and 55, the AD9772's performance can
be evaluated differentially or single-ended using a transformer,
differential amplifier, or directly coupled output. To evaluate
the output differentially using the transformer, remove jumpers
JP12 and JP13 and monitor the output at J6 (IOUT). To evalu-
ate the output differentially, remove the transformer (T2) and
install jumpers JP12 and JP13. The output of the amplifier can
be evaluated at J13 (AMPOUT). To evaluate the AD9772
single-ended and directly coupled, remove the transformer and
jumpers (JP12 and JP13) and install resistors R16 or R17 with
0

The digital data to the AD9772 comes across a ribbon cable
which interfaces to a 40-pin IDC connector. Proper termina-
tion or voltage scaling can be accomplished by installing RN2
and/or RN3 SIP resistor networks. The 22

DIP resistor net-

work, RN1, must be installed and helps reduce the digital data
edge rates. A single-ended CLOCK input can be supplied via
the ribbon cable by installing JP8 or more preferably via the
SMA connector, J3 (CLOCK). If the CLOCK is supplied by J3,
the AD9772 can be configured for a differential clock interface
by installing jumpers JP1 and configuring JP2, JP3, and JP9 for
the DF position. To configure the AD9772 clock input for a
single-ended clock interface, remove JP1 and configure JP2, JP3
and JP9 for the SE position.

The AD9772's PLL clock multiplier can be disabled by config-
uring jumper JP5 for the L position. In this case, the user must
supply a clock input at twice (2

)the data rate via J3 (CLOCK).

The 1

clock is made available on SMA connector, J1

(PLLLOCK) and should be used to trigger a pattern generator
directly or via a programmable pulse generator. Note, PLLLOCK
is capable of providing a 0 V to 0.85 V output into a 50

load.

To enable the PLL clock multiplier, JP5 must be configured for
the H position. In this case, the clock may be supplied via the
ribbon cable (i.e., JP8 installed) or J3 (CLOCK). The divide-
by-N ratio can be set by configuring JP6 (DIV0) and JP7 (DIV1).

The AD9772 can be configured for Baseband or Direct IF Mode
operation by configuring jumpers JP11 (MOD0) and JP10
(MOD1). For baseband operation, JP10 and JP11 should be
configured in the L position. For direct IF operation, JP10 and
JP11 should be configured in the H position. For direct IF
operation without "zero-stuffing," JP11 should be configured in
the H position while JP10 should be configured in the low position.

The AD9772's voltage reference can be enabled or disabled via
JP4 (EXT REF IN). To enable the reference, configure JP in
the INT position. A voltage of approximately 1.2 V will appear
at the TP6 (REFIO) test point. To disable the internal refer-
ence, configure JP4 in the EXT position and drive TP6 with an
external voltage reference. Lastly, the AD9772 can be placed in
the SLEEP mode by driving the TP11 test point with logic level
HIGH input signal.

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