REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD9856

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

CMOS 200 MHz

Quadrature Digital Upconverter

FUNCTIONAL BLOCK DIAGRAM

DDS AND CONTROL FUNCTIONS

12-BIT

DAC

COSINE

SINE

COMPLEX

DATA IN

REFERENCE

CLOCK IN

TxENABLE

(I/Q SYNC)

PROFILE

SELECT

12

PROFILE

SELECT

34

MASTER

RESET

SPI INTERFACE
TO AD8320/AD8321
PROGRAMMABLE
CABLE DRIVER
AMPLIFIER

DAC
R

SET

DC-80 MHz
OUTPUT

BIDIRECTIONAL SPI CONTROL INTERFACE:

32-BIT FREQUENCY TUNING WORD
FREQUENCY UPDATE
INTERPOLATION FILTER RATE
REFERENCE CLOCK MULTIPLIER RATE
SPECTRAL PHASE INVERSION ENABLE
CABLE DRIVER AMPLIFIER CONTROL

DEMULTIPLEXER AND

SERIAL-TO-PARALLEL

CONVERTER

INV

SINC

AD9856

4 8

SELECTABLE

INTERPOLATING

HALFBANDS

4 8

SELECTABLE

INTERPOLATING

HALFBANDS

4 20 PROG.

CLOCK

MULTIPLIER

2 TO 63

SELECTABLE

INTERPOLATOR

2 TO 63

SELECTABLE

INTERPOLATOR

FEATURES
Universal Low Cost Modulator Solution for

Communications Applications

DC to 80 MHz Output Bandwidth
Integrated 12-Bit D/A Converter
Programmable Sample Rate Interpolation Filter
Programmable Reference Clock Multiplier
Internal SIN(x)/x Compensation Filter
>52 dB SFDR @ 40 MHz A

OUT

>48 dB SFDR @ 70 MHz A

OUT

>80 dB Narrowband SFDR @ 70 MHz A

OUT

+3 V Single Supply Operation
Space-Saving Surface-Mount Packaging
Bidirectional Control Bus Interface
Supports Burst and Continuous Tx Modes
Single Tone Mode for Frequency Synthesis Applications
Four Programmable, Pin-Selectable Modulator Profiles
Direct Interface to AD8320/AD8321 PGA Cable Driver

GENERAL DESCRIPTION

The AD9856 integrates a high speed direct-digital synthesizer
(DDS), a high performance, high speed 12-bit digital-to-analog
converter (DAC), clock multiplier circuitry, digital filters and
other DSP functions onto a single chip, to form a complete
quadrature digital upconverter device. The AD9856 is intended
to function as a universal I/Q modulator and agile upconverter
for communications applications, where cost, size, power dissi-
pation and dynamic performance are critical attributes.

The AD9856 is available in a space-saving surface mount pack-
age and specified to operate over the extended industrial tem-
perature range of 40

C to +85

APPLICATIONS
HFC Data, Telephony and Video Modems
Wireless and Satellite Communications
Cellular Basestations

REV. B

AD9856SPECIFICATIONS

= +3 V 5%, R

SET

= 3.9 k

, External reference clock frequency = 10 MHz

with REFCLK Multiplier enabled at 20 ).

Test

AD9856

Parameter

Temp

Level

Min

Typ

Max

Units

REF CLOCK INPUT CHARACTERISTICS

Frequency Range

REFCLK Multiplier Disabled

Full

200

MHz

REFCLK Multiplier Enabled at 4

Full

MHz

REFCLK Multiplier Enabled at 20

Full

MHz

Duty Cycle

+25

Input Capacitance

+25

Input Impedance

+25

100

DAC OUTPUT CHARACTERISTICS

Resolution

Bits

Full-Scale Output Current

Gain Error

+25

+10

%FS

Output Offset

+25

Differential Nonlinearity

+25

0.5

LSB

Integral Nonlinearity

+25

LSB

Output Capacitance

+25

Phase Noise @ 1 kHz Offset, 40 MHz A

OUT

REFCLK Multiplier Enabled at 20

+25

dBc/Hz

REFCLK Multiplier at 4

+25

100

dBc/Hz

REFCLK Multiplier Disabled

+25

110

dBc/Hz

Voltage Compliance Range

+25

0.5

1.5

Wideband SFDR:

1 MHz Analog Out

+25

dBc

20 MHz Analog Out

+25

dBc

42 MHz Analog Out

+25

dBc

65 MHz Analog Out

+25

dBc

80 MHz Analog Out

+25

dBc

Narrowband SFDR: (

100 kHz Window)

70 MHz Analog Out

+25

dBc

MODULATOR CHARACTERISTICS

Adjacent Channel Power (CH Power = 6.98 dBm)

+25

dBm

Error Vector Magnitude

+25

I/Q Offset

+25

Inband Spurious Emissions

+25

dBc

Pass Band Amplitude Ripple (DC to 80 MHz)

+25

0.3

TIMING CHARACTERISTICS

Serial Control Bus

Maximum Frequency

Full

MHz

Minimum Clock Pulsewidth High (t

PWH

)

Full

Minimum Clock Pulsewidth Low (t

PWL

)

Full

Maximum Clock Rise/Fall Time

Full

Minimum Data Setup Time (t

)

Full

Minimum Data Hold Time (t

)

Full

Maximum Data Valid Time (t

)

Full

Wake-Up Time

Full

Minimum RESET Pulsewidth High (t

)

Full

REFCLK
Cycles

CMOS LOGIC INPUTS

Logic "1" Voltage

+25

+2.6

Logic "0" Voltage

+25

+0.4

Logic "1" Current

+25

Logic "0" Current

+25

Input Capacitance

+25

REV. B

AD9856

Test

AD9856

Parameter

Temp

Level

Min

Typ

Max

Units

CMOS LOGIC OUTPUTS (1 mA LOAD)

Logic "1" Voltage

+25

2.7

Logic "0" Voltage

+25

0.4

POWER SUPPLY

Current

Full Operating Conditions

+25

530

Burst Operation (25%)

+25

450

Single Tone Mode

+25

495

160 MHz Clock

+25

445

120 MHz Clock

+25

345

Power-Down Mode

+25

NOTES

For 200 MHz operation in Modulation Mode at +85

C operating temperature, V

must be +3 V min.

Assuming 1.3 k

and 0.01

F loop filter components.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

Maximum Junction Temperature . . . . . . . . . . . . . . . .+165

Storage Temperature . . . . . . . . . . . . . . . . . . 65

C to +150

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V

Operating Temperature . . . . . . . . . . . . . . . . . 40

C to +85

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . 0.7 V to +V

Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . +300

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 38

C/W

*Absolute maximum ratings are limiting values, to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option

AD9856AST

C to +85

Thin Quad Flatpack

ST-48

AD9856/PCB

+25

Evaluation Board

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9856 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

EXPLANATION OF TEST LEVELS

Test Level

100% Production Tested.

III

Sample Tested Only.

Parameter is guaranteed by design and characterization
testing.

Parameter is a typical value only.

Devices are 100% production tested at +25

C and

guaranteed by design and characterization testing for
industrial operating temperature range.

AD9856

REV. B

Pin #

Pin Name

Pin Function

TxENABLE

Input Pulse that Synchronizes
the Data Stream

D11

Input Data (Most Significant Bit)

D10

Input Data

4, 10,
21, 44

DVDD

Digital Supply Voltage

5, 11,
20, 43

DGND

Digital Ground

D9D6

Input Data

1216

D5D1

Input Data

Input Data (Least Significant
Bit)

18, 19,
22

No Internal Connection

23, 28,
31

AGND

Analog Ground

BG REF BYPASS

No External Connection*

DAC R

SET

Resistor Connection

DAC REF BYPASS

No External Connection*

AVDD

Analog Supply Voltage

Pin #

Pin Name

Pin Function

OUTB

Complementary Analog
Current Output of the DAC

OUT

True Analog Current Output
of DAC

PLL GND

PLL Ground

PLL FILTER

PLL Loop Filter Connection

PLL SUPPLY

PLL Voltage Supply

CA ENABLE

Cable Driver Amp Enable

CA DATA

Cable Driver Amp Data

CA CLK

Cable Driver Amp Clock

Chip Select

SDO

Serial Data Output

SDIO

Serial Port I/O

SCLK

Serial Port Clock

SYNC I/O

Performs I/O Synchronization

PS0

Profile Select 0

PS1

Profile Select 1

REFCLK

Reference Clock Input

RESET

Master Reset

PIN FUNCTION DESCRIPTIONS

PIN CONFIGURATION

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44

39 38

43 42 41 40

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

AD9856

CA DATA

CA ENABLE

PLL SUPPLY

PLL FILTER
PLL GND

AGND

OUT

TxENABLE

D11

D10

DVDD

DGND

NC = NO CONNECT

DVDD

DGND

OUTB

AGND

AVDD

DAC REF BYPASS

BG REF

BYPASS

DAC R

SET

DVDD

DGND

AGND

SYNC I/O

REFCLK

SCLK

RESET

PS0

DVDD

DGND

CA CLK

PS1

SDO

SDIO

*In most cases optimal performance is achieved with no external connection. For extremely noisy environments BG REF BYPASS can be bypassed with up to a

0.1

F capacitor to AGND (Pin 23). DAC REF BYPASS can be bypassed with up to a 0.1

F capacitor to AVDD (Pin 27).

AD9856

REV. B

FUNCTIONAL BLOCK AND MODE DESCRIPTION

Operating Modes

1. Complex quadrature modulator mode.
2. Single tone output mode.

Input Data Format

Programmable: 12-bit, 6-bit, or 3-bit input formats. Data input to the AD9856 is
12-bit, twos complement. Complex I/Q symbol component data is required to be at
least 2

oversampled, depending upon configuration.

Input Sample Rate

Up to 50 Msamples/s @ 200 MHz SYSCLK rate.

Input Reference Clock Frequency

For DC-80 MHz A

OUT

operation (200 MHz SYSCLK rate):

w/REFCLK Multiplier enabled: 10 MHz50 MHz, programmable via control bus
w/REFCLK Multiplier disabled: 200 MHz.
Note: For optimum data synchronization, the AD9856 Reference Clock, and the
input data clock, should be derived from the same clock source.

Internal Reference Clock Multiplier

Programmable in integer steps over the range of 4

. Can be disabled (effective

REFCLK Multiplier = 1) via control bus. Output of REFCLK Multiplier = SYSCLK
rate, which is the internal clock rate applied to the DDS and DAC function.

Profile Select

Four pin-selectable, preprogrammed formats. Available for modulation and single
tone operating modes.

Interpolating Range

Fixed 4

, selectable 2

and selectable 2

range

Half-Band Filters

Interpolating filters that provide upsampling and reduce the effects of the CIC
passband roll-off characteristics.

TxENABLE FunctionBurst Mode

When Burst Mode is enabled via the control bus, the rising edge of the applied
TxENABLE pulse should be coincident with, and frame, the input data packet. This
establishes data sampling synchronization.

TxENABLE FunctionContinuous Mode

When continuous mode is enabled via the control bus, the TxENABLE pin becomes
an I/Q control line. A Logic "1" on TxENABLE indicates I data is being presented
to the AD9856. A Logic "0" on TxENABLE indicates Q data is being presented to the
AD9856. Each rising edge of TxENABLE resynchronizes the AD9856 input sam-
pling capability.

Inverse SINC Filter

Precompensates for SIN(x)/x roll-off of DAC; user bypassable.

I/Q Channel Invert

Cos(

t) + Q

Sin(

t)] or [I

Cos(

t) Q

Sin(

t)] (default), configurable via

control bus, per profile.

Full Sleep Mode

Power dissipation reduced to less than 6 mW when Full Sleep Mode active, program-
mable via control bus.

AD9856

REV. B

Typical Modulated Output Spectral Plots

START 0Hz

5MHz/

STOP 50MHz

REF LVL
25dBm

dBm

1AP

16

24

32

40

48

56

64

72

80

RBW

10kHz

RF ATT 10dB

VBW

1kHz

SWT

12.5s Unit

dBm

Figure 1. QPSK at 42 MHz and 2.56 MS/s; 10.24 MHz
External Clock with REFCLK Multiplier = 12, CIC = 3,
HB3 On, 2

Data

START 0Hz

4MHz/

STOP 40MHz

REF LVL
30dBm

dBm

1AP

16

24

32

40

48

56

64

72

80

RBW 10kHz

ATT

10dB

VBW 1kHz
SWT

10s

UNIT

dBm

Figure 2. 64-QAM at 28 MHz and 6 MS/s; 36 MHz External
Clock with REFCLK Multiplier = 4, CIC = 2, HB3 Off, 3

Data

START 0Hz

8MHz/

STOP 80MHz

REF LVL
25dBm

dBm

1AP

16

24

32

40

48

56

64

72

80

RBW 10kHz

ATT

10dB

VBW 1kHz
SWT

20s Unit

dBm

Figure 3. 16-QAM at 65 MHz and 2.56 MS/s; 10.24 MHz
External Clock with REFCLK Multiplier = 18, CIC = 9,
HB3 Off, 2

Data

START 0Hz

5MHz/

STOP 50MHz

REF LVL
30dBm

dBm

1AP

16

24

32

40

48

56

64

72

80

RBW

10kHz

RF ATT

10dB

VBW 1kHz
SWT

12.5s

UNIT

dBm

Figure 4. 256-QAM at 38 MHz and 6 MS/s; 48 MHz External
Clock with REFCLK Multiplier = 4, CIC = 2, HB3 Off, 4

Data

AD9856

REV. B

Typical Narrowband SFDR Spectral Plots

Typical Phase Noise Spectral Plots

CENTER 70.1MHz

10kHz/

SPAN 100kHz

10

REF LVL
5dBm

dBm

1AP

20

30

40

50

60

70

80

90

100

RBW

100Hz

RF ATT

20dB

VBW 100Hz
SWT

50s

UNIT

Figure 9. 70.1 MHz Narrowband SFDR, 10 MHz External
Clock with REFCLK Multiplier = 20

CENTER 70.1MHz

10kHz/

SPAN 100kHz

12

REF LVL
5dBm

dBm

1AP

24

36

48

60

72

84

96

100

120

RBW

100Hz

RF ATT

20dB

VBW 100Hz
SWT

50s

UNIT

Figure 11. 70.1 MHz Narrowband SFDR, 200 MHz External
Clock with REFCLK Multiplier Disabled

CENTER 40.1MHz 500Hz/ SPAN 5kHz

12

REF LVL
0dBm

dBm

1AP

24

36

48

60

72

84

96

108

120

RBW

30Hz

RF ATT

30dB

VBW 30Hz
SWT

28s

UNIT

FXD

FXD 2.248dBm

Figure 10. 40.1 MHz Output, 10 MHz External Clock with
REFCLK Multiplier = 20

CENTER 40.1MHz

500Hz/ SPAN 5kHz

12

REF LVL
0dBm

dBm

1AP

24

36

48

60

72

84

96

100

120

RBW

30Hz

RF ATT

30dB

VBW 30Hz
SWT

28s

UNIT

FXD

FXD 2.248dBm

Figure 12. 40.1 MHz Output, 200 MHz External Clock with
REFCLK Multiplier Disabled

AD9856

REV. B

Table I. Serial Control Bus Register Layout

Register

AD9856 Register Layout

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Profile

(hex)

SDO

LSB

REFCLK

Reserved

N/A

Active

First

Mult.<4>

Mult.<3>

Mult.<2>

Mult.<1>

Mult.<0>

CIC

Continuous

Full Sleep

Single Tone

Bypass Inverse

Bypass

Input Format

N/A

Gain

Mode

Sinc Filter

REFCLK

Select <1>

Select <0>

Mult.

Frequency Tuning Word <7:0>

Frequency Tuning Word <15:8>

Frequency Tuning Word <23:16>

Frequency Tuning Word <31:24>

Interpolator Interpolator

Interpolator

Spectral

Bypass the

Rate <5>

Rate <4>

Rate <3>

Rate <2>

Rate <1>

Rate <0>

Inversion

Third Half

Band Filter

AD8320/AD8321 Gain Control Bits <7:0>

Frequency Tuning Word <7:0>

Frequency Tuning Word <15:8>

Frequency Tuning Word <23:16>

Frequency Tuning Word <31:24>

Interpolator Interpolator

Interpolator

Spectral

Bypass the

Rate <5>

Rate <4>

Rate <3>

Rate <2>

Rate <1>

Rate <0>

Inversion

Third Half

Band Filter

AD8320/AD8321 Gain Control Bits <7:0>

Frequency Tuning Word <7:0>

Unset

Frequency Tuning Word <15:8>

Unset

Frequency Tuning Word <23:16>

Unset

Frequency Tuning Word <31:24>

Unset

Interpolator Interpolator

Interpolator

Spectral

Bypass the

Unset

Rate <5>

Rate <4>

Rate <3>

Rate <2>

Rate <1>

Rate <0>

Inversion

Third Half

Band Filter

AD8320/AD8321 Gain Control Bits <7:0>

Frequency Tuning Word <7:0>

Unset

Frequency Tuning Word <15:8>

Unset

Frequency Tuning Word <23:16>

Unset

Frequency Tuning Word <31:24>

Unset

Interpolator Interpolator

Interpolator

Spectral

Bypass the

Unset

Rate <5>

Rate <4>

Rate <3>

Rate <2>

Rate <1>

Rate <0>

Inversion

Third Half

Band Filter

AD8320/AD8321 Gain Control Bits <7:0>

AD9856

REV. B

SDO Active--Register Address 00h, Bit 7. Active high indicates
serial port uses dedicated in/out lines. Default low configures
serial port as single line I/O.

LSB First--Register Address 00h, Bit 6. Active high indicates
serial port access is LSB to MSB format. Default low indicates
MSB to LSB format.

REFCLK Multiplier--Register Address 00h, Bits 5, 4, 3, 2, 1 form
the reference clock multiplier. Valid entries range from
420 (decimal). Straight binary to decimal conversion is imple-
mented. For example, to multiply the reference clock by 19 deci-
mal, Program Register Address 00h, Bits 51, as 13h. Default value
is 0A (hex).

RESERVED BIT--Register Address 00h, Bit 0. This bit is
reserved. Always set this bit to Logic 1 when writing to this
register.

CIC GAIN--Register Address 01h, Bit 7. The CIC GAIN bit
multiplies the CIC filter output by 2. See the Cascaded Inte-
grated Comb Filter section of this data sheet for more details.
Default value is 0 (inactive).

CONTINUOUS MODE--Register Address 01h, Bit 6 is the
continuous mode configuration bit. Active high, configures the
AD9856 to accept continuous mode timing on the TxENABLE
input. A low configures the device for burst mode timing. De-
fault value is 0 (burst mode).

FULL SLEEP MODE--Register Address 01h, Bit 5. Active
high full sleep mode bit. When activated, the AD9856 enters a
full shutdown mode, consuming less than 2 mA, after completing
a shutdown sequence. Default value is 0 (awake).

SINGLE TONE MODE--Register Address 01h, Bit 4. Active
high configures the AD9856 for single tone applications. The
AD9856 will supply a single frequency output as determined by
the frequency tuning word (FTW) selected by the active profile.
In this mode, the 12 input data pins are ignored but should be
tied high or low. Default value is 0 (inactive).

BYPASS INVERSE SINC FILTER--Register Address 01h,
Bit 3. Active high, configures the AD9856 to bypass the SIN(x)/
x compensation filter. Defaults value is 0 (Inverse SINC Filter
Enabled).

BYPASS REFCLK Multiplier--Register Address 01h, Bit 2.
Active high, configures the AD9856 to bypass the REFCLK
Multiplier function. When active, effectively causes the REFCLK
Multiplier factor to be 1. Defaults value is 1 (REFCLK Multi-
plier bypassed).

INPUT FORMAT SELECT--Register Address 01h, Bits 1
and 0, form the Input Format Mode bits.

10b = 12-bit mode
01b = 6-bit mode
00b = 3-bit mode
Default value is 10b (12-bit mode).

Profile 1 Registers--Active when PROFILE Inputs Are 00b

FREQUENCY TUNING WORD (FTW)--The frequency
tuning word for Profile 1 is formed via a concatenation of regis-
ter addresses 05h, 04h, 03h and 02h. Bit 7 of register address
05h is the most significant bit of the Profile 1 frequency tuning
word. Bit 0 of register address 02h is the least significant bit of
the Profile 1 frequency tuning word. The output frequency
equation is given as: f

OUT

= (FTW

SYSCLK)/2

INTERPOLATION RATE--Register Address 06h, Bits 7
through 2 form the Profile 1 CIC filter interpolation rate value.
Allowed values range from 2 to 63 (decimal).

SPECTRAL INVERSION--Register Address 06h, Bit 1. Ac-
tive high, Profile 1 Spectral Inversion bit. When active, inverted
modulation is performed [I

Cos(

t) + Q

Sin(

t)]. Default is

inactive, logic zero, noninverted modulation [I

Cos(

t) Q

Sin(

t)].

BYPASS HALF-BAND FILTER 3--Register Address 06h, Bit
0. Active high, causes the AD9856 to bypass the third half-band
filter stage that precedes the CIC interpolation filter. Bypassing
the third half-band filter negates the 2

upsample inherent with

this filter and reduces the overall interpolation rate of the half-
band filter chain from 8

to 4

. Default value is 0 (half-band 3

enabled).

AD8320/AD8321 GAIN CONTROL--Register Address 07h,
Bits 7 through 0 form the Profile 1 AD8320/AD8321 gain bits.
The AD9856 dedicates three output pins, which directly in-
terface to the AD8320/AD8321 cable driver amp. This allows
direct control of the cable driver via the AD9856. See the
Programming/Writing the AD8320/AD8321 Cable Driver Gain
Control section of this data sheet for more details. Bit 7 is the
MSB, Bit 0 is the LSB. Default value is 00h.

Profile 2 Registers--Active when PROFILE Inputs Are 01b

Profile 2 Register functionality is identical to Profile 1, with the
exception of the register addresses.

Profile 3 Registers--Active when PROFILE Inputs Are 10b

Profile 3 Register functionality is identical to Profile 1, with the
exception of the register addresses.

Profile 4 Registers--Active when PROFILE Inputs Are 11b

Profile 4 Register functionality is identical to Profile 1, with the
exception of the register addresses.

AD9856

REV. B

THEORY OF OPERATION

To gain a general understanding of the functionality of the
AD9856 it is helpful to refer to Figure 21, which displays a
block diagram of the device architecture. The following is a
general description of the device functionality. Later sections
will detail each of the data path building blocks.

Modulation Mode Operation

The AD9856 accepts 12-bit data words, which are strobed into
the Data Assembler via an internal clock. The input, TxENABLE,
serves as the "valve" which allows data to be accepted or ig-
nored by the Data Assembler. The user has the option to feed
the 12-bit data words to the AD9856 as single 12-bit words,
dual 6-bit words, or quad 3-bit words. This provides the user
with the flexibility to use fewer interface pins, if so desired.
Furthermore, the incoming data is assumed to be complex, in
that alternating 12-bit words are regarded as the inphase (I) and
quadrature (Q) components of a symbol.

The rate at which the 12-bit words are presented to the AD9856
will be referred to as the Input Sample Rate (f

). It should be

pointed out that f

is not the same as the baseband data rate

provided by the user. As a matter of fact, it is required that the
user's baseband data be upsampled by at least a factor of two
(2) before being applied to the AD9856 in order to minimize
the frequency-dependent attenuation associated with the CIC
filter stage (detailed in a later section).

The Data Assembler splits the incoming data word pairs into
separate I/Q data streams. The rate at which the I/Q data word
pairs appear at the output of the Data Assembler will be referred
to as the I/Q Sample Rate (f

). Since two 12-bit input data

words are used to construct the individual I and Q data paths, it
should be apparent that the input sample rate is twice the I/Q
sample rate (i.e., f

= 2

Once through the Data Assembler, the I/Q data streams are fed
through two half-band filters (half-band filters #1 and #2). The
combination of these two filters results in a factor of four (4)
increase of the sample rate. Thus, at the output of half-band
filter #2, the sample rate is 4

. In addition to the sample

rate increase, the half-band filters provide the low-pass filtering
characteristic necessary to suppress the spectral images pro-
duced by the upsampling process. Further upsampling is avail-
able via an optional third half-band filter (half-band filter #3).
When selected, this provides an overall upsampling factor of
eight (8). Thus, if half-band filter #3 is selected, then the sample
rate at its output is 8

After passing through the half-band filter stages, the I/Q data
streams are fed to a Cascaded Integrator-Comb (CIC) filter.
This filter is configured as an interpolating filter, which allows
further upsampling rates of any integer value between 2 and 63,
inclusive. The CIC filter, like the half-bands, has a built-in low-
pass characteristic. Again, this provides for suppression of the
spectral images produced by the upsampling process.

The digital quadrature modulator stage following the CIC filters
is used to frequency shift the baseband spectrum of the incom-
ing data stream up to the desired carrier frequency (this process
is known as upconversion). The carrier frequency is controlled
numerically by a Direct Digital Synthesizer (DDS). The DDS
uses its internal reference clock (SYSCLK) to generate the
desired carrier frequency with a high degree of precision. The
carrier is applied to the I and Q multipliers in quadrature fash-
ion (90

phase offset) and summed to yield a data stream that

is the modulated carrier. It should be noted at this point that the
incoming data has been converted from an input sample rate
of f

to an output sample rate of SYSCLK (see the block

diagram).

The sampled carrier is ultimately destined to serve as the input
data to the digital-to-analog converter (DAC) integrated on the
AD9856. The DAC output spectrum is distorted due to the
intrinsic zero-order hold effect associated with DAC-generated
signals. This distortion is deterministic, however, and follows
the familiar SIN(x)/x (or SINC) envelope. Since the SINC
distortion is predictable, it is also correctable. Hence, the presence
of the optional Inverse SINC filter preceding the DAC. This is a
FIR filter, which has a transfer function conforming to the inverse
of the SINC response. Thus, when selected, it modifies the incom-
ing data stream so that the SINC distortion, which would other-
wise appear in the DAC output spectrum is virtually eliminated.

As mentioned earlier, the output data is sampled at the rate of
SYSCLK. Since the AD9856 is designed to operate at SYSCLK
frequencies up to 200 MHz, there is the potential difficulty of
trying to provide a stable input clock (REFCLK). Although
stable, high frequency oscillators are available commercially they
tend to be cost prohibitive. To alleviate this problem, the AD9856
has a built-in programmable clock multiplier circuit. This allows
the user to use a relatively low frequency (thus, less expensive)
oscillator to generate the REFCLK signal. The low frequency
REFCLK signal can then be multiplied in frequency by an
integer factor of between 4 and 20, inclusive, to become the
SYSCLK signal.

DATA

TxENABLE

DATA

ASSEMBLER

HALF-BAND

FILTER #1

HALF-BAND

FILTER #2

HALF-BAND

FILTER #3

DDS

INV

SINC

INV SINC

BYPASS

SET

OUT

M = 4...20

REFCLK

N = 2...63

(SYSCLK)

(F4)

(F3)

(F2)

(F1)

3, 6, 12

MUX

COS

SIN

CIC

FILTER

QUADRATURE

MODULATOR

MUX

DAC

HBF #3

BYPASS

HBF #3

BYPASS

MUX

HBF #3 BYPASS

(F5)

MUX

REFCLK

MULTIPLIER

(M)

Figure 21. AD9856 Block Diagram

AD9856

REV. B

Single Tone Output Operation

The AD9856 can be configured for frequency synthesis applica-
tions by writing the single tone bit true. In single tone mode, the
AD9856 disengages the modulator and preceding datapath logic
to output a spectrally pure single frequency sine wave. The
AD9856 provides for a 32-bit frequency tuning word, which
results in a tuning resolution of 0.046 Hz at a SYSCLK rate of
200 MHz.

A good rule of thumb when using the AD9856 as a frequency
synthesizer is to limit the fundamental output frequency to 40%
of SYSCLK. This avoids generating aliases too close to the
desired fundamental output frequency, thus minimizing the cost
of filtering the aliases.

All applicable programming features of the AD9856 apply when
configured in single tone mode. These features include:

1. Frequency hopping via the PROFILE inputs and associated

tuning word, which allows Frequency Shift Keying (FSK)
modulation.

2. Ability to bypass the REFCLK Multiplier, which results in

lower phase noise and reduced output jitter.

3. Ability to bypass the SIN(x)/x compensation filter.

4. Full power-down mode.

INPUT WORD RATE (f

) vs. REFCLK RELATIONSHIP

There is a fundamental relationship between the input word rate
(f

) and the frequency of the clock that serves as the timing

source for the AD9856 (REFCLK). f

is defined as the rate at

which K-bit data words (K = 3, 6 or 12) are presented to the
AD9856. There are, however, a number of factors that affect
this relationship. They are:

The interpolation rate of the CIC filter stage.

Whether or not Half-Band Filter #3 is bypassed.

The value of REFCLK Multiplier (if selected).

Input Word Length.

This relationship can be summed up with the following equation:

REFCLK = (2 HNf

)/MI

Where H, N, I and M are integers and are determined as follows:

H =

| 1:

Half-Band Filter #3 Bypassed

| 2:

Half-Band Filter #3 Enabled

M =

| 1:

REFCLK Multiplier Bypassed

| 4

20:

REFCLK Multiplier Enabled

| 1:

Full Word Input Format

| 2:

Half Word Input Format

| 4:

Quarter Word Input Format

N =

CIC interpolation rate (2

63)

It should be obvious from these conditions that REFCLK and
f

have an integer ratio relationship. It is of utmost importance

that the user chooses a value of REFCLK, which will ensure
that this integer ratio relationship is maintained.

I/Q DATA SYNCHRONIZATION

As mentioned above, the AD9856 accepts I/Q data pairs, twos
complement numbering system, in three different word length
modes. The full word mode accepts 12-bit parallel I and Q data.
The half word mode accepts dual 6-bit I and Q data inputs to

form a 12-bit word. The quarter word mode accepts multiple
3-bit I and Q data inputs to form a 12-bit word. For all word
length modes, the AD9856 assembles the data for signal pro-
cessing into time aligned, parallel 12-bit I/Q pairs. In addition to
the word length flexibility, the AD9856 operates in two "input
timing" modes, burst or continuous, programmable via the
serial port.

For burst mode input timing, no external data clock needs to be
provided as the data is oversampled at the D<11:0> pins using
the system clock (SYSCLK). The TxENABLE pin is required
to frame the data burst as the rising edge of TxENABLE is used
to synchronize the AD9856 to the input data rate. The AD9856
registers the input data at the approximate center of the data
valid time. It should be obvious that for larger CIC interpola-
tion rates, more SYSCLK cycles are available to oversample
the input data, maximizing clock jitter tolerances.

For continuous mode input timing, the TxENABLE pin can be
thought of as a data input clock running at 1/2 the input sample
rate (f

/2). In addition to synchronization, for continuous mode

timing, the TxENABLE input indicates to the AD9856 whether
an I or Q input is being presented to the D<11:0> pins. It is
intended that data is presented in alternating fashion such that I
data is followed by Q data. Stated another way, the TxENABLE
pin should maintain approximately a 50/50 duty cycle. As in
burst mode, the rising edge of TxENABLE synchronizes the
AD9856 to the input data rate and the data is registered at the
approximate center of the data valid time. The continuous oper-
ating mode can only be used in conjunction with the full word
input format.

Burst Mode Input Timing

Figures 2226 describe the input timing relationship between
TxENABLE and the 12-bit input data word for all three input
format modes when the AD9856 is configured for burst input
timing. Also shown in these diagrams is the time-aligned, 12-bit
parallel I/Q data as assembled by the AD9856.

Figure 22 describes the classic burst mode timing, for full word
input mode, in which TxENABLE frames the input data stream.
Note that sequential input of alternating I/Q data, starting with
I data, is required.

The input sample rate for full word mode, when the third half-
band filter is engaged, is given by:

= SYSCLK/4N

where N is the CIC interpolation rate.

The input sample rate for full word mode, when the third half-
band filter is not engaged is given by:

= SYSCLK/2N

where N is the CIC interpolation rate

Figure 23 describes an alternate timing method for TxENABLE
when the AD9856 is configured in full word, burst mode
operation. The benefit of this timing is that the AD9856 will
resynchronize the input sampling logic when the rising edge of
TxENABLE is detected. The low time on TxENABLE is lim-
ited to one input sample period and must be low during the Q
data period. The maximum high time on TxENABLE is unlim-
ited. It should be clear that unlimited high time on TxENABLE
results in the timing diagram of Figure 22. See Figure 26 for the
ramifications of violating the TxENABLE low time constraint
when operating in burst mode.

AD9856

REV. B

Figure 24 describes the input timing for half word mode, burst
input timing operation.

In half word mode, data is input on the D<11:6> inputs. The
D<5:0> inputs are unused in this mode and should be tied to
DGND or DVDD. The AD9856 expects the data to be input in
the following manner: I<11:6>,I<5:0>,Q<11:6>,Q<5:0>.
Data is twos complement, the sign bit is D<11> in notation
I<11:0>,Q<11:0>.

The input sample rate for half word mode, when the third half-
band filter is engaged, is given by:

= SYSCLK/2N

where N is the CIC interpolation rate.

The input sample rate for half word mode, when the third half-
band filter is not engaged is given by:

= SYSCLK/N

where N is the CIC interpolation rate.

Figure 25 describes the input timing for quarter word, burst
input timing operation.

In quarter word mode, data is input on the D<11:9> inputs.
The D<8:0> inputs are unused in this mode and should be tied
to DGND or DVDD. The AD9856 expects the data to be input
in the following manner: I<11:9>, I<8:6>, I<5:3>, I<2:0>,
Q<11:9>, Q<8:6>, Q<5:3>, Q<2:0>. Data is twos comple-
ment, the sign bit is D<11> in notation I<11:0>, Q<11:0>.

The input sample rate for quarter word mode, when the third
half-band filter is engaged, is given by:

= SYSCLK/N

where N is the CIC interpolation rate.

Please note that Half-Band Filter #3 must be engaged when operat-
ing in quarter word mode.

TxENABLE

D(11:0)

INTERNAL I

INTERNAL Q

Figure 22. 12-Bit Input Mode, Classic Burst Timing

TxENABLE

D(11:0)

INTERNAL I

INTERNAL Q

Figure 23. 12-Bit Input Mode, Alternate TxENABLE Timing

TxENABLE

D(11:6)

INTERNAL I

INTERNAL Q

I0(11:6)

I0(5:0)

Q0(5:0)

I1(11:6)

I1(5:0)

Q1(11:6)

Q1(5:0)

I2(11:6)

Q0(11:6)

I2(5:0)

Figure 24. 6-Bit Input Mode, Burst Mode Timing

I0(11:9)

I0(8:6)

I0(5:3)

I0(2:0)

Q0(11:9)

Q0(8:6)

Q0(5:3)

Q0(2:0)

I1(11:9)

I1(8:6)

TxENABLE

D(11:9)

INTERNAL I

INTERNAL Q

Figure 25. 3-Bit Input Mode, Burst Mode Timing

AD9856

REV. B

TxENABLE

D(11:0)

INTERNAL I

INTERNAL Q

IN2

IN1

QN2

QN1

LOGIC 0

Figure 26. Burst Mode Input Timing--End of Burst

IN+1

QN+1

IN+2

QN+2

IN+3

QN+3

IN+4

QN+4

IN+5

IN+1

IN+2

IN+3

TxENABLE

D(11:0)

INTERNAL I

INTERNAL Q

IN1

QN1

QN+4

IN+4

QN+3

Figure 27. Continuous Mode Input Timing--TxENABLE Static High

IN+1

QN+1

IN+2

QN+2

IN+3

QN+3

IN+4

QN+4

QN+2

QN+1

IN+3

TxENABLE

D(11:0)

INTERNAL I

INTERNAL Q

IN1

QN1

QN+3

Figure 28. Continuous Mode Input Timing--TxENABLE Static Low

Figure 26 describes the end of burst timing and internal data
assembly. It's important to note that in burst mode operation, if
the TxENABLE input is low for more than one input sample
period, numerical zeros are internally generated and passed to
the data path logic for signal processing. This is not valid for
continuous mode operation, as will be discussed later.

To ensure proper operation, the minimum time between falling
and rising edges of TxENABLE is one input sample period.

Continuous Mode Input Timing

The AD9856 is configured for continuous mode input timing by
writing the Continuous Mode bit true (Logic 1). The Continu-
ous Mode bit is in register address 01h, Bit 6. The AD9856
must be configured for full word input format when operating in
continuous mode input timing. The input data rate equations
described above, for full word mode, apply for continuous mode.
Figure 23, which is the alternate burst mode timing diagram, is
also the continuous mode input timing. Figures 27 and 28 de-
scribe what the internal data assembler will present to the signal
processing logic when the TxENABLE input is held static for

greater than one input sample period. Please note that the tim-
ing diagram of Figures 27 and 28 detail INCORRECT timing
relationships between TxENABLE and data. They are only
presented to indicate that the AD9856 will resynchronize
properly after detecting a rising edge of TxENABLE. It should
also be noted that the significant difference between burst and
continuous mode operation is that in addition to synchronizing
the data, TxENABLE is used to indicate whether an I or Q
input is being sampled.

Do not engage continuous mode simultaneously with the
REFCLK multiplier function. This has been found to corrupt
the CIC interpolating filter, forcing unrecoverable mathematical
overflow that can only be resolved by issuing a RESET com-
mand. The problem is due to the PLL failing to be locked to the
reference clock while nonzero data is being clocked into the
interpolation stages from the data inputs. The recommended
sequency is to first engage the REFCLK multiplier function
(allowing at least 1 ms for loop stabilization) and then engage
continuous mode via software.

AD9856

REV. B

HALF-BAND FILTERS (HBFs)

Before presenting a detailed description of the HBFs, recall that
the input data stream is representative of complex data; i.e., two
input samples are required to produce one I/Q data pair. The I/Q
sample rate is one-half the input data rate. The I/Q sample rate
(the rate at which I or Q samples are presented to the input of
the first half-band filter) will be referred to as f

. Since the

AD9856 is a quadrature modulator, f

represents the baseband

of the internal I/Q sample pairs. It should be emphasized here
that f

is not the same as the baseband of the user's symbol rate

data, which must be upsampled before presentation to the AD9856
(as will be explained later). The I/Q sample rate (f

) puts a

limit on the minimum bandwidth necessary to transmit the f

spectrum. This is the familiar Nyquist limit and is equal to one-
half f

, which hereafter will be referred to as f

NYQ

HBF 1 is a 47-tap filter that provides a factor-of-two increase in
sampling rate. HBF 2 is a 15-tap filter offering an additional
factor-of-two increase in sampling rate. Together, HBF 1 and 2
provide a factor-of-four increase in the sampling rate (4

NYQ

). Their combined insertion loss is a mere 0.01 dB, so

virtually no loss of signal level occurs through the first two HBFs.
HBF 3 is an 11-tap filter and, if selected, increases the sampling
rate by an additional factor of two. Thus, the output sample rate
of HBF 3 is 8

or 16

NYQ

. HBF 3 exhibits 0.03 dB of

signal level loss. As such, the loss in signal level through all
three HBFs is only 0.04 dB and may be ignored for all practi-
cal purposes.

In relation to phase response, all three HBFs are linear phase
filters. As such, virtually no phase distortion is introduced within
the passband of the filters. This is an important feature as phase
distortion is generally intolerable in a data transmission system.

In addition to knowledge of the insertion loss and phase re-
sponse of the HBFs, some knowledge of the frequency response
of the HBFs is useful as well. The combined frequency response
of HBF 1 and 2 is shown in Figure 29.

The usable bandwidth of the filter chain puts a limit on the maxi-
mum data rate that can be propagated through the AD9856. A
look at the passband detail of the HBF 1 and 2 response indi-
cates that in order to maintain an amplitude error of no more
than 1 dB, we are restricted to signals having a bandwidth of no
more than about 90% of f

NYQ

. Thus, in order to keep the band-

width of the data in the flat portion of the filter passband, the
user must oversample the baseband data by at least a factor of
two prior to presenting it to the AD9856. Note that without
oversampling, the Nyquist bandwidth of the baseband data
corresponds to the f

NYQ

. As such, the upper end of the data

bandwidth will suffer 6 dB or more of attenuation due to the
frequency response of HBF 1 and 2. Furthermore, if the base-
band data applied to the AD9856 has been pulse shaped there is
an additional concern. Typically, pulse shaping is applied to the
baseband data via a filter having a raised cosine response. In
such cases, an

value is used to modify the bandwidth of the

data where the value of

is such that 0

1. A value of 0

causes the data bandwidth to correspond to the Nyquist band-
width. A value of 1 causes the data bandwidth to be extended to
twice the Nyquist bandwidth. Thus, with 2

oversampling of

the baseband data and

= 1, the Nyquist bandwidth of the data

will correspond with the I/Q Nyquist bandwidth. As stated
earlier, this results in problems near the upper edge of the data
bandwidth due to the frequency response of HBF 1 and 2.

3.5

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

30

100

0.5

MAGNITUDE dB

1.0

1.5

2.0

2.5

3.0

4.0

40

50

60

70

80

90

10

20

a. Half-Band 1 and 2 Frequency Response

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

0.1

MAGNITUDE dB

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

b. Passband Detail

Figure 29. Combined Frequency Response of HBF 1 and 2

To reiterate, the user must oversample their baseband data by at
least a factor of two (2). In addition, there is a further restriction
on pulse shaping. That is, the maximum value of

that can be

implemented is 0.8. This is because the data bandwidth be-
comes: 1/2(1 +

) f

NYQ

= 0.9 f

NYQ

, which puts the data band-

width at the extreme edge of the flat portion of the filter response.
If a particular application requires an

value between 0.8 and

1, then the user must oversample the baseband data by at least a
factor of four (4).

AD9856

REV. B

In applications requiring both a low data rate and a high output
sample rate, a third HBF is available (HBF 3). Selection of
HBF 3 offers an upsampling ratio of eight (8) instead of four
(4). The combined frequency response of HBF 1, 2 and 3 is
shown in Figure 30. Comparing the passband detail of HBF 1
and 2 with the passband detail of HBF 1, 2 and 3, it becomes
evident that HBF 3 has virtually no impact on frequency re-
sponse from 0 to 1 (where 1 corresponds to f

NYQ

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

30

100

MAGNITUDE dB

40

50

60

70

80

90

10

20

a. Half-Band 1, 2 and 3 Frequency Response

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

0.1

MAGNITUDE dB

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

b. Passband Detail

Figure 30. Combined Frequency Response of HBF 1, 2 and 3

CASCADED INTEGRATOR-COMB (CIC) FILTER

A CIC filter is unlike a typical FIR filter in that it offers the
flexibility to handle differing input and output sample rates
(only in integer ratios, however). In the purest sense, a CIC
filter can provide either an increase or a decrease in sample rate
at the output relative to the input, depending on the architec-
ture. If the integration stage precedes the comb stage, the CIC
filter provides sample rate reduction (decimation). When the
comb stage precedes the integrator stage the CIC filter provides
an increase in sample rate (interpolation). In the AD9856, the
CIC filter is configured as an interpolator. In fact, it is a pro-
grammable interpolator and provides a sample rate increase, R,
such that 2

63.

In addition to the ability to provide a change in sample rate
between input and output, a CIC filter also has an intrinsic low-
pass frequency response characteristic. The frequency response
of a CIC filter is dependent on three factors:

1. The rate change ratio, R.

2. The order of the filter, N.

3. The number of unit delays per stage, M.

It can be shown that the system function, H(z), of a CIC filter is
given by:

H z

( )

The form on the far right has the advantage of providing a result
for z = 1 (corresponding to zero frequency or dc). The alternate
form yields an indeterminate form (0/0) for z = 1, but is other-
wise identical. The only variable parameter for the AD9856's CIC
filter is R. M and N are fixed at 1 and 4, respectively. Thus,
the CIC system function for the AD9856 simplifies to:

H z

( )

The transfer function is given by:

H f

( )

(

)

(

)

(

)

The frequency response in this form is such that f is scaled to
the output sample rate of the CIC filter. That is, f = 1 corre-
sponds to the frequency of the output sample rate of the CIC
filter. H(f/R) will yield the frequency response with respect to
the input sample of the CIC filter. Figure 31 reveals the CIC
frequency response and passband detail for R = 2 and R = 63
and with HBF 3 bypassed. Figure 32 is similar but with HBF 3
selected. Note the flatter passband response when HBF 3 is
employed.

As with the case of the HBFs, consideration must be given to
the frequency dependent attenuation that the CIC filter intro-
duces over the frequency range of the data to be transmitted.
Note that the CIC frequency response plots have f

NYQ

as their

reference frequency; i.e., unity (1) on the frequency scale corre-
sponds to f

NYQ

. If the incoming data that is applied to the

AD9856 is oversampled by a factor of 2 (as required), then the
Nyquist bandwidth of the applied data is one-half f

NYQ

on the CIC

frequency response plots. A look at the 0.5 point on the passband
detail plots reveals a worst case attenuation of about 0.25 dB
(HBF 3 bypassed, R = 63). This, of course, assumes pulse shaped
data with

= 0 (minimum bandwidth scenario). When a value

= 1 is used, the bandwidth of the data corresponds to f

NYQ

(the point, 1.0 on the CIC frequency scale). Thus, the worst
case attenuation for

= 1 is about 0.9 dB.

AD9856

REV. B

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

MAGNITUDE dB

150

10 12 14 16 18 20

140

130

120

110

100

90

80

70

60

50

40

30

20

10

22 24 26 28 30 32

a. CIC Frequency Response (R = 2, HBF 3 Bypass)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

MAGNITUDE dB

72 108

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

144 180 216 252 288 324 360 396 432 468 504

b. CIC Frequency Response (R = 63, HBF 3 Bypass)

The degree of the impact of the attenuation introduced by the
CIC filter over the Nyquist bandwidth of the data is application
specific. The user must decide how much attenuation is accept-
able. If less attenuation is desired, then additional oversampling
of the baseband data must be employed. Alternatively, the user
can precompensate the baseband data before presenting it to the
AD9856. That is, if the data is precompensated through a filter
that has a frequency response characteristic, which is the inverse
of the CIC filter response, then the overall system response can
be nearly perfectly flattened over the bandwidth of the data.

Another issue to consider with the CIC filters is insertion loss.
Unfortunately, CIC insertion loss is not fixed but is a function
of R, M and N. Since M and N are fixed for the AD9856, the
CIC insertion loss is a function of R, only.

Interpolation rates that are an integer power-of-2 result in no
insertion loss. However, all noninteger power-of-2 interpolation
rates result in a specific amount of insertion loss.

To help overcome the insertion loss problem, the AD9856
provides the user a means to boost the gain through the CIC

stage by a factor of 2 (via the CIC Gain bit--see the AD9856
control register description). The reason for this feature is to
allow the user to take advantage of the full dynamic range of the
DAC, thus maximizing the signal-to-noise ratio (SNR) at the
output of the DAC stage. Obviously, it is desirable to operate
the DAC over its full-scale range in order to minimize the inher-
ent quantization effects associated with a DAC. Any significant
loss through the CIC stage will be reflected at the DAC output
as a reduction in SNR. The degradation in SNR can be over-
come by boosting the CIC output level. Table II (The CIC
Interpolation Filter Insertion Loss Table) tabulates insertion
loss as a function of R. The values are provided in linear and
decibel form, both with and without the factor-of-two gain
employed.

A word of caution: When the CIC Gain bit is active, the user
must ensure that the data supplied to the AD9856 is scaled
down to yield an overall gain of unity (1) through the CIC filter
stage. Gains in excess of unity are likely to cause overflow errors
in the data path, thereby compromising the validity of the ana-
log output signal.

Figure 31. CIC Filter Frequency Response (HB 3 Bypassed and R = 2, 63)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

0.2

MAGNITUDE dB

0.4

0.6

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.8

1.0

1.2

1.4

1.6

1.8

2.0

c. Passband Detail (R = 2, HBF 3 Bypass)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

0.2

MAGNITUDE dB

0.4

0.6

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.8

1.0

1.2

1.4

1.6

1.8

2.0

d. Passband Detail (R = 63, HBF 3 Bypass)

AD9856

REV. B

Figure 32. CIC Filter Frequency Response (HB 3 Selected and R = 2, 63)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

MAGNITUDE dB

150

10 12 14 16 18 20

140

130

120

110

100

90

80

70

60

50

40

30

20

10

22 24 26 28 30 32

a. CIC Frequency Response (R = 2, HBF 3 Selected)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

576

MAGNITUDE dB

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

144 216 288 360 432 504

648 720 792 864 936 1008

b. CIC Frequency Response (R = 63, HBF 3 Active)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

0.2

MAGNITUDE dB

0.4

0.6

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.8

1.0

1.2

1.4

1.6

1.8

2.0

c. Passband Detail (R = 2, HBF 3 Selected)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

0.2

MAGNITUDE dB

0.4

0.6

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.8

1.0

1.2

1.4

1.6

1.8

2.0

d. Passband Detail (R = 63, HBF 3 Active)

DIGITAL QUADRATURE MODULATOR

Following the CIC filter stage the I and Q data (which have
been processed independently up to this point) are mixed in the
modulator stage to produce a digital modulated carrier. The
carrier frequency is selected by programming the direct digital
synthesizer (see the DDS section) with the appropriate 32-bit
tuning word via the AD9856 control registers. The DDS simul-
taneously generates a digital (sampled) sine and cosine wave at
the programmed carrier frequency. The digital sine and cosine
data is multiplied by the Q and I data, respectively, to create the
quadrature components of the original data upconverted to the
carrier frequency. The quadrature components are digitally
summed and passed on to the subsequent stages.

The key point is that the modulation is done digitally, which
eliminates the phase and gain imbalance and crosstalk issues
typically associated with analog modulators. Note that the
modulated "signal" is actually a number stream sampled at the

rate of SYSCLK, which is the same rate at which the DAC is
clocked (see Figure 21, the AD9856 block diagram).

It should be pointed out that the architecture of the quadrature
modulator results in a 3 dB loss of signal level. To visualize this,
assume that both the I data and Q data are fixed at the maxi-
mum possible digital value, x. Then the output of the modula-
tor, y, is:

y = x

cos(

) + x

sin(

) = x

[cos(

) + sin(

)]

From this equation it can be shown that y assumes a maximum
value of x

2 (a gain of 3 dB). However, if the same number of

bits were used to represent the y values, as is used to represent
the x values, an overflow would occur. To prevent this possibil-
ity, an effective "divide-by-two" is implemented on the y values,
which reduces the maximum value of y by a factor of two. Since
division by two results in a 6 dB loss, the modulator yields an
overall loss of 3 dB (3 dB 6 dB = 3 dB, or 3 dB of loss).

AD9856

REV. B

Table II. CIC Interpolation Filter Insertion Loss Table

Interpolation Rate

Default Gain

2 Gain

(Linear)

(dB)

(Linear)

(dB)

1.0000

0.000

2.0000

6.021

0.8438

1.476

1.6875

4.545

1.0000

0.000

2.0000

6.021

0.9766

0.206

1.9531

5.815

0.8438

1.476

1.6875

4.545

0.6699

3.480

1.3398

2.541

1.0000

0.000

2.0000

6.021

0.7119

2.951

1.4238

3.069

0.9766

0.206

1.9531

5.815

0.6499

3.743

1.2998

2.278

0.8438

1.476

1.6875

4.545

0.5364

5.411

1.0728

0.610

0.6699

3.480

1.3398

2.541

0.8240

1.682

1.6479

4.339

1.0000

0.000

2.0000

6.021

0.5997

4.441

1.1995

1.580

0.7119

2.951

1.4238

3.069

0.8373

1.543

1.6746

4.478

0.9766

0.206

1.9531

5.815

0.5652

4.955

1.1305

1.065

0.6499

3.743

1.2998

2.278

0.7426

2.585

1.4852

3.436

0.8438

1.476

1.6875

4.545

0.9537

0.412

1.9073

5.609

0.5364

5.411

1.0728

0.610

0.6007

4.427

1.2014

1.593

0.6699

3.480

1.3398

2.541

0.7443

2.565

1.4886

3.455

0.8240

1.682

1.6479

4.339

0.9091

0.827

1.8183

5.193

1.0000

0.000

2.0000

6.021

0.5484

5.219

1.0967

0.802

0.5997

4.441

1.1995

1.580

0.6542

3.686

1.3084

2.335

0.7119

2.951

1.4238

3.069

0.7729

2.237

1.5458

3.783

0.8373

1.543

1.6746

4.478

0.9051

0.866

1.8103

5.155

0.9766

0.206

1.9531

5.815

0.5258

5.583

1.0517

0.437

0.5652

4.955

1.1305

1.065

0.6066

4.342

1.2132

1.679

0.6499

3.743

1.2998

2.278

0.6952

3.157

1.3905

2.863

0.7426

2.585

1.4852

3.436

0.7921

2.024

1.5842

3.996

0.8438

1.476

1.6875

4.545

0.8976

0.938

1.7952

5.082

0.9537

0.412

1.9073

5.609

0.5060

5.917

1.0120

0.104

0.5364

5.411

1.0728

0.610

0.5679

4.914

1.1358

1.106

0.6007

4.427

1.2014

1.593

0.6347

3.949

1.2693

2.072

0.6699

3.480

1.3398

2.541

0.7065

3.018

1.4129

3.002

0.7443

2.565

1.4886

3.455

0.7835

2.120

1.5669

3.901

0.8240

1.682

1.6479

4.339

0.8659

1.251

1.7317

4.770

0.9091

0.827

1.8183

5.193

0.9539

0.410

1.9077

5.610

AD9856

REV. B

INVERSE SINC FILTER (ISF)

The AD9856 is almost entirely a digital device. The input
"signal" is made up of a time series of digital data words. These
data words propagate through the device as numbers. Ultimately,
this number stream must be converted to an analog signal. To
this end, the AD9856 incorporates an integrated DAC. The
output waveform of the DAC is the familiar "staircase" pattern
typical of a signal that is sampled and quantized. The staircase
pattern is a result of the finite time that the DAC holds a quan-
tized level until the next sampling instant. This is known as a
zero-order hold function. The spectrum of the zero-order hold
function is the familiar SIN(x)/x, or SINC, envelope.

The series of digital data words presented at the input of the
DAC represent an impulse stream. It is the spectrum of this
impulse stream, which is the desired output signal. Due to the
zero-order hold effect of the DAC, however, the output spec-
trum is the product of the zero-order hold spectrum (the SINC
envelope) and the Fourier transform of the impulse stream.
Thus, there is an intrinsic distortion in the output spectrum,
which follows the SINC response.

The SINC response is deterministic and totally predictable.
Thus, it is possible to pre-distort the input data stream in a
manner, which compensates for the SINC envelope distortion.
This can be accomplished by means of an ISF. The ISF incor-
porated on the AD9856 is a 17-tap, linear phase FIR filter. Its
frequency response characteristic is the inverse of the SINC
envelope. Data sent through the ISF is altered in such a way as
to correct for the SINC envelope distortion.

It should be noted, however, that the ISF is sampled at the
same rate as the DAC. Thus, the effective range of the SINC
envelope compensation only extends to the Nyquist frequency
(1/2 of the DAC sample rate).

Figure 33 is a plot that shows the effectiveness of the ISF in
correcting for the SINC distortion. The plot includes a graph of
the SINC envelope, the ISF response and the SYSTEM re-
sponse (which is the product of the SINC and ISF responses).
It should be mentioned at this point that the ISF exhibits an
insertion loss of 3.1 dB. Thus, signal levels at the output of the
AD9856 with the ISF bypassed are 3.1 dB higher than with the
ISF engaged. However, for modulated output signals, which
have a relatively wide bandwidth, the benefits of the SINC

FREQUENCY NORMALIZED TO SAMPLE RATE

0.5

4.0

0.1

0.2

0.3

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.5

1.0

0.5

0.4

2.0

4.0

3.5

3.0

2.5

ISF

SINC

SYSTEM

Figure 33. Inverse SINC Filter Response

compensation usually outweigh the 3 dB loss in output level.
The decision of whether or not to use the ISF is an application
specific system design issue.

DIRECT DIGITAL SYNTHESIZER FUNCTION

The direct digital synthesizer (DDS) block generates the sine/
cosine carrier reference signals that are digitally modulated by
the I/Q data paths. The DDS function is frequency tuned via
the serial control port with a 32-bit tuning word. This allows the
AD9856's output carrier frequency to be very precisely tuned
while still providing output frequency agility.

The equation relating output frequency of the AD9856 digital
modulator to the frequency tuning word (FTWORD) and the
system clock (SYSCLK) is given as:

OUT

= (FTWORD

SYSCLK)/2

Where: A

OUT

and SYSCLK frequencies are in Hz and

FTWORD is a decimal number from 0 to 4,294,967,296 (2

)

Example: Find the FTWORD for A

OUT

= 41 MHz and

SYSCLK = 122.88 MHz

If A

OUT

= 41 MHz and SYSCLK = 122.88 MHz, then:

FTWORD = 556AAAAB hex

Loading 556AAAABh into control bus registers 02h05h (for
Profile 1) programs the AD9856 for A

OUT

= 41 MHz, given a

SYSCLK frequency of 122.88 MHz.

D/A CONVERTER

A 12-bit digital-to-analog converter (DAC) is used to convert
the digitally processed waveform into an analog signal. The
worst case spurious signals due to the DAC are the harmonics of
the fundamental signal and their aliases (please see the AD9851
Complete-DDS data sheet for a detailed explanation of aliased
images). The wideband 12-bit DAC in the AD9856 maintains
spurious-free dynamic range (SFDR) performance of 60 dBc
up to A

OUT

= 42 MHz and 55 dBc up to A

OUT

= 65 MHz.

The conversion process will produce aliased components of the
fundamental signal at n

SYSCLK

CARRIER

(n = 1, 2, 3).

These are typically filtered with an external RLC filter at the
DAC output. It is important for this analog filter to have a suffi-
ciently flat gain and linear phase response across the bandwidth
of interest so as to avoid modulation impairments. A relatively
inexpensive 7th order elliptical low-pass filter is sufficient to
suppress the aliased components for HFC network applications.

The AD9856 provides true and complement current outputs on
pins 30 and 29 respectively. The full-scale output current is set
by the R

SET

resistor at Pin 25. The value of R

SET

for a particular

OUT

is determined using the following equation:

SET

= 39.936/I

OUT

For example, if a full-scale output current of 20 mA is desired,
then R

SET

= (39.936/0.02), or approximately 2 k

. Every dou-

bling of the R

SET

value will halve the output current. Maximum

output current is specified as 20 mA.

The full-scale output current range of the AD9856 is 5 mA
20 mA. Full-scale output currents outside of this range will
degrade SFDR performance. SFDR is also slightly affected by
output matching, that is, the two outputs should be terminated
equally for best SFDR performance.

AD9856

REV. B

The output load should be located as close as possible to the
AD9856 package to minimize stray capacitance and inductance.
The load may be a simple resistor to ground, an op amp
current-to-voltage converter, or a transformer-coupled circuit.
It is best not to attempt to directly drive highly reactive loads
(such as an LC filter). Driving an LC filter without a trans-
former requires that the filter be doubly terminated for best
performance, that is, the filter input and output should both be
resistively terminated with the appropriate values. The parallel
combination of the two terminations will determine the load
that the AD9856 will see for signals within the filter passband.
For example, a 50

terminated input/output low-pass filter will

look like a 25

load to the AD9856.

The output compliance voltage of the AD9856 is 0.5 V to
+1.5 V. Any signal developed at the DAC output should not
exceed +1.5 V, otherwise, signal distortion will result. Further-
more, the signal may extend below ground as much as 0.5 V
without damage or signal distortion. The use of a transformer
with a grounded center-tap for common-mode rejection results in
signals at the AD9856 DAC output pins that are symmetrical
about ground.

As previously mentioned, by differentially combining the two
signals the user can provide some degree of common mode
signal rejection. A differential combiner might consist of a trans-
former or an op amp. The object is to combine or amplify only
the difference between two signals and to reject any common,
usually undesirable, characteristic, such as 60 Hz hum or "clock
feedthrough" that is equally present on both input signals. The
AD9856 true and complement outputs can be differentially
combined using a broadband 1:1 transformer with a grounded,
center-tapped primary to perform differential combining of the
two DAC outputs.

REFERENCE CLOCK MULTIPLIER

Due to the fact that the AD9856 is a DDS-based modulator, a
relatively high frequency system clock is required. For DDS
applications, the carrier is typically limited to about 40% of
SYSCLK. For a 65 MHz carrier, the system clock required is
above 160 MHz. To avoid the cost associated with these high
frequency references, and the noise coupling issues associated
with operating a high frequency clock on a PC board, the
AD9856 provides an on-chip programmable clock multiplier
(REFCLK Multiplier). The available clock multiplier range is
from 4

to 20

, in integer steps. With the REFCLK Multiplier

enabled, the input reference clock required for the AD9856 can
be kept in the 10 MHz to 50 MHz range for 200 MHz system
operation, which results in cost and system implementation
savings. The REFCLK Multiplier function maintains clock
integrity as evidenced by the AD9856's system phase noise
characteristics of 105 dBc/Hz (A

OUT

= 40 MHz, REFCLK

Multiplier = 6, Offset = 1 kHz) and virtually no clock-related
spurii in the output spectrum. External loop filter components
consisting of a series resistor (1.3 k

) and capacitor (0.01

provide the compensation zero for the REFCLK Multiplier PLL
loop. The overall loop performance has been optimized for these
component values.

THROUGHPUT AND LATENCY

Data latency through the AD9856 is easiest to describe in terms
of SYSCLK clock cycles. Latency is a function of the AD9856
configuration; primarily affected by the CIC interpolation rate
and whether the third half-band filter is engaged.

When the third half-band filter is engaged the AD9856 latency
is given by:

126 N + 37 SYSCLK clock cycles

where N is the CIC interpolation rate.

If the AD9856 is configured to bypass the third half-band filter,
the latency is given by:

63 N + 37 SYSCLK clock cycles.

These equations should be considered estimates as observed
latency may be data dependent. The latency was calculated
using the linear delay model for the FIR filters.

In single tone mode, frequency hopping is accomplished via
changing the PROFILE input pins. The time required to switch
from one frequency to another is less than 50 SYSCLK cycles
with the Inverse SINC Filter engaged. With the Inverse SINC
Filter bypassed, the latency drops to less than 35 SYSCLK
cycles.

CONTROL INTERFACE

The AD9856 serial port is a flexible, synchronous serial com-
munications port allowing easy interface to many industry stan-
dard microcontrollers and microprocessors. The serial I/O is
compatible with most synchronous transfer formats, including
both the Motorola 6905/11 SPI and Intel 8051 SSR protocols.

The interface allows read/write access to all registers that config-
ure the AD9856. Single or multiple byte transfers are supported
as well as MSB first or LSB first transfer formats. The AD9856's
serial interface port can be configured as a single pin I/O (SDIO)
or two unidirectional pins for in/out (SDIO/SDO).

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the AD9856.
Phase 1 is the instruction cycle, which is the writing of an in-
struction byte into the AD9856, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9856 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the upcom-
ing data transfer is read or write, the number of bytes in the data
transfer (14), and the starting register address for the first byte
of the data transfer.

The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9856. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9856
and the system controller. Phase 2 of the communication cycle
is a transfer of 1, 2, 3, or 4 data bytes as determined by the
instruction byte. Normally, using one communication cycle in a
multibyte transfer is the preferred method. However, single byte
communication cycles are useful to reduce CPU overhead when
register access requires one byte only. Examples of this may be
to write the AD9856 SLEEP bit, or an AD8320/AD8321 gain
control byte.

AD9856

REV. B

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 34. Serial Port Writing Timing--Clock Stall Low

O 7

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

DON'T CARE

SDIO

SCLK

SDO

O 6

O 5

O 4

O 3

O 2

O 1

O 0

Figure 35. Three-Wire Serial Port Read Timing--Clock Stall Low

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 36. Serial Port Write Timing--Clock Stall High

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

O 7

O 6

O 5

O 4

O 3

O 2

O 1

O 0

Figure 37. Two-Wire Serial Port Read Timing--Clock Stall High

At the completion of any communication cycle, the AD9856
serial port controller expects the next 8 rising SCLK edges to be
the instruction byte of the next communication cycle.

All data input to the AD9856 is registered on the rising edge of
SCLK. All data is driven out of the AD9856 on the falling edge
of SCLK.

Figures 3437 are useful in understanding the general operation
of the AD9856 Serial Port.

INSTRUCTION BYTE

The instruction byte contains the following information as shown
below (see Table III):

Table III. Instruction Byte Information

MSB

LSB

AD9856

REV. B

WBit 7 of the instruction byte determines whether a read or

write data transfer will occur after the instruction byte write.
Logic high indicates read operation. Logic zero indicates a write
operation.

N1, N0--Bits 6 and 5 of the instruction byte determine the
number of bytes to be transferred during the data transfer cycle
of the communications cycle. The bit decodes are shown in
Table IV.

Table IV. N1, N2 Decode Bits

Description

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

A4, A3, A2, A1, A0--Bits 4, 3, 2, 1, 0 of the instruction byte
determine which register is accessed during the data transfer
portion of the communications cycle. For multibyte transfers,
this address is the starting byte address. The remaining register
addresses are generated by the AD9856.

SERIAL INTERFACE PORT PIN DESCRIPTION

SCLK--Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9856 and to run the internal state ma-
chines. SCLK maximum frequency is 10 MHz.
CS--Chip Select. Active low input that allows more than one
device on the same serial communications lines. The SDO and
SDIO pins will go to a high impedance state when this input is
high. If driven high during any communications cycle, that cycle
is suspended until

CS is reactivated low. Chip Select can be tied

low in systems that maintain control of SCLK.

SDIO--Serial Data I/O. Data is always written into the AD9856
on this pin. However, this pin can be used as a bidirectional
data line. The configuration of this pin is controlled by Bit 7 of
register address 0h. The default is logic zero, which configures
the SDIO pin as bidirectional.

SDO--Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In the
case where the AD9856 operates in a single bidirectional I/O
mode, this pin does not output data and is set to a high imped-
ance state.

SYNC I/O--Synchronizes the I/O port state machines without
affecting the addressable registers contents. An active high input
on the SYNC I/O pin causes the current communication cycle
to abort. After SYNC I/O returns low (Logic 0) another com-
munication cycle may begin, starting with the instruction byte
write.

CA CLK--Output clock pin to the AD8320/AD8321. If using
the AD9856 to control the AD8320/AD8321 Programmable
Cable Driver Amplifier, connect this pin to the CLK input of
the AD8320/AD8321.

CA DATA--Output data pin to the AD8320/AD8321. If using
the AD9856 to control the AD8320/AD8321 Programmable
Cable Driver Amplifier, connect this pin to the SDATA input of
the AD8320/AD8321.

CA ENABLE--Output Enable pin to the AD8320/AD8321. If
using the AD9856 to control the AD8320/AD8321 Program-
mable Cable Driver Amplifier, connect this pin to the DATAEN
input of the AD8320/AD8321.

MSB/LSB TRANSFERS

The AD9856 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the REG0<6> bit. The default value
of REG0<6> is low (MSB first). When REG0<6> is set active
high, the AD9856 serial port is in LSB first format. The instruc-
tion byte must be written in the format indicated by REG0<6>.
That is, if the AD9856 is in LSB first mode, the instruction byte
must be written from least significant bit to most significant bit.
Multibyte data transfers in MSB format can be completed by
writing an instruction byte that includes the register address
of the most significant byte. In MSB first mode, the serial port
internal byte address generator decrements for each byte
required of the multibyte communication cycle. Multibyte data
transfers in LSB first format can be completed by writing an
instruction byte that includes the register address of the least
significant byte. In LSB first

mode, the serial port internal byte

address generator increments for each byte required of the
multibyte communication cycle.

NOTES ON SERIAL PORT OPERATION

The AD9856 serial port configuration bits reside in Bits 6 and 7
of register address 0h. It is important to note that the configura-
tion changes immediately upon writing to this register. For
multibyte transfers, writing to this register may occur during the

middle of a communication cycle. Care must be taken to
compensate for this new configuration for the remainder of
the current communication cycle.

The AD9856 serial port controller address can roll from 19h to
0h for multibyte I/O operations if the MSB first mode is active.
The serial port controller address can roll from 0h to 19h for
multibyte I/O operations if the LSB first mode is active.

The system must maintain synchronization with the AD9856 or
the internal control logic will not be able to recognize further
instructions. For example, if the system sends an instruction
byte for a 2-byte write, then pulses the SCLK pin for a 3-byte
write (24 additional SCLK rising edges), communication syn-
chronization is lost. In this case, the first 16 SCLK rising edges
after the instruction cycle will properly write the first two data
bytes into the AD9856, but the next eight rising SCLK edges
are interpreted as the next instruction byte, not the final byte of
the previous communication cycle.

In the case where synchronization is lost between the system
and the AD9856, the SYNC I/O pin provides a means to re-
establish synchronization without re-initializing the entire chip.
The SYNC I/O pin enables the user to reset the AD9856 state
machine to accept the next eight SCLK rising edges to be coin-
cident with the instruction phase of a new communication cycle.
By applying and removing a "high" signal to the SYNC I/O pin,
the AD9856 is set to once again begin performing the commu-
nication cycle in synchronization with the system. Any informa-
tion that had been written to the AD9856 registers during a
valid communication cycle prior to loss of synchronization will
remain intact.

AD9856

REV. B

PROGRAMMING/WRITING THE AD8320/AD8321 CABLE
DRIVER AMPLIFIER GAIN CONTROL

Programming the Gain Control register of the AD8320/AD8321
programmable cable driver amplifier can be accomplished via
the AD9856 serial port. Four 8-bit registers (one per profile)
within the AD9856 store the gain value to be written to the
AD8320/AD8321. The AD8320/AD8321 is written via three
dedicated AD9856 output pins that are directly connected to
the AD8320/AD8321's serial input port. The transfer of data
from the AD9856 to the AD8320/AD8321 requires 136 SYSCLK
clock cycles and occurs upon detection of three conditions.
Each is described below:

1. Power-up Reset--Upon initial power up, the AD9856 clears

(Logic 0) the contents of control registers 07h, 0Dh, 13h,
and 19h, which defines the lowest gain setting of the AD8320/
AD8321. Thus, the AD9856 writes all 0s out of the AD8320/
AD8321 serial interface.

SYMBOL

DEFINITION

MIN

PRE

SETUP TIME

30ns

SCLK

PERIOD OF SERIAL DATA CLOCK

100ns

DSU

SERIAL DATA SETUP TIME

30ns

SCLKPWH

SERIAL DATA CLOCK PULSEWIDTH HIGH

40ns

SCLKPWL

SERIAL DATA CLOCK PULSEWIDTH LOW

40ns

DHLD

SERIAL DATA HOLD TIME

0ns

SCLK

SDIO

1ST BIT

2ND BIT

DSU

DHLD

SCLKPWH

SCLKPWL

SCLK

PRE

Figure 38. Timing Diagram for Data Write to AD9856

SYMBOL

DEFINITION

MAX

DATA VALID TIME

30ns

SCLK

SDIO

1ST BIT

2ND BIT

SDO

Figure 39. Timing Diagram for Read from AD9856

2. Change in profile selection bits (PS1, PS0)--The AD9856

samples the PS1, PS0 input pins and writes to the AD8320/
AD8321 gain control register when a change in profile is
determined. The data written to the AD8320/AD8321 comes
from the AD9856 gain control register associated with the
current profile.

3. Serial Port Write of AD9856 Registers that Contain

AD8320/AD8321 Data--The AD9856 will write to the
AD8320/AD8321 with data from the gain control register
associated with the current profile whenever ANY AD9856
gain control register is updated. The user does not have to
write the AD9856 in any particular order or be concerned
with time between writes. If the AD9856 is currently writ-
ing to the AD8320/AD8321 while one of the four AD9856
gain control registers is being addressed, the AD9856 will
immediately terminate the AD8320/AD8321 write sequence
(without updating the AD8320/AD8321) and begin a new
AD8320/AD8321 write sequence.

AD9856

REV. B

UNDERSTANDING AND USING PIN SELECTABLE
MODULATOR PROFILES

The AD9856 Quadrature Digital Upconverter is capable of
storing four preconfigured modulation modes called "profiles"
that define the following:

Output Frequency--32 Bits

Interpolation Rate--6 Bits

Spectral Inversion Status--1 Bit

Bypass 3rd Half-Band Filter--1 Bit

Gain Control of AD8320/AD8321--8 Bits

Output Frequency: This attribute consists of four 8-bit words
loaded into four register addresses to form a 32-bit frequency
tuning word (FTW) for each profile. The lowest register address
corresponds to the least significant 8-bit word. Ascending
addresses correspond to increasingly significant 8-bit words.
The output frequency equation is given as: f

OUT

= (FTW

SYSCLK)/2

Interpolation Rate: Consists of a 6-bit word representing the
allowed interpolation values from 2 to 63. Interpolation is the
mechanism used to "up-sample" or multiply the input data rate
such that it exactly matches that of the DDS sample rate
(SYSCLK). This implies that the system clock must be an exact
multiple of the symbol rate. This 6-bit word represents the 6 MSBs
of the eight bits allocated for that address. The remaining two
bits contain the spectral inversion status bit and half-band by-
pass bit.

Spectral Inversion: Single bit that when at Logic 0 the default
or "noninverted" output from the adder is sent to the following
stages. A Logic 1 will cause the inverted output to be sent to the
following stages. The noninverted output is described as I

Cos(

t) Q

Sin(

t). The inverted output is described as I

Cos(

t) + Q

Sin(

t). This bit is located adjacent to the LSB

at the same address as the interpolation rate (see above).

Bypass Third Half-Band Filter: A single bit located in the
LSB position of the same address as the interpolation rate.
When this bit is Logic 0, the third half-band filter is engaged

and its inherent 2

interpolation rate is applied. When this bit is

Logic 1, the third half-band filter is bypassed and the 2

inter-

polation rate is negated. This allows users to input higher data
rates--rates that may be too high for the minimum interpolation
rate if all three half-band filters with their inherent 2

interpola-

tion rate are engaged. The overall effect is to reduce minimum
interpolation rate from 8

to 4

AD8320/AD8321 Gain Control: An 8-bit word that controls
the gain of an AD8320/AD8321 Programmable Gain Amplifier
connected to the AD9856 with the 3-bit SPI interface bus. Gain
range is from 10 dB (00 hex) to +26 dB (FFhex). The gain is
linear in V/V/LSB and follows the equation: A

= 0.316 + 0.077

Code. Where "Code" is the decimal equivalent of the 8-bit

gain word.

Profile Selection: After profiles have been loaded into the
appropriate registers, the user may select which profile to use
with two input pins: PS0 and PS1, Pins 45 and 46. Profiles are
selected according to the table below.

Table V. Profile Select Matrix

PS1

PS0

PROFILE

Except while in single tone mode, it is recommended that users
suspend the TxENABLE function by bringing that pin to Logic
0 prior to changing from one profile to another and then
reasserting TxENABLE afterwards. This assures that any
dis-continuities resulting from register data transfer are not
transmitted up or downstream. Furthermore, changing interpo-
lation rates during a burst may create an unrecoverable digital
overflow condition that would interrupt transmission of the
current burst until a RESET and reloading procedure would be
completed.

GAIN TRANSFER

GAIN TRANSFER
G1

CA ENABLE

CA CLK

CA DATA

VALID DATA WORD G1

MSB...LSB

VALID DATA WORD G2

8 CLOCK CYCLES

SYMBOL

DEFINITION

MIN

CA DATA SETUP TIME

6.5ns

CA DATA HOLD TIME

2ns

CA CLOCK PULSE HIGH

9ns

CA CLOCK PERIOD

25ns

CA ENABLE SETUP TIME

17ns

CA ENABLE HOLD TIME

2.0ns

Figure 40. Programmable Cable Driver Amplifier Output Control Interface Timing

AD9856

REV. B

POWER DISSIPATION CONSIDERATIONS

The majority of the AD9856 power dissipation comes from
digital switching currents. As such, power dissipation is highly
dependent upon chip configuration.

Obviously, the major contributor to switching current is the
maximum clock rate at which the device is operated, but other
factors can play a significant role. Factors such as the CIC inter-
polation rate, and whether the third half-band filter and inverse
SINC filters are active, can affect the power dissipation of the
device.

It is important for the user to consider all of these factors when
optimizing performance for power dissipation. For example,
there are two ways to achieve a 6 MS/s transmission rate with
the AD9856. The first method uses an f

MAX

of 192 MHz; the

other method uses an f

MAX

of 144 MHz, which reduces power

dissipation by nearly 25%.

For the first method, the input data must be externally 4

up-

sampled. The AD9856 must be configured for a CIC interpola-
tion rate of three while bypassing the 3rd half-band filter. This
results in an I/Q input sample rate of 24 MHz which is further
upsampled by a factor of 8 to 192 MHz.

The second method requires an f

MAX

of 144 MHz with exter-

nally 2

upsampled input data. The AD9856 is configured for

a CIC interpolation rate of 3 while bypassing the 3rd half-band
filter. The input I/Q sample rate is 12 MHz, which is further
upsampled by a factor of 12 MHz to 144 MHz.

For burst applications with relatively long nonbursting periods,
the sleep bit is useful for saving power. When in sleep mode,
power is reduced to below 6 mW. Consideration must be given
to wake-up time, which will generally be in the 400

s to 750

range. For those applications that cannot use the sleep bit due
to this wake-up time, there is an alternate method of reducing
power dissipation when not transmitting. By writing the "Bypass
REFCLK Multiplier" bit active, the power is reduced by nearly
the REFCLK Multiplier factor. For example, if the external
reference clock is 16 MHz and REFCLK Multiplier is set to
10

, all clocks will divide down by a factor of 10 when the

REFCLK Multiplier is bypassed. This effectively scales down

the power dissipation by nearly a factor of 10. In this case, both
the REFCLK Multiplier function and the DAC, which use
relatively little power, remain fully powered. The REFCLK
Multiplier circuit is locked to the 16 MHz external reference
clock but its output is driving a very small load, hence very
little power dissipation. When the REFCLK Multiplier is reacti-
vated, the acquisition time is small. In this power-reduction
technique, the larger the REFCLK Multiplier factor, the larger
the power savings.

The AD9856 is specified for operation at +3.0 V

5% and the

thermal impedance of the AD9856 in the 48-LQFP plastic
package is 38

C/W. At 200 MHz operation, power dissipation is

1.5 W. This permits operation over the industrial temperature
range without exceeding the maximum junction temperature of
150

C. To realize this quoted thermal impedance, all power and

ground pins must be soldered down to a multilayer PCB with
power and ground copper planes directly available at the pack-
age pins.

Under worst case conditions, that is, with power supplies at
+2.85 V and ambient temperatures of +85

C, device operation

at 200 MHz is guaranteed for single tone mode only. For modu-
lation mode at 200 MHz, +85

C operation, the minimum power

supply voltage is +3.0 V.

AD9856 EVALUATION BOARD

An evaluation board is available for the AD9856 quadrature
digital upconverter that facilitates bench and system analysis
of the device. The AD9856/PCB contains the AD9856 device
and Windows software that allows control of the device via the
printer port of a PC. The DAC output is provided on a jack for
spectral analysis. The AD9856/PCB circuit board provides a
single-ended 65 MHz, 50

, elliptical low-pass filter on the out-

put of the DAC.

There is also a provision for the user to implement the AD8320/
AD8321 programmable cable driver amplifier on the AD9856/
PCB evaluation board. The AD8320/AD8321 gain is programmed
through the AD9856 via the menu driven control software.

AD9856

REV. B

DVDD

+12V

+3.3V

GND

10 F

C29

0.1 F

C24

0.1 F

C30

0.1 F

C31

0.1 F

10 F

C27

0.1 F

C22

0.1 F

C25

0.1 F

C14

0.1 F

C20

0.1 F

10 F

AVDD

GND

2Y4
2Y3
2Y2
2Y1
1Y4
1Y3
1Y2
1Y1

2A4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
GND

74HC244A

1G 2G

+3.3V

GND

+3.3V

74HC132

1A
1B
1Y
2A
2B
2Y
DGND

DVDD

4B
4A

3B
3A

RBE

+3.3V
RBE

SDIO

+3.3V

SDO

GND

74HC125A

1G
1A
1Y
2G
2A
2Y
GND

RBE

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

CLOCK

OE
D0
D1
D2
D3
D4
D5
D6
D7
GND

74HC574

+3.3V

R8
10k

+3.3V

R11
10k

R10
10k

SCLK

SYNC I/O
RST

PS0
PS1

GND

RBE

+3.3V

RBE

LATCH
SCLK
SDIO

RST
SYNC I/O

E23

E24

E16

E17

E18

E19

48 47 46 45 44 43 42 41 40 39 38 37

RST

SYNC I/O

SCLK

SDO

J14

CACLK

R7
50

PS0

PS1

CAENB

R1
3.92

GND

DVDD

C17
7pF

C18

33pF

C19

22pF

120nH

100nH

C10

68pF

C11

100pF

C12

82pF

C13

56pF

C16

0.01 F

1.3k

C15
0.1 F

13 THRU

20 ARE NC

21 THRU

40 ARE GND

TxENABLE
D11
D10
DVDD
DGND
D9
D8
D7
D6
DVDD
DGND
D5

CA DATA

CA ENABLE

PLL SUPPLY

PLL FILTER

PLL GND

AGND

OUT

OUTB

AGND

AVDD

DAC REF BYPASS

DAC R

SET

J10

RESET

REFCLK

PS1

PS0

DVDD

DGND

SYNC I

/
O

SCLK

SDIO

SDO

CA CLK

DGND

DVDD

AGND

BG REF

BYPASS

13 14 15 16 17 18 19 20 21 22 23 24

GND

DVDD

GND

DVDD

DUT

AD9856

SDIO

J15

GND

CADAT

AVDD

C9
0.1 F

AVDD

R4
50

DVDD

C7
0.1 F

AVDD

GND

E14

E15

E12

E13

E10

E11

GND

+3.3V

+12V

AVDD

DVDD

W10

E25

E26

+3.3V

CADATA

VCC1

VIN

VREF

VCC

GND 1
GND 2

BYP

GND 3
GND 4
GND 5

SDATA
CLK

DATEN

GND
VOCM

+12V
+12V
+12V
VOUT

AD8320/21

C28
0.1 F

+12V

CACLK

CAEN

J13

+12V

J12

C23

0.1 F

OUTPUT

J11

GND

W11

PODN

R6
1.3k

C26

0.1 F

C21

0.1 F

E20

E21

E22

REFCLKIN

TxENABLE

RBE

SDO

65MHz
LOW PASS
FILTER

POWER
DOWN
CONTROL

50
INPUT

0.1 F

RESET

NC = NO CONNECT

Figure 41. AD9856/PCB Evaluation Board Electrical Schematic

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