REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADG428/ADG429
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
FUNCTIONAL BLOCK DIAGRAMS
LC
2
MOS Latchable 4-/8-Channel
High Performance Analog Multiplexers
FEATURES
44 V Supply Maximum Ratings
V
SS
to V
DD
Analog Signal Range
Low On Resistance (60
typ)
Low Power Consumption (1.6 mW max)
Low Charge Injection (<4 pC typ)
Fast Switching
Break-Before-Make Switching Action
Plug-In Replacement for DG428/DG429
APPLICATIONS
Automatic Test Equipment
Data Acquisition Systems
Communication Systems
Avionics and Military Systems
Microprocessor Controlled Analog Systems
Medical Instrumentation
GENERAL DESCRIPTION
The ADG428 and ADG429 are monolithic CMOS analog
multiplexers comprising eight single channels and four differen-
tial channels respectively. On-chip address and control latches
facilitate microprocessor interfacing. The ADG428 switches one
of eight inputs to a common output as determined by the 3-bit
binary address lines A0, A1 and A2. The ADG429 switches one
of four differential inputs to a common differential output as
determined by the 2-bit binary address lines A0 and A1. An EN
input on both devices is used to enable or disable the device.
When disabled, all channels are switched OFF. All the control
inputs, address and enable inputs are TTL compatible over the
full specified operating temperature range. This makes the part
suitable for bus-controlled systems such as data acquisition sys-
tems, process controls, avionics and ATEs because the TTL-
compatible address latches simplify the digital interface design
and reduce the board space required.
The ADG428/ADG429 are designed on an enhanced LC
2
MOS
process that provides low power dissipation yet gives high switching
speed and low on resistance. Each channel conducts equally well
in both directions when ON and has an input signal range that
extends to the supplies. In the OFF condition, signal levels up to
the supplies are blocked. All channels exhibit break-before-make
switching action, preventing momentary shorting when switching
channels. Inherent in the design is low charge injection for mini-
mum transients when switching the digital inputs.
The ADG428/ADG429 are improved replacements for the
DG428/DG429 Analog Multiplexers.
PRODUCT HIGHLIGHTS
1. Extended Signal Range
The ADG428/ADG429 are fabricated on an enhanced
LC
2
MOS process, giving an increased signal range that ex-
tends to the supply rails.
2. Low Power Dissipation
3. Low R
ON
4. Single/Dual Supply Operation
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG428/ADG429 can be operated from a single rail power
supply. The parts are fully specified with a single +12 V
power supply and will remain functional with single supplies
as low as +5 V.
ADG428
DECODERS/DRIVERS
LATCHES
WR
S1
S8
RS
D
A2
A1
A0
EN
DA
S1A
S4A
ADG429
DECODERS/DRIVERS
A1
A0
EN
DB
S1B
S4B
LATCHES
WR
RS
REV. C
2
ADG428/ADG429SPECIFICATIONS
DUAL SUPPLY
1
B Version
T Version
40 C to
55 C to
Parameter
+25 C +85 C
+25 C +125 C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
V
SS
to V
DD
V
SS
to V
DD
V
R
ON
60
60
typ
V
D
=
10 V, I
S
= 1 mA
100
125
100
125
max
R
ON
10
10
% max
10 V < V
S
< 10 V, I
S
= 1 mA
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF)
0.03
0.3
0.03
0.3
nA typ
V
D
=
10 V, V
S
= 10 V;
0.5
50
0.5
50
nA max
Test Circuit 2
Drain OFF Leakage I
D
(OFF)
V
D
=
10 V, V
S
= 10 V;
ADG428
0.07
0.7
0.07
0.7
nA typ
Test Circuit 3
1
100
1
100
nA max
ADG429
0.05
0.5
0.05
0.5
nA typ
1
50
1
50
nA max
Channel ON Leakage I
D
, I
S
(ON)
V
S
= V
D
=
10 V;
ADG428
1
100
1
100
nA max
Test Circuit 4
ADG429
1
50
1
50
nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.4
2.4
V min
Input Low Voltage, V
INL
0.8
0.8
V max
Input Current
I
INL
or I
INH
0.1
1
0.1
1
A max
V
IN
= 0 or V
DD
C
IN
, Digital Input Capacitance
8
8
pF typ
f = 1 MHz
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
110
110
ns typ
R
L
= 1 M
, C
L
= 35 pF;
250
300
250
300
ns max
V
S1
=
10 V, V
S8
= 10 V;
Test Circuit 5
t
OPEN
10
10
ns min
R
L
= 1 k
, C
L
= 35 pF;
V
S
= +5 V; Test Circuit 6
t
ON
(EN,
WR)
115
115
ns typ
R
L
= 1 k
, C
L
= 35 pF;
150
225
150
225
ns max
V
S
= +5 V; Test Circuit 7
t
OFF
(EN,
RS)
105
105
ns typ
R
L
= 1 k
, C
L
= 35 pF;
150
300
150
300
ns max
V
S
= +5 V; Test Circuit 7
t
W
, Write Pulsewidth
100
100
ns min
t
S
, Address, Enable Setup Time
100
100
ns min
t
H
, Address, Enable Hold Time
10
10
ns min
t
RS
, Reset Pulsewidth
100
100
ns min
V
S
= +5 V
Charge Injection
4
4
pC typ
V
S
= 0 V, R
S
= 0
, C
L
= 10 nF;
Test Circuit 10
OFF Isolation
75
75
dB typ
R
L
= 1 k
, C
L
= 15 pF, f = 100 kHz;
60
60
dB min
V
S
= 7 V rms, V
EN
= 0 V; Test Circuit 11
Channel-to-Channel Crosstalk
85
85
dB typ
R
L
= 1 k
, C
L
= 15 pF, f = 100 kHz;
Test Circuit 12
C
S
(OFF)
11
11
pF typ
f = 1 MHz
C
D
(OFF)
f = 1 MHz
ADG428
40
40
pF typ
ADG429
20
20
pF typ
C
D
, C
S
(ON)
f = 1 MHz
ADG428
54
54
pF typ
ADG429
34
34
pF typ
POWER REQUIREMENTS
V
IN
= 0 V, V
EN
= 0 V
I
DD
20
20
A typ
100
100
A max
I
SS
0.001
0.001
A typ
5
5
A max
NOTES
1
Temperature ranges are as follows: B Version: 40
C to +85
C; T Version: 55
C to +125
C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(V
DD
= +15 V, V
SS
= 15 V, GND = 0 V,
WR = 0 V, RS = 2.4 V unless otherwise noted)
REV. C
3
ADG428/ADG429
SINGLE SUPPLY
1
B Version
T Version
40 C to
55 C to
Parameter
+25 C
+85 C
+25 C
+125 C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 to V
DD
0 to V
DD
V
R
ON
90
90
typ
V
D
= +10 V, I
S
= 500
A
200
200
max
R
ON
10
10
% max
0 V < V
S
< 10 V, I
S
= 1 mA
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF)
0.005
0.005
nA typ
V
D
= 10 V/0 V, V
S
= 0 V/10 V;
0.5
50
0.5
50
nA max
Test Circuit 2
Drain OFF Leakage I
D
(OFF)
V
D
= 10 V/0 V, V
S
= 0 V/10 V;
ADG428
0.015
0.015
nA typ
Test Circuit 3
1
100
1
100
nA max
ADG429
0.008
0.008
nA typ
1
50
1
50
nA max
Channel ON Leakage I
D
, I
S
(ON)
V
S
= V
D
= 10 V/0 V;
ADG428
0.02
0.02
nA typ
Test Circuit 4
1
100
1
100
nA max
ADG429
0.01
0.01
nA max
1
50
1
50
nA max
DIGITAL INPUTS
Input High Voltage, V
INH
2.4
2.4
V min
Input Low Voltage, V
INL
0.8
0.8
V max
Input Current
I
INL
or I
INH
1
1
A max
V
IN
= 0 or V
DD
C
IN
, Digital Input Capacitance
8
8
pF typ
f = 1 MHz
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
250
250
ns typ
R
L
= 1 M
, C
L
= 35 pF;
350
450
350
450
ns max
V
S1
= 10 V/0 V, V
S8
= 0 V/10 V;
Test Circuit 5
t
OPEN
25
10
25
10
ns min
R
L
= 1 k
, C
L
= 35 pF;
V
S
= +5 V; Test Circuit 6
t
ON
(EN,
WR)
200
200
ns typ
R
L
= 1 k
, C
L
= 35 pF;
300
400
300
400
ns max
V
S
= +5 V; Test Circuit 7
t
OFF
(EN,
RS)
80
80
ns typ
R
L
= 1 k
, C
L
= 35 pF;
300
400
300
400
ns max
V
S
= +5 V; Test Circuit 7
t
W
, Write Pulsewidth
100
100
ns min
t
S
, Address, Enable Setup Time
100
100
ns min
t
H
, Address, Enable Hold Time
10
10
ns min
t
RS
, Reset Pulsewidth
100
100
ns min
V
S
= +5 V
Charge Injection
4
4
pC typ
V
S
= 6 V, R
S
= 0
, C
L
= 10 nF;
Test Circuit 10
OFF Isolation
75
75
dB typ
R
L
= 1 k
, C
L
= 15 pF, f = 100 kHz;
60
60
dB min
V
S
= 7 V rms, V
EN
= 0 V; Test Circuit 11
Channel-to-Channel Crosstalk
85
85
dB typ
R
L
= 1 k
, C
L
= 15 pF, f = 100 kHz;
Test Circuit 12
C
S
(OFF)
11
11
pF typ
f = 1 MHz
C
D
(OFF)
f = 1 MHz
ADG428
40
40
pF typ
ADG429
20
20
pF typ
C
D
, C
S
(ON)
f = 1 MHz
ADG428
54
54
pF typ
ADG429
34
34
pF typ
POWER REQUIREMENTS
V
IN
= 0 V, V
EN
= 0 V
I
DD
20
20
A typ
100
100
A max
NOTES
1
Temperature ranges are as follows: B Version: 40
C to +85
C; T Version: 55
C to +125
C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(V
DD
= +12 V, V
SS
= 0 V, GND = 0 V,
WR = 0 V, RS = 2.4 V unless otherwise noted)
REV. C
ADG428/ADG429
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG428/ADG429 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25
C unless otherwise noted.)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 25 V
Analog, Digital Inputs
2
. . . . . . . . . . V
SS
2 V to V
DD
+ 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . 40
C to +85
C
Extended (T Version) . . . . . . . . . . . . . . . . 55
C to +125
C
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150
C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 73
C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300
C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115
C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260
C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215
C
PLCC Package, Power Dissipation . . . . . . . . . . . . . . . 800 mW
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at A, EN,
WR, RS, S or D will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
ORDERING GUIDE
Model
1
Temperature Range
Package Options
2
ADG428BN
40
C to +85
C
N-18
ADG428BP
40
C to +85
C
P-20A
ADG428BR
40
C to +85
C
R-18
ADG428TQ
55
C to +125
C
Q-18
ADG429BN
40
C to +85
C
N-18
ADG429BP
40
C to +85
C
P-20A
ADG429TQ
55
C to +125
C
Q-18
NOTES
1
For availability of MIL-STD-883, Class B processed parts, contact factory.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip;
R = Small Outline IC (SOIC).
ADG429 PIN CONFIGURATIONS
DIP/SOIC
PLCC
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
ADG428
D
S4
WR
A0
EN
V
SS
S3
S2
S1
S8
S7
RS
A1
A2
GND
S6
S5
V
DD
3 2 1 20 19
9 10 11 12 13
18
17
16
15
14
4
5
6
7
8
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
NC = NO CONNECT
EN
V
SS
S1
S2
S3
A2
GND
V
DD
S5
S6
ADG428
A0
WR
NC
RS
A1
S4
D
NC
S8
S7
DIP
PLCC
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
ADG429
DA
S4A
WR
A0
EN
V
SS
S3A
S2A
S1A
DB
S4B
RS
A1
GND
V
DD
S3B
S2B
S1B
3 2 1 20 19
9 10 11 12 13
18
17
16
15
14
4
5
6
7
8
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
NC = NO CONNECT
EN
V
SS
S1A
S2A
S3A
GND
V
DD
S1B
S2B
S3B
ADG429
A0
WR
NC
RS
A1
S4A
DA
NC
DB
S4B
ADG428 PIN CONFIGURATIONS
REV. C
ADG428/ADG429
5
ADG428 Truth Table
A2
A1
A0
EN
WR RS
ON SWITCH
Latching
X
X
X
X
g
1
Maintains Previous
Switch Condition
Reset
X
X
X
X
X
0
NONE
(Latches Cleared)
Transparent Operation
X
X
X
0
0
1
NONE
0
0
0
1
0
1
1
0
0
1
1
0
1
2
0
1
0
1
0
1
3
0
1
1
1
0
1
4
1
0
0
1
0
1
5
1
0
1
1
0
1
6
1
1
0
1
0
1
7
1
1
1
1
0
1
8
ADG429 Truth Table
A1
A0
EN
WR
RS
ON SWITCH PAIR
Latching
X
X
X
g
1
Maintains Previous
Switch Condition
Reset
X
X
X
X
0
NONE
(Latches Cleared)
Transparent Operation
X
X
0
0
1
NONE
0
0
1
0
1
1
0
1
1
0
1
2
1
0
1
0
1
3
1
1
1
0
1
4
TERMINOLOGY
V
DD
Most positive power supply potential.
V
SS
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
GND
Ground (0 V) reference.
R
ON
Ohmic resistance between D and S.
R
ON
Difference between the R
ON
of any two
channels.
I
S
(OFF)
Source leakage current when the switch is off.
I
D
(OFF)
Drain leakage current when the switch is off.
I
D
, I
S
(ON)
Channel leakage current when the switch is
on.
V
D
(V
S
)
Analog voltage on terminals D, S.
C
S
(OFF)
Channel input capacitance for "OFF"
condition.
C
D
(OFF)
Channel output capacitance for "OFF"
condition.
C
D
, C
S
(ON)
"ON" switch capacitance.
C
IN
Digital input capacitance.
t
ON
(EN)
Delay time between the 50% and 90% points
of the digital input and switch "ON"
condition.
t
OFF
(EN)
Delay time between the 50% and 90% points
of the digital input and switch "OFF"
condition.
t
TRANSITlON
Delay time between the 50% and 90% points
of the digital inputs and the switch "ON"
condition when switching from one address
state to another.
t
OPEN
"OFF" time measured between 80% points of
both switches when switching from one
address state to another.
V
INL
Maximum input voltage for Logic "0."
V
INH
Minimum input voltage for Logic "1."
I
INL
(I
INH
)
Input current of the digital input.
Crosstalk
A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling
through an "OFF" channel.
Charge
A measure of the glitch impulse transferred
Injection
from the digital input to the analog output
during switching.
I
DD
Positive supply current.
I
SS
Negative supply current.
REV. C
ADG428/ADG429
6
TIMING DIAGRAMS
3V
WR
0V
3V
A0, A1, (A2)
EN
0V
50%
50%
t
W
t
S
t
H
2V
0.8V
Figure 1.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while
WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of
WR.
50%
50%
3V
RS
0V
V
O
SWITCH
OUTPUT
0V
0.8V
O
t
RS
t
OFF
(
RS
)
Figure 2.
Figure 2 shows the Reset Pulsewidth, t
RS
, and the Reset Turnoff
Time, t
OFF
, (
RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. tr = tf = 20 ns.
Typical Characteristics
V
D
(V
S
) Volts
140
40
15
15
10
R
ON
5
0
5
10
130
100
70
80
V
DD
= +15V
V
SS
= 15V
60
50
120
110
90
T
A
= +25 C
V
DD
= +5V
V
SS
= 5V
V
DD
= +12V
V
SS
= 12V
V
DD
= +10V
V
SS
= 10V
Figure 3. R
ON
as a Function of V
D
(V
S
): Dual Supply
Voltage
V
D
(V
S
) Volts
80
40
R
ON
75
60
55
50
45
70
65
15
15
10
5
0
5
10
V
DD
= +15V
V
SS
= 15V
+125 C
+85 C
+25 C
Figure 4. R
ON
as a Function of V
D
(V
S
) for Different
Temperatures
V
D
(V
S
) Volts
600
550
100
0
15
3
6
9
12
400
250
200
150
500
450
300
350
R
ON
50
0
T
A
= +25 C
V
DD
= +12V
V
SS
= 0V
V
DD
= +10V
V
SS
= 0V
V
DD
= +5V
V
SS
= 0V
V
DD
= +15V
V
SS
= 0V
Figure 5. R
ON
as a Function of V
D
(V
S
): Single Supply
Voltage
V
D
(V
S
) Volts
160
60
0
15
2
R
ON
4
6
8
10
150
120
90
80
70
140
130
110
100
V
DD
= +12V
V
SS
= 0V
+125 C
+25 C
+85 C
Figure 6. R
ON
as a Function of V
D
(V
S
) for Different
Temperatures
REV. C
ADG428/ADG429
7
SWITCHING FREQUENCY Hz
6000
1000
10
10M
100
I
DD
A
1k
10k
100k
1M
5500
4000
2500
2000
1500
5000
4500
3500
3000
500
0
V
DD
= +15V
V
SS
= 15V
EN = 2.4V
EN = 0V
Figure 7. Positive Supply Current vs. Switching Frequency
V
IN
Volts
1
15
3
5
7
9
11
13
130
50
t ns
120
90
80
70
60
110
100
V
DD
= +15V
V
SS
= 15V
t
ON
(EN)
t
TRANSITION
t
OFF
(EN)
Figure 8. Switching Time vs. V
IN
(Bipolar Supply)
V
SUPPLY
Volts
300
275
50
5
15
7
9
11
13
200
125
100
75
250
225
150
175
t ns
25
0
V
IN
= +5V
t
ON
(EN)
t
TRANSITION
t
OFF
(EN)
Figure 9. Switching Time vs. Bipolar Supply
V
DD
= +15V
V
SS
= 15V
SWITCHING FREQUENCY Hz
1000
100
0.1
10
10M
100
I
SS
A
1k
10k
100k
1M
10
1
EN = 2.4V
EN = 0V
Figure 10. Negative Supply Current vs. Switching
Frequency
V
IN
Volts
200
40
t ns
180
120
100
80
60
160
140
1
13
3
5
7
9
11
t
OFF
(EN)
t
TRANSITION
t
ON
(EN)
V
DD
= +12V
V
SS
= 0V
Figure 11. Switching Time vs. V
IN
(Single Supply)
V
SUPPLY
Volts
500
200
0
5
15
6
t ns
7
8
9
10
11
12
13
14
450
250
150
50
350
300
100
400
V
IN
= +5V
t
ON
(EN)
t
TRANSITION
t
OFF
(EN)
Figure 12. Switching Time vs. Single Supply
REV. C
ADG428/ADG429
8
FREQUENCY Hz
100
95
50
100
10M
1k
10k
100k
1M
80
65
60
55
90
85
70
75
OFF ISOLATION dB
45
40
V
DD
= +15V
V
SS
= 15V
Figure 13. OFF Isolation vs. Frequency
V
D
(V
S
) Volts
0.2
0.1
15
15
10
LEAKAGE CURRENT nA
5
0
5
10
0.1
0
V
DD
= +15V
V
SS
= 15V
T
A
= +25 C
I
D
(ON)
I
D
(OFF)
I
S
(OFF)
Figure 14. Leakage Currents as a Function of V
D
(V
S
)
FREQUENCY Hz
110
105
60
1k
10k
100k
90
75
70
65
100
95
80
85
CROSSTALK dB
55
50
V
DD
= +15V
V
SS
= 15V
1M
10M
Figure 15. Crosstalk vs. Frequency
V
D
(V
S
) Volts
0.04
0.04
LEAKAGE CURRENT nA
0.03
0
0.01
0.02
0.03
0.02
0.01
0
12
2
4
6
8
10
V
DD
= +12V
V
SS
= 0V
T
A
= +25 C
I
D
(OFF)
I
S
(OFF)
I
D
(ON)
Figure 16. Leakage Currents as a Function of V
D
(V
S
)
REV. C
ADG428/ADG429
9
TEST CIRCUITS
I
DS
V1
S
D
V
S
R
ON
= V1/I
DS
Test Circuit 1. On Resistance
S1
D
S2
S8
A
EN
GND
V
DD
V
SS
V
DD
V
SS
+0.8V
V
D
V
S
I
S
(OFF)
Test Circuit 2. I
S
(OFF)
S1
D
S2
S8
A
EN
GND
V
DD
V
SS
V
DD
V
SS
+0.8V
V
D
V
S
I
D
(OFF)
Test Circuit 3. I
D
(OFF)
S1
D
S8
A
EN
GND
V
DD
V
SS
V
DD
V
SS
2.4V
V
D
V
S
I
D
(ON)
Test Circuit 4. I
D
(ON)
V
DD
V
SS
V
DD
V
SS
V
S1
V
S8
OUTPUT
ADG428*
A0
A1
A2
50
2.4V
EN
GND
S1
S2S7
S8
D
1M
35pF
*SIMILAR CONNECTION FOR ADG429
RS
V
IN
WR
3V
0V
ENABLE
DRIVE V
IN
t
TRANSITION
t
TRANSITION
OUTPUT
50%
50%
90%
90%
Test Circuit 5. Switching Time of Multiplexer, t
TRANSITION
V
DD
V
SS
V
DD
V
SS
V
S
OUTPUT
ADG428*
A0
A1
A2
50
2.4V
EN
GND
S1
S2S7
S8
D
1k
35pF
*SIMILAR CONNECTION FOR ADG429
RS
V
IN
WR
3V
0V
ADDRESS
DRIVE V
IN
OUTPUT
80%
80%
t
OPEN
Test Circuit 6. Break-Before-Make Delay, t
OPEN
REV. C
ADG428/ADG429
10
V
DD
V
SS
V
DD
V
SS
V
S
OUTPUT
ADG428*
A0
A1
A2
2.4V
EN
GND
S1
S2S8
D
1k
35pF
*SIMILAR CONNECTION FOR ADG429
RS
WR
50
V
IN
3V
0V
ENABLE DRIVE
V
IN
OUTPUT (V
O
)
0.9V
O
V
O
0V
50%
50%
0.9V
O
t
ON
(EN)
t
OFF
(EN)
Test Circuit 7. Enable Delay, t
ON
(EN), t
OFF
(EN)
V
DD
V
SS
V
DD
V
SS
V
S
OUTPUT
ADG428*
A0
A1
A2
2.4V
EN
GND
S1
S2S8
D
1k
35pF
*SIMILAR CONNECTION FOR ADG429
RS
WR
V
RS
V
WR
3V
0V
WR
OUTPUT
V
O
0V
50%
0.2V
O
t
ON
(
WR
)
Test Circuit 8. Write Turn-On Time, t
ON
(WR)
V
DD
V
SS
V
DD
V
SS
V
S
OUTPUT
ADG428*
A0
A1
A2
2.4V
EN
S1
S2S8
D
1k
35pF
*SIMILAR CONNECTION FOR ADG429
RS
V
IN
GND
WR
3V
0V
RS
OUTPUT
V
O
0V
50%
0.8V
O
t
OFF
(
RS
)
Test Circuit 9. Reset Turn-Off Time, t
OFF
(
RS)
REV. C
ADG428/ADG429
11
V
DD
V
SS
V
DD
V
SS
V
IN
ADG428*
A0
A1
A2
2.4V
EN
D
*SIMILAR CONNECTION FOR ADG429
RS
GND
WR
C
L
10nF
S
V
S
R
S
V
OUT
3V
EN
V
OUT
Q
INJ
= C
L
V
OUT
V
OUT
Test Circuit 10. Charge Injection
V
DD
V
SS
V
DD
V
SS
2.4V
ADG428
A0
A1
A2
D
RS
EN
1k
S1
V
OUT
S8
GND
WR
V
S
0V
Test Circuit 11. OFF Isolation
V
DD
V
SS
V
DD
V
SS
2.4V
ADG428
A0
A1
A2
D
RS
EN
1k
S1
V
OUT
S2
S8
GND
WR
1k
V
S
Test Circuit 12. Crosstalk
REV. C
ADG428/ADG429
12
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C1825c05/99
PRINTED IN U.S.A.
PLCC (P-20A)
3
PIN 1
IDENTIFIER
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.395 (10.02)
0.385 (9.78)
SQ
0.356 (9.04)
0.350 (8.89)
SQ
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.050
(1.27)
BSC
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.026 (0.66)
0.180 (4.57)
0.165 (4.19)
0.040 (1.01)
0.025 (0.64)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.110 (2.79)
0.085 (2.16)
Plastic DIP (N-18)
18
1
9
10
0.910 (23.12)
0.890 (22.61)
0.260 (6.61)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.020 (0.508)
0.015 (0.381)
0.180
(4.48)
MAX
0.065 (1.66)
0.045 (1.15)
0.175 (4.45)
0.120 (3.05)
0.105 (2.67)
0.095 (2.42)
0.306 (7.78)
0.294 (7.47)
0.120 (0.305)
0.008 (0.203)
0.140 (3.56)
0.120 (3.05)
Cerdip (Q-18)
18
1
9
10
0.310 (7.87)
0.220 (5.59)
PIN 1
SEATING
PLANE
0.022 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
0.840 (21.34) MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.320 (8.13)
0.290 (7.37)
0.015 (0.381)
0.008 (0.204)
SOIC (R-18)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
x 45
18
10
9
1
0.4625 (11.75)
0.4469 (11.35)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
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