FUNCTIONAL BLOCK DIAGRAMS
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG431
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG432
IN1
IN2
IN3
IN4
S1
D1
S2
D2
S3
D3
S4
D4
ADG433
SWITCHES SHOWN FOR A LOGIC "1" INPUT
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
LC
2
MOS
Precision Quad SPST Switches
ADG431/ADG432/ADG433
FEATURES
44 V Supply Maximum Ratings
15 V Analog Signal Range
Low On Resistance (<24 )
Ultralow Power Dissipation (3.9 W)
Low Leakage (<0.25 nA)
Fast Switching Times
t
ON
<165 ns
t
OFF
<130 ns
Break-Before-Make Switching Action
TTL/CMOS Compatible
Plug-in Replacement for DG411/DG412/DG413
APPLICATIONS
Audio and Video Switching
Automatic Test Equipment
Precision Data Acquisition
Battery Powered Systems
Sample Hold Systems
Communication Systems
GENERAL DESCRIPTION
The ADG431, ADG432 and ADG433 are monolithic CMOS
devices comprising four independently selectable switches. They
are designed on an enhanced LC
2
MOS process which provides
low power dissipation yet gives high switching speed and low on
resistance.
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. Fast switching speed coupled with high
signal bandwidth also make the parts suitable for video signal
switching. CMOS construction ensures ultralow power dissipa-
tion making the parts ideally suited for portable and battery
powered instruments.
The ADG431, ADG432 and ADG433 contain four indepen-
dent SPST switches. The ADG431 and ADG432 differ only in
that the digital control logic is inverted. The ADG431 switches
are turned on with a logic low on the appropriate control input,
while a logic high is required for the ADG432. The ADG433
has two switches with digital control logic similar to that of the
ADG431 while the logic is inverted on the other two switches.
Each switch conducts equally well in both directions when ON
and has an input signal range which extends to the supplies. In
the OFF condition, signal levels up to the supplies are blocked.
All switches exhibit break before make switching action for use
in multiplexer applications. Inherent in the design is low charge
injection for minimum transients when switching the digital inputs.
PRODUCT HIGHLIGHTS
1. Extended Signal Range
The ADG431, ADG432 and ADG433 are fabricated on an
enhanced LC
2
MOS process giving an increased signal range
which extends fully to the supply rails.
2. Ultralow Power Dissipation
3. Low R
ON
4. Break-Before-Make Switching
This prevents channel shorting when the switches are config-
ured as a multiplexer.
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG431, ADG432 and ADG433 can be operated from a
single rail power supply. The parts are fully specified with a
single +12 V power supply and will remain functional with
single supplies as low as +5 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
ADG431/ADG432/ADG433SPECIFICATIONS
1
Dual Supply
B Versions
T Versions
40 C to
55 C to
Parameter
+25 C
+85 C
+25 C
+125 C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
V
DD
to V
SS
V
DD
to V
SS
V
R
ON
17
17
typ
V
D
=
8.5 V, I
S
= 10 mA;
24
26
24
27
max
V
DD
= +13.5 V, V
SS
= 13.5 V
R
ON
vs. V
D
(V
S
)
15
15
% typ
R
ON
Drift
0.5
0.5
%/
C typ
R
ON
Match
5
5
% typ
V
D
= 0 V, I
S
= 10 mA
LEAKAGE CURRENTS
V
DD
= +16.5 V, V
SS
= 16.5 V
Source OFF Leakage I
S
(OFF)
0.05
0.05
nA typ
V
D
=
15.5 V, V
S
= 15.5 V;
0.25
2
0.25
15
nA max
Test Circuit 2
Drain OFF Leakage I
D
(OFF)
0.05
0.05
nA typ
V
D
=
15.5 V, V
S
= 15.5 V;
0.25
2
0.25
15
nA max
Test Circuit 2
Channel ON Leakage I
D
, I
S
(ON)
0.1
0.1
nA typ
V
D
= V
S
=
15.5 V;
0.35
3
0.35
17
nA max
Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4
2.4
V min
Input Low Voltage, V
INL
0.8
0.8
V max
Input Current
I
INL
or I
INH
0.005
0.005
A typ
V
IN
= V
INL
or V
INH
0.02
0.02
A max
C
IN
Digital Input Capacitance
9
9
pF typ
DYNAMIC CHARACTERISTICS
2
V
DD
= +15 V, V
SS
= 15 V
t
ON
90
90
ns typ
R
L
= 300
, C
L
= 35 pF;
165
175
ns max
V
S
=
10 V; Test Circuit 4
t
OFF
60
60
ns typ
R
L
= 300
, C
L
= 35 pF;
130
145
ns max
V
S
=
10 V; Test Circuit 4
Break-Before-Make Time Delay, t
D
25
25
ns typ
R
L
= 300
, C
L
= 35 pF;
(ADG433 Only)
V
S1
= V
S2
= +10 V;
Test Circuit 5
Charge Injection
5
5
pC typ
V
S
= 0 V, R
S
= 0
, C
L
= 10 nF;
Test Circuit 6
OFF Isolation
68
68
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk
85
85
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
C
S
(OFF)
9
9
pF typ
f = 1 MHz
C
D
(OFF)
9
9
pF typ
f = 1 MHz
C
D
, C
S
(ON)
35
35
pF typ
f = 1 MHz
POWER REQUIREMENTS
V
DD
= +16.5 V, V
SS
= 16.5 V
Digital Inputs = 0 V or 5 V
I
DD
0.0001
0.0001
A typ
0.1
0.2
0.1
0.2
A max
I
SS
0.0001
0.0001
A typ
0.1
0.2
0.1
0.2
A max
I
L
0.0001
0.0001
A typ
0.1
0.2
0.1
0.2
A max
Power Dissipation
7.7
7.7
W max
NOTES
1
Temperature ranges are as follows: B Versions: 40
C to +85
C; T Versions: 55
C to +125
C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. B
2
(V
DD
= +15 V 10%, V
SS
= 15 V 10%, V
L
= +5 V 10%, GND = O V, unless otherwise noted)
Truth Table (ADG431/ADG432)
ADG431 In
ADG432 In
Switch Condition
0
1
ON
1
0
OFF
Truth Table (ADG433)
Logic
Switch 1, 4
Switch 2, 3
0
OFF
ON
1
ON
OFF
Single Supply
B Versions
T Versions
40 C to
55 C to
Parameter
+25 C
+85 C
+25 C
+125 C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to V
DD
0 V to V
DD
V
R
ON
28
28
typ
0 < V
D
< 8.5 V, I
S
= 10 mA;
42
45
42
45
max
V
DD
= +10.8 V
R
ON
vs. V
D
(V
S
)
20
20
% typ
R
ON
Drift
0.5
0.5
%/
C typ
R
ON
Match
5
5
% typ
V
D
= 0 V, I
S
= 10 mA
LEAKAGE CURRENTS
V
DD
= +13.2 V
Source OFF Leakage I
S
(OFF)
0.04
0.04
nA typ
V
D
= 12.2/1 V, V
S
= 1/12.2 V;
0.25
2
0.25
15
nA max
Test Circuit 2
Drain OFF Leakage I
D
(OFF)
0.04
0.04
nA typ
V
D
= 12.2/1 V, V
S
= 1/12.2 V;
0.25
2
0.25
15
nA max
Test Circuit 2
Channel ON Leakage I
D
, Is (ON)
0.01
0.01
nA typ
V
D
= V
S
= +12.2 V/+1 V;
0.3
3
0.3
17
nA max
Test Circuit 3
DIGITAL INPUTS
Input High Voltage, V
INH
2.4
2.4
V min
Input Low Voltage, V
INL
0.8
0.8
V max
Input Current
I
INL
or I
INH
0.005
0.005
A typ
V
IN
= V
INL
or V
INH
0.01
0.01
A max
C
IN
Digital Input Capacitance
9
9
pF typ
DYNAMIC CHARACTERISTICS
2
V
DD
= +12 V, V
SS
= 0 V
t
ON
165
165
ns typ
R
L
= 300
, C
L
= 35 pF;
240
240
ns max
V
S
= +8 V; Test Circuit 4
t
OFF
60
60
ns typ
R
L
= 300
, C
L
= 35 pF;
115
115
ns max
V
S
= +8 V; Test Circuit 4
Break-Before-Make Time Delay, t
D
25
25
ns typ
R
L
= 300
, C
L
= 35 pF;
(ADG433 Only)
V
S1
= V
S2
= +10 V;
Test Circuit 5
Charge Injection
25
25
pC typ
V
S
= 0 V, R
S
= 0
, C
L
= 10 nF;
Test Circuit 6
OFF Isolation
68
68
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 7
Channel-to-Channel Crosstalk
85
85
dB typ
R
L
= 50
, C
L
= 5 pF, f = 1 MHz;
Test Circuit 8
C
S
(OFF)
9
9
pF typ
f = 1 MHz
C
D
(OFF)
9
9
pF typ
f = 1 MHz
C
D
, C
S
(ON)
35
35
pF typ
f = 1 MHz
POWER REQUIREMENTS
V
DD
= +13.2 V
Digital Inputs = 0 V or 5 V
I
DD
0.0001
0.0001
A typ
0.03
0.1
0.03
0.1
A max
I
L
0.0001
0.0001
A typ
0.03
0.1
0.03
0.1
A max
V
L
= +5.25 V
Power Dissipation
1.9
1.9
W max
NOTES
1
Temperature ranges are as follows: B Versions: 40
C to +85
C; T Versions: 55
C to +125
C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(V
DD
= +12 V 10%, V
SS
= O V, V
L
= +5 V 10%, GND = O V, unless otherwise noted)
ADG431/ADG432/ADG433
REV. B
3
ADG431/ADG432/ADG433
REV. B
4
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25
C unless otherwise noted)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to 25 V
V
L
to GND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Analog, Digital Inputs
2
. . . . . . . . . . V
SS
2 V to V
DD
+ 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . 40
C to +85
C
Extended (T Version) . . . . . . . . . . . . . . . . 55
C to +125
C
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150
C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 76
C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300
C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117
C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260
C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG431/ADG432/ADG433 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
(DIP/SOIC)
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1
D1
S1
V
SS
GND
S4
D4
IN4
IN2
D2
S2
V
DD
V
L
S3
D3
IN3
ADG431
ADG432
ADG433
ORDERING GUIDE
Model
1
Temperature Range
Package Options
2
ADG431BN
40
C to +85
C
N-16
ADG431BR
40
C to +85
C
R-16A
ADG431TQ
55
C to +125
C
Q-16
ADG431ABR
40
C to +85
C
R-16A
3
ADG432BN
40
C to +85
C
N-16
ADG432BR
40
C to +85
C
R-16A
ADG432TQ
55
C to +125
C
Q-16
ADG432ABR
40
C to +85
C
R-16A
3
ADG433BN
40
C to +85
C
N-16
ADG433BR
40
C to +85
C
R-16A
ADG433ABR
40
C to +85
C
R-16A
3
NOTES
1
To order MIL-STD-883, Class B processed parts, add /883B to T grade part numbers.
2
N = Plastic DIP; R = 0.15" Small Outline IC (SOIC); Q = Cerdip.
3
Trench isolated, latch-up proof parts. See Trench Isolation section.
TERMINOLOGY
V
DD
Most positive power supply potential.
V
SS
Most negative power supply potential in dual
supplies. In single supply applications, it may be
connected to GND.
V
L
Logic power supply (+5 V).
GND
Ground (0 V) reference.
S
Source terminal. May be an input or output.
D
Drain terminal. May be an input or output.
IN
Logic control input.
R
ON
Ohmic resistance between D and S.
R
ON
vs. V
D
(V
S
) The variation in R
ON
due to a change in the ana-
log input voltage with a constant load current.
R
ON
Drift
Change in R
ON
vs. temperature.
R
ON
Match
Difference between the R
ON
of any two switches.
I
S
(OFF)
Source leakage current with the switch "OFF."
I
D
(OFF)
Drain leakage current with the switch "OFF."
I
D
, I
S
(ON)
Channel leakage current with the switch "ON."
V
D
(V
S
)
Analog voltage on terminals D, S.
C
S
(OFF)
"OFF" switch source capacitance.
C
D
(OFF)
"OFF" switch drain capacitance.
C
D
, C
S
(ON)
"ON" switch capacitance.
C
IN
Input Capacitance to ground of a digital input.
t
ON
Delay between applying the digital control input
and the output switching on.
t
OFF
Delay between applying the digital control input
and the output switching off.
t
D
"OFF" time or "ON" time measured between the
90% points of both switches, when switching
from one address state to another.
Crosstalk
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling through an
"OFF" switch.
Charge
A measure of the glitch impulse transferred from the
Injection
digital input to the analog output during switching.
WARNING!
ESD SENSITIVE DEVICE
ADG431/ADG432/ADG433
REV. B
5
Typical Performance Graphs
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
50
40
10
20
10
R
ON
0
10
20
30
20
T
A
= +25 C
V
L
= +5V
0
V
DD
= +15V
V
SS
= 15V
V
DD
= +10V
V
SS
= 10V
V
DD
= +12V
V
SS
= 12V
V
DD
= +5V
V
SS
= 5V
Figure 1. On Resistance as a Function of V
D
(V
S
) Dual
Supplies
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
50
40
10
20
10
R
ON
0
10
20
30
20
0
V
DD
= +15V
V
SS
= 15V
V
L
= +5V
+125 C
+85 C
+25 C
Figure 2. On Resistance as a Function of
V
D
(V
S
) for Different Temperatures
TEMPERATURE C
10
0.001
20
120
40
LEAKAGE CURRENT nA
60
80
100
1
0.1
0.01
V
DD
= +15V
V
SS
= 15V
V
L
= +5V
140
V
S
= 15V
V
D
= 15V
I
S
(OFF)
I
D
(OFF)
I
D
(ON)
Figure 3. Leakage Currents as a Function of Temperature
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
50
40
10
0
5
R
ON
10
15
20
30
20
T
A
= +25 C
V
L
= +5V
0
V
DD
= +15V
V
SS
= 0V
V
DD
= +10V
V
SS
= 0V
V
DD
= +12V
V
SS
= 0V
V
DD
= +5V
V
SS
= 0V
Figure 4. On Resistance as a Function of V
D
(V
S
) Single
Supply
FREQUENCY Hz
100mA
100nA
10
10M
100
I
SUPPLY
1k
10k
100k
1M
10mA
1mA
100 A
10 A
1 A
V
DD
= +15V 4 SW
V
SS
= 15V
V
L
= +5V
1 SW
I+, I
I
L
Figure 5. Supply Current vs. Input Switching Frequency
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
0.04
0.02
0.04
20
10
LEAKAGE CURRENT nA
0
10
20
0.00
0.02
V
DD
= +15V
V
SS
= 15V
T
A
= +25 C
V
L
= +5V
I
D
(ON)
I
S
(OFF)
I
D
(OFF)
Figure 6. Leakage Currents as a Function of V
D
(V
S
)
ADG431/ADG432/ADG433
REV. B
6
FREQUENCY Hz
120
100
40
100
10M
1k
OFF ISOLATION dB
10k
100k
1M
80
60
V
DD
= +15V
V
SS
= 15V
V
L
= +5V
Figure 7. Off Isolation vs. Frequency
FREQUENCY Hz
110
100
60
100
10M
1k
CROSSTALK dB
10k
100k
1M
90
80
70
V
DD
= +15V
V
SS
= 15V
V
L
= +5V
Figure 8. Crosstalk vs. Frequency
TRENCH ISOLATION
In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors from a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode becomes forward biased. A silicon-controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current which, in turn, leads to
latch up. With trench isolation, this diode is removed, the result
being a latch-up proof switch.
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
T
R
E
N
C
H
T
R
E
N
C
H
T
R
E
N
C
H
P
+
P
+
P-CHANNEL
N
+
N
+
N-CHANNEL
P
N
V
G
V
D
V
S
V
G
V
D
V
S
Figure 9. Trench Isolation
APPLICATION
Figure 10 illustrates a precise, fast sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V
OUT
follows the input signal V
IN
. In the hold
mode, SW1 is opened and the signal is held by the hold capaci-
tor C
H
.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 30
V/
s.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network R
C
and C
C
. This compensation network also
reduces the hold time glitch while optimizing the acquisition
time. Using the illustrated op amps and component values, the
pedestal error has a maximum value of 5 mV over the
10 V
input range. Both the acquisition and settling times are 850 ns.
+15V
15V
2200pF
R
C
75
C
C
1000pF
C
H
2200pF
V
OUT
ADG431
ADG432
ADG433
SW1
SW2
S
S
D
D
+15V
+5V
15V
AD845
+15V
15V
V
IN
AD711
Figure 10. Fast, Accurate Sample-and-Hold
ADG431/ADG432/ADG433
REV. B
7
Test Circuits
I
DS
V1
S
D
V
S
R
ON
= V1/I
DS
Test Circuit 1. On Resistance
S
D
+15V
+5V
0.1 F
0.1 F
V
DD
V
L
IN
V
S
GND
V
SS
R
L
300
C
L
35pF
V
OUT
0.1 F
15V
t
ON
t
OFF
3V
50%
50%
50%
50%
3V
90%
90%
V
IN
V
IN
V
OUT
ADG431
ADG432
Test Circuit 4. Switching Times
S1
D1
+15V
+5V
0.1 F
0.1 F
V
DD
V
L
IN1, IN2
V
S1
GND
V
SS
R
L1
300
C
L1
35pF
V
OUT1
0.1 F
15V
V
S2
V
OUT2
R
L2
300
C
L2
35pF
S2
V
IN
D2
t
D
t
D
3V
50%
50%
90%
V
IN
V
OUT1
V
OUT2
90%
90%
90%
0V
0V
0V
Test Circuit 5. Break-Before-Make Time Delay
S
D
+15V
+5V
V
DD
V
L
IN
V
S
GND
V
SS
C
L
10nF
V
OUT
15V
R
S
3V
V
IN
V
OUT
V
OUT
Q
INJ
= C
L
V
OUT
Test Circuit 6. Charge Injection
S
D
V
S
A
V
D
A
I
S
(OFF)
I
D
(OFF)
Test Circuit 2. Off Leakage
S
D
V
S
V
D
A
I
D
(ON)
Test Circuit 3. On Leakage
ADG431/ADG432/ADG433
REV. B
8
C1826b011/98
PRINTED IN U.S.A.
16-Lead Cerdip
(Q-16)
16
1
8
9
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN
0.080 (2.03) MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
0.840 (21.34) MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
16-Lead Plastic DIP (Narrow)
(N-16)
16
1
8
9
0.840 (21.34)
0.745 (18.92)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.26)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
S
D
+15V
+5V
0.1 F
0.1 F
V
DD
V
L
IN
V
S
GND
V
SS
R
L
50
V
OUT
0.1 F
15V
V
IN
Test Circuit 7. Off Isolation
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead SOIC
(R-16A)
16
9
8
1
0.3937 (10.00)
0.3859 (9.80)
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0688 (1.75)
0.0532 (1.35)
0.0500
(1.27)
BSC
0.0099 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
S
D
+15V
+5V
0.1 F
0.1 F
V
DD
V
L
V
S
GND
V
SS
50
NC
0.1 F
15V
V
IN1
V
IN2
S
D
R
L
50
V
OUT
CHANNEL TO CHANNEL
CROSSTALK = 20 LOG V
S
/V
OUT
Test Circuit 8. Channel-to-Channel Crosstalk
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